[deliverable/linux.git] / arch / arm / mach-h720x / common.c

/*
 * linux/arch/arm/mach-h720x/common.c
 *
 * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
 *               2003 Robert Schwebel <r.schwebel@pengutronix.de>
 *               2004 Sascha Hauer    <s.hauer@pengutronix.de>
 *
 * common stuff for Hynix h720x processors
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/mman.h>
#include <linux/init.h>
#include <linux/interrupt.h>

#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/dma.h>
#include <asm/io.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <asm/arch/irqs.h>

#include <asm/mach/dma.h>

#if 0
#define IRQDBG(args...) printk(args)
#else
#define IRQDBG(args...) do {} while(0)
#endif

void __init arch_dma_init(dma_t *dma)
{
}

/*
 * Return usecs since last timer reload
 * (timercount * (usecs perjiffie)) / (ticks per jiffie)
 */
unsigned long h720x_gettimeoffset(void)
{
	return (CPU_REG (TIMER_VIRT, TM0_COUNT) * tick_usec) / LATCH;
}

/*
 * mask Global irq's
 */
static void mask_global_irq (unsigned int irq )
{
	CPU_REG (IRQC_VIRT, IRQC_IER) &= ~(1 << irq);
}

/*
 * unmask Global irq's
 */
static void unmask_global_irq (unsigned int irq )
{
	CPU_REG (IRQC_VIRT, IRQC_IER) |= (1 << irq);
}


/*
 * ack GPIO irq's
 * Ack only for edge triggered int's valid
 */
static void inline ack_gpio_irq(u32 irq)
{
	u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq));
	u32 bit = IRQ_TO_BIT(irq);
	if ( (CPU_REG (reg_base, GPIO_EDGE) & bit))
		CPU_REG (reg_base, GPIO_CLR) = bit;
}

/*
 * mask GPIO irq's
 */
static void inline mask_gpio_irq(u32 irq)
{
	u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq));
	u32 bit = IRQ_TO_BIT(irq);
	CPU_REG (reg_base, GPIO_MASK) &= ~bit;
}

/*
 * unmask GPIO irq's
 */
static void inline unmask_gpio_irq(u32 irq)
{
	u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq));
	u32 bit = IRQ_TO_BIT(irq);
	CPU_REG (reg_base, GPIO_MASK) |= bit;
}

static void
h720x_gpio_handler(unsigned int mask, unsigned int irq,
                 struct irq_desc *desc)
{
	IRQDBG("%s irq: %d\n", __func__, irq);
	desc = irq_desc + irq;
	while (mask) {
		if (mask & 1) {
			IRQDBG("handling irq %d\n", irq);
			desc_handle_irq(irq, desc);
		}
		irq++;
		desc++;
		mask >>= 1;
	}
}

static void
h720x_gpioa_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
	unsigned int mask, irq;

	mask = CPU_REG(GPIO_A_VIRT,GPIO_STAT);
	irq = IRQ_CHAINED_GPIOA(0);
	IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
	h720x_gpio_handler(mask, irq, desc);
}

static void
h720x_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
	unsigned int mask, irq;
	mask = CPU_REG(GPIO_B_VIRT,GPIO_STAT);
	irq = IRQ_CHAINED_GPIOB(0);
	IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
	h720x_gpio_handler(mask, irq, desc);
}

static void
h720x_gpioc_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
	unsigned int mask, irq;

	mask = CPU_REG(GPIO_C_VIRT,GPIO_STAT);
	irq = IRQ_CHAINED_GPIOC(0);
	IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
	h720x_gpio_handler(mask, irq, desc);
}

static void
h720x_gpiod_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
	unsigned int mask, irq;

	mask = CPU_REG(GPIO_D_VIRT,GPIO_STAT);
	irq = IRQ_CHAINED_GPIOD(0);
	IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
	h720x_gpio_handler(mask, irq, desc);
}

#ifdef CONFIG_CPU_H7202
static void
h720x_gpioe_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
	unsigned int mask, irq;

	mask = CPU_REG(GPIO_E_VIRT,GPIO_STAT);
	irq = IRQ_CHAINED_GPIOE(0);
	IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
	h720x_gpio_handler(mask, irq, desc);
}
#endif

static struct irq_chip h720x_global_chip = {
	.ack = mask_global_irq,
	.mask = mask_global_irq,
	.unmask = unmask_global_irq,
};

static struct irq_chip h720x_gpio_chip = {
	.ack = ack_gpio_irq,
	.mask = mask_gpio_irq,
	.unmask = unmask_gpio_irq,
};

/*
 * Initialize IRQ's, mask all, enable multiplexed irq's
 */
void __init h720x_init_irq (void)
{
	int 	irq;

	/* Mask global irq's */
	CPU_REG (IRQC_VIRT, IRQC_IER) = 0x0;

	/* Mask all multiplexed irq's */
	CPU_REG (GPIO_A_VIRT, GPIO_MASK) = 0x0;
	CPU_REG (GPIO_B_VIRT, GPIO_MASK) = 0x0;
	CPU_REG (GPIO_C_VIRT, GPIO_MASK) = 0x0;
	CPU_REG (GPIO_D_VIRT, GPIO_MASK) = 0x0;

	/* Initialize global IRQ's, fast path */
	for (irq = 0; irq < NR_GLBL_IRQS; irq++) {
		set_irq_chip(irq, &h720x_global_chip);
		set_irq_handler(irq, handle_level_irq);
		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
	}

	/* Initialize multiplexed IRQ's, slow path */
	for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) {
		set_irq_chip(irq, &h720x_gpio_chip);
		set_irq_handler(irq, handle_edge_irq);
		set_irq_flags(irq, IRQF_VALID );
	}
	set_irq_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler);
	set_irq_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler);
	set_irq_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler);
	set_irq_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler);

#ifdef CONFIG_CPU_H7202
	for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) {
		set_irq_chip(irq, &h720x_gpio_chip);
		set_irq_handler(irq, handle_edge_irq);
		set_irq_flags(irq, IRQF_VALID );
	}
	set_irq_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler);
#endif

	/* Enable multiplexed irq's */
	CPU_REG (IRQC_VIRT, IRQC_IER) = IRQ_ENA_MUX;
}

static struct map_desc h720x_io_desc[] __initdata = {
	{
		.virtual	= IO_VIRT,
		.pfn		= __phys_to_pfn(IO_PHYS),
		.length		= IO_SIZE,
		.type		= MT_DEVICE
	},
};

/* Initialize io tables */
void __init h720x_map_io(void)
{
	iotable_init(h720x_io_desc,ARRAY_SIZE(h720x_io_desc));
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-h720x/common.c
	3	*
	4	* Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
	5	* 2003 Robert Schwebel <r.schwebel@pengutronix.de>
	6	* 2004 Sascha Hauer <s.hauer@pengutronix.de>
	7	*
	8	* common stuff for Hynix h720x processors
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*
	14	*/
	15
	16	#include <linux/sched.h>
	17	#include <linux/slab.h>
	18	#include <linux/mman.h>
	19	#include <linux/init.h>
	20	#include <linux/interrupt.h>
	21
	22	#include <asm/page.h>
	23	#include <asm/pgtable.h>
	24	#include <asm/dma.h>
	25	#include <asm/io.h>
	26	#include <asm/hardware.h>
	27	#include <asm/irq.h>
	28	#include <asm/mach/irq.h>
	29	#include <asm/mach/map.h>
	30	#include <asm/arch/irqs.h>
	31
	32	#include <asm/mach/dma.h>
	33
	34	#if 0
	35	#define IRQDBG(args...) printk(args)
	36	#else
	37	#define IRQDBG(args...) do {} while(0)
	38	#endif
	39
	40	void __init arch_dma_init(dma_t *dma)
	41	{
	42	}
	43
	44	/*
	45	* Return usecs since last timer reload
	46	* (timercount * (usecs perjiffie)) / (ticks per jiffie)
	47	*/
	48	unsigned long h720x_gettimeoffset(void)
	49	{
	50	return (CPU_REG (TIMER_VIRT, TM0_COUNT) * tick_usec) / LATCH;
	51	}
	52
	53	/*
	54	* mask Global irq's
	55	*/
	56	static void mask_global_irq (unsigned int irq )
	57	{
	58	CPU_REG (IRQC_VIRT, IRQC_IER) &= ~(1 << irq);
	59	}
	60
	61	/*
	62	* unmask Global irq's
	63	*/
	64	static void unmask_global_irq (unsigned int irq )
65	{
66	CPU_REG (IRQC_VIRT, IRQC_IER) \|= (1 << irq);
67	}
68
69
70	/*
71	* ack GPIO irq's
72	* Ack only for edge triggered int's valid
73	*/
74	static void inline ack_gpio_irq(u32 irq)
75	{
76	u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq));
77	u32 bit = IRQ_TO_BIT(irq);
78	if ( (CPU_REG (reg_base, GPIO_EDGE) & bit))
79	CPU_REG (reg_base, GPIO_CLR) = bit;
80	}
81
82	/*
83	* mask GPIO irq's
84	*/
85	static void inline mask_gpio_irq(u32 irq)
86	{
87	u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq));
88	u32 bit = IRQ_TO_BIT(irq);
89	CPU_REG (reg_base, GPIO_MASK) &= ~bit;
90	}
91
92	/*
93	* unmask GPIO irq's
94	*/
95	static void inline unmask_gpio_irq(u32 irq)
96	{
97	u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq));
98	u32 bit = IRQ_TO_BIT(irq);
99	CPU_REG (reg_base, GPIO_MASK) \|= bit;
100	}
101
102	static void
103	h720x_gpio_handler(unsigned int mask, unsigned int irq,
10dd5ce2	104	struct irq_desc *desc)
1da177e4	105	{
8e86f427	106	IRQDBG("%s irq: %d\n", __func__, irq);
1da177e4 LT	107	desc = irq_desc + irq;
	108	while (mask) {
	109	if (mask & 1) {
	110	IRQDBG("handling irq %d\n", irq);
0cd61b68	111	desc_handle_irq(irq, desc);
1da177e4 LT	112	}
	113	irq++;
	114	desc++;
	115	mask >>= 1;
	116	}
	117	}
	118
	119	static void
10dd5ce2	120	h720x_gpioa_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
1da177e4 LT	121	{
	122	unsigned int mask, irq;
	123
	124	mask = CPU_REG(GPIO_A_VIRT,GPIO_STAT);
	125	irq = IRQ_CHAINED_GPIOA(0);
8e86f427	126	IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
0cd61b68	127	h720x_gpio_handler(mask, irq, desc);
1da177e4 LT	128	}
	129
	130	static void
10dd5ce2	131	h720x_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
1da177e4 LT	132	{
	133	unsigned int mask, irq;
	134	mask = CPU_REG(GPIO_B_VIRT,GPIO_STAT);
	135	irq = IRQ_CHAINED_GPIOB(0);
8e86f427	136	IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
0cd61b68	137	h720x_gpio_handler(mask, irq, desc);
1da177e4 LT	138	}
	139
	140	static void
10dd5ce2	141	h720x_gpioc_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
1da177e4 LT	142	{
	143	unsigned int mask, irq;
	144
	145	mask = CPU_REG(GPIO_C_VIRT,GPIO_STAT);
	146	irq = IRQ_CHAINED_GPIOC(0);
8e86f427	147	IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
0cd61b68	148	h720x_gpio_handler(mask, irq, desc);
1da177e4 LT	149	}
	150
	151	static void
10dd5ce2	152	h720x_gpiod_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
1da177e4 LT	153	{
	154	unsigned int mask, irq;
	155
	156	mask = CPU_REG(GPIO_D_VIRT,GPIO_STAT);
	157	irq = IRQ_CHAINED_GPIOD(0);
8e86f427	158	IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
0cd61b68	159	h720x_gpio_handler(mask, irq, desc);
1da177e4 LT	160	}
	161
	162	#ifdef CONFIG_CPU_H7202
	163	static void
10dd5ce2	164	h720x_gpioe_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
1da177e4 LT	165	{
	166	unsigned int mask, irq;
	167
	168	mask = CPU_REG(GPIO_E_VIRT,GPIO_STAT);
	169	irq = IRQ_CHAINED_GPIOE(0);
8e86f427	170	IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
0cd61b68	171	h720x_gpio_handler(mask, irq, desc);
1da177e4 LT	172	}
	173	#endif
	174
10dd5ce2	175	static struct irq_chip h720x_global_chip = {
1da177e4 LT	176	.ack = mask_global_irq,
	177	.mask = mask_global_irq,
	178	.unmask = unmask_global_irq,
	179	};
	180
10dd5ce2	181	static struct irq_chip h720x_gpio_chip = {
1da177e4 LT	182	.ack = ack_gpio_irq,
	183	.mask = mask_gpio_irq,
	184	.unmask = unmask_gpio_irq,
	185	};
	186
	187	/*
	188	* Initialize IRQ's, mask all, enable multiplexed irq's
	189	*/
	190	void __init h720x_init_irq (void)
	191	{
	192	int irq;
	193
	194	/* Mask global irq's */
	195	CPU_REG (IRQC_VIRT, IRQC_IER) = 0x0;
	196
	197	/* Mask all multiplexed irq's */
	198	CPU_REG (GPIO_A_VIRT, GPIO_MASK) = 0x0;
	199	CPU_REG (GPIO_B_VIRT, GPIO_MASK) = 0x0;
	200	CPU_REG (GPIO_C_VIRT, GPIO_MASK) = 0x0;
	201	CPU_REG (GPIO_D_VIRT, GPIO_MASK) = 0x0;
	202
	203	/* Initialize global IRQ's, fast path */
	204	for (irq = 0; irq < NR_GLBL_IRQS; irq++) {
	205	set_irq_chip(irq, &h720x_global_chip);
10dd5ce2	206	set_irq_handler(irq, handle_level_irq);
1da177e4 LT	207	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	208	}
	209
	210	/* Initialize multiplexed IRQ's, slow path */
	211	for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) {
	212	set_irq_chip(irq, &h720x_gpio_chip);
10dd5ce2	213	set_irq_handler(irq, handle_edge_irq);
1da177e4 LT	214	set_irq_flags(irq, IRQF_VALID );
	215	}
	216	set_irq_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler);
	217	set_irq_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler);
	218	set_irq_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler);
	219	set_irq_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler);
	220
	221	#ifdef CONFIG_CPU_H7202
	222	for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) {
	223	set_irq_chip(irq, &h720x_gpio_chip);
10dd5ce2	224	set_irq_handler(irq, handle_edge_irq);
1da177e4 LT	225	set_irq_flags(irq, IRQF_VALID );
	226	}
	227	set_irq_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler);
	228	#endif
	229
	230	/* Enable multiplexed irq's */
	231	CPU_REG (IRQC_VIRT, IRQC_IER) = IRQ_ENA_MUX;
	232	}
	233
	234	static struct map_desc h720x_io_desc[] __initdata = {
3e9635e4 DS	235	{
	236	.virtual = IO_VIRT,
	237	.pfn = __phys_to_pfn(IO_PHYS),
	238	.length = IO_SIZE,
	239	.type = MT_DEVICE
	240	},
1da177e4 LT	241	};
	242
	243	/* Initialize io tables */
	244	void __init h720x_map_io(void)
	245	{
	246	iotable_init(h720x_io_desc,ARRAY_SIZE(h720x_io_desc));
	247	}