ARM: 7938/1: OMAP4/highbank: Flush L2 cache before disabling
[deliverable/linux.git] / arch / arm / mach-highbank / highbank.c
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1/*
2 * Copyright 2010-2011 Calxeda, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16#include <linux/clk.h>
17#include <linux/clkdev.h>
0583fe47 18#include <linux/clocksource.h>
1dc737c4 19#include <linux/dma-mapping.h>
220e6cf7 20#include <linux/io.h>
0529e315 21#include <linux/irqchip.h>
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22#include <linux/of.h>
23#include <linux/of_irq.h>
24#include <linux/of_platform.h>
25#include <linux/of_address.h>
1dc737c4 26#include <linux/amba/bus.h>
60a66e37 27#include <linux/platform_device.h>
220e6cf7 28
dd68eb02 29#include <asm/psci.h>
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30#include <asm/hardware/cache-l2x0.h>
31#include <asm/mach/arch.h>
52530343 32#include <asm/mach/map.h>
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33
34#include "core.h"
35#include "sysregs.h"
36
37void __iomem *sregs_base;
7a2848d3 38void __iomem *scu_base_addr;
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39
40static void __init highbank_scu_map_io(void)
41{
42 unsigned long base;
43
44 /* Get SCU base */
45 asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
46
7a2848d3 47 scu_base_addr = ioremap(base, SZ_4K);
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48}
49
220e6cf7 50
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51static void highbank_l2x0_disable(void)
52{
b25f3e1c 53 outer_flush_all();
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54 /* Disable PL310 L2 Cache controller */
55 highbank_smc1(0x102, 0x0);
56}
8e56130d 57
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58static void __init highbank_init_irq(void)
59{
0529e315 60 irqchip_init();
8e56130d 61
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62 if (of_find_compatible_node(NULL, NULL, "arm,cortex-a9"))
63 highbank_scu_map_io();
64
8e56130d 65 /* Enable PL310 L2 Cache controller */
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66 if (IS_ENABLED(CONFIG_CACHE_L2X0) &&
67 of_find_compatible_node(NULL, NULL, "arm,pl310-cache")) {
68 highbank_smc1(0x102, 0x1);
69 l2x0_of_init(0, ~0UL);
70 outer_cache.disable = highbank_l2x0_disable;
71 }
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72}
73
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74static void highbank_power_off(void)
75{
c05ee88f 76 highbank_set_pwr_shutdown();
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77
78 while (1)
79 cpu_do_idle();
80}
81
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82static int highbank_platform_notifier(struct notifier_block *nb,
83 unsigned long event, void *__dev)
84{
85 struct resource *res;
86 int reg = -1;
e64bf95e 87 u32 val;
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88 struct device *dev = __dev;
89
90 if (event != BUS_NOTIFY_ADD_DEVICE)
91 return NOTIFY_DONE;
92
93 if (of_device_is_compatible(dev->of_node, "calxeda,hb-ahci"))
94 reg = 0xc;
95 else if (of_device_is_compatible(dev->of_node, "calxeda,hb-sdhci"))
96 reg = 0x18;
97 else if (of_device_is_compatible(dev->of_node, "arm,pl330"))
98 reg = 0x20;
99 else if (of_device_is_compatible(dev->of_node, "calxeda,hb-xgmac")) {
100 res = platform_get_resource(to_platform_device(dev),
101 IORESOURCE_MEM, 0);
102 if (res) {
103 if (res->start == 0xfff50000)
104 reg = 0;
105 else if (res->start == 0xfff51000)
106 reg = 4;
107 }
108 }
109
110 if (reg < 0)
111 return NOTIFY_DONE;
112
113 if (of_property_read_bool(dev->of_node, "dma-coherent")) {
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114 val = readl(sregs_base + reg);
115 writel(val | 0xff01, sregs_base + reg);
1dc737c4 116 set_dma_ops(dev, &arm_coherent_dma_ops);
e64bf95e 117 }
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118
119 return NOTIFY_OK;
120}
121
122static struct notifier_block highbank_amba_nb = {
123 .notifier_call = highbank_platform_notifier,
124};
125
126static struct notifier_block highbank_platform_nb = {
127 .notifier_call = highbank_platform_notifier,
128};
129
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130static struct platform_device highbank_cpuidle_device = {
131 .name = "cpuidle-calxeda",
132};
133
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134static void __init highbank_init(void)
135{
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136 struct device_node *np;
137
138 /* Map system registers */
139 np = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs");
140 sregs_base = of_iomap(np, 0);
141 WARN_ON(!sregs_base);
142
220e6cf7 143 pm_power_off = highbank_power_off;
a283580c 144 highbank_pm_init();
220e6cf7 145
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146 bus_register_notifier(&platform_bus_type, &highbank_platform_nb);
147 bus_register_notifier(&amba_bustype, &highbank_amba_nb);
148
220e6cf7 149 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
60a66e37 150
a410146c 151 if (psci_ops.cpu_suspend)
60a66e37 152 platform_device_register(&highbank_cpuidle_device);
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153}
154
155static const char *highbank_match[] __initconst = {
156 "calxeda,highbank",
e095c0d1 157 "calxeda,ecx-2000",
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158 NULL,
159};
160
161DT_MACHINE_START(HIGHBANK, "Highbank")
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162#if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE)
163 .dma_zone_size = (4ULL * SZ_1G),
164#endif
220e6cf7 165 .init_irq = highbank_init_irq,
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166 .init_machine = highbank_init,
167 .dt_compat = highbank_match,
00e9967e 168 .restart = highbank_restart,
220e6cf7 169MACHINE_END
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