projects / deliverable / linux.git / blame
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|---|---|---|
| 220e6cf7 RH |
1 | /* |
| 2 | * Copyright 2011 Calxeda, Inc. | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or modify it | |
| 5 | * under the terms and conditions of the GNU General Public License, | |
| 6 | * version 2, as published by the Free Software Foundation. | |
| 7 | * | |
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| 11 | * more details. | |
| 12 | * | |
| 13 | * You should have received a copy of the GNU General Public License along with | |
| 14 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
| 15 | */ | |
| 16 | #ifndef _MACH_HIGHBANK__SYSREGS_H_ | |
| 17 | #define _MACH_HIGHBANK__SYSREGS_H_ | |
| 18 | ||
| 19 | #include <linux/io.h> | |
| 7a2848d3 RH |
20 | #include <linux/smp.h> |
| 21 | #include <asm/smp_plat.h> | |
| 22 | #include <asm/smp_scu.h> | |
| 23 | #include "core.h" | |
| 220e6cf7 RH |
24 | |
| 25 | extern void __iomem *sregs_base; | |
| 26 | ||
| 27 | #define HB_SREG_A9_PWR_REQ 0xf00 | |
| 28 | #define HB_SREG_A9_BOOT_STAT 0xf04 | |
| 29 | #define HB_SREG_A9_BOOT_DATA 0xf08 | |
| 30 | ||
| 31 | #define HB_PWR_SUSPEND 0 | |
| 32 | #define HB_PWR_SOFT_RESET 1 | |
| 33 | #define HB_PWR_HARD_RESET 2 | |
| 34 | #define HB_PWR_SHUTDOWN 3 | |
| 35 | ||
| 7a2848d3 RH |
36 | #define SREG_CPU_PWR_CTRL(c) (0x200 + ((c) * 4)) |
| 37 | ||
| 38 | static inline void highbank_set_core_pwr(void) | |
| 39 | { | |
| 40 | int cpu = cpu_logical_map(smp_processor_id()); | |
| 41 | if (scu_base_addr) | |
| 42 | scu_power_mode(scu_base_addr, SCU_PM_POWEROFF); | |
| 43 | else | |
| 44 | writel_relaxed(1, sregs_base + SREG_CPU_PWR_CTRL(cpu)); | |
| 45 | } | |
| 46 | ||
| 220e6cf7 RH |
47 | static inline void hignbank_set_pwr_suspend(void) |
| 48 | { | |
| 49 | writel(HB_PWR_SUSPEND, sregs_base + HB_SREG_A9_PWR_REQ); | |
| 7a2848d3 | 50 | highbank_set_core_pwr(); |
| 220e6cf7 RH |
51 | } |
| 52 | ||
| 53 | static inline void hignbank_set_pwr_shutdown(void) | |
| 54 | { | |
| 55 | writel(HB_PWR_SHUTDOWN, sregs_base + HB_SREG_A9_PWR_REQ); | |
| 7a2848d3 | 56 | highbank_set_core_pwr(); |
| 220e6cf7 RH |
57 | } |
| 58 | ||
| 59 | static inline void hignbank_set_pwr_soft_reset(void) | |
| 60 | { | |
| 61 | writel(HB_PWR_SOFT_RESET, sregs_base + HB_SREG_A9_PWR_REQ); | |
| 7a2848d3 | 62 | highbank_set_core_pwr(); |
| 220e6cf7 RH |
63 | } |
| 64 | ||
| 65 | static inline void hignbank_set_pwr_hard_reset(void) | |
| 66 | { | |
| 67 | writel(HB_PWR_HARD_RESET, sregs_base + HB_SREG_A9_PWR_REQ); | |
| 7a2848d3 | 68 | highbank_set_core_pwr(); |
| 220e6cf7 RH |
69 | } |
| 70 | ||
| 71 | #endif |