[deliverable/linux.git] / arch / arm / mach-hisi / platmcpm.c

/*
 * Copyright (c) 2013-2014 Linaro Ltd.
 * Copyright (c) 2013-2014 Hisilicon Limited.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 */
#include <linux/init.h>
#include <linux/smp.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/memblock.h>
#include <linux/of_address.h>

#include <asm/cputype.h>
#include <asm/cp15.h>
#include <asm/cacheflush.h>
#include <asm/smp.h>
#include <asm/smp_plat.h>

#include "core.h"

/* bits definition in SC_CPU_RESET_REQ[x]/SC_CPU_RESET_DREQ[x]
 * 1 -- unreset; 0 -- reset
 */
#define CORE_RESET_BIT(x)		(1 << x)
#define NEON_RESET_BIT(x)		(1 << (x + 4))
#define CORE_DEBUG_RESET_BIT(x)		(1 << (x + 9))
#define CLUSTER_L2_RESET_BIT		(1 << 8)
#define CLUSTER_DEBUG_RESET_BIT		(1 << 13)

/*
 * bits definition in SC_CPU_RESET_STATUS[x]
 * 1 -- reset status; 0 -- unreset status
 */
#define CORE_RESET_STATUS(x)		(1 << x)
#define NEON_RESET_STATUS(x)		(1 << (x + 4))
#define CORE_DEBUG_RESET_STATUS(x)	(1 << (x + 9))
#define CLUSTER_L2_RESET_STATUS		(1 << 8)
#define CLUSTER_DEBUG_RESET_STATUS	(1 << 13)
#define CORE_WFI_STATUS(x)		(1 << (x + 16))
#define CORE_WFE_STATUS(x)		(1 << (x + 20))
#define CORE_DEBUG_ACK(x)		(1 << (x + 24))

#define SC_CPU_RESET_REQ(x)		(0x520 + (x << 3))	/* reset */
#define SC_CPU_RESET_DREQ(x)		(0x524 + (x << 3))	/* unreset */
#define SC_CPU_RESET_STATUS(x)		(0x1520 + (x << 3))

#define FAB_SF_MODE			0x0c
#define FAB_SF_INVLD			0x10

/* bits definition in FB_SF_INVLD */
#define FB_SF_INVLD_START		(1 << 8)

#define HIP04_MAX_CLUSTERS		4
#define HIP04_MAX_CPUS_PER_CLUSTER	4

#define POLL_MSEC	10
#define TIMEOUT_MSEC	1000

static void __iomem *sysctrl, *fabric;
static int hip04_cpu_table[HIP04_MAX_CLUSTERS][HIP04_MAX_CPUS_PER_CLUSTER];
static DEFINE_SPINLOCK(boot_lock);
static u32 fabric_phys_addr;
/*
 * [0]: bootwrapper physical address
 * [1]: bootwrapper size
 * [2]: relocation address
 * [3]: relocation size
 */
static u32 hip04_boot_method[4];

static bool hip04_cluster_is_down(unsigned int cluster)
{
	int i;

	for (i = 0; i < HIP04_MAX_CPUS_PER_CLUSTER; i++)
		if (hip04_cpu_table[cluster][i])
			return false;
	return true;
}

static void hip04_set_snoop_filter(unsigned int cluster, unsigned int on)
{
	unsigned long data;

	if (!fabric)
		BUG();
	data = readl_relaxed(fabric + FAB_SF_MODE);
	if (on)
		data |= 1 << cluster;
	else
		data &= ~(1 << cluster);
	writel_relaxed(data, fabric + FAB_SF_MODE);
	do {
		cpu_relax();
	} while (data != readl_relaxed(fabric + FAB_SF_MODE));
}

static int hip04_boot_secondary(unsigned int l_cpu, struct task_struct *idle)
{
	unsigned int mpidr, cpu, cluster;
	unsigned long data;
	void __iomem *sys_dreq, *sys_status;

	mpidr = cpu_logical_map(l_cpu);
	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);

	if (!sysctrl)
		return -ENODEV;
	if (cluster >= HIP04_MAX_CLUSTERS || cpu >= HIP04_MAX_CPUS_PER_CLUSTER)
		return -EINVAL;

	spin_lock_irq(&boot_lock);

	if (hip04_cpu_table[cluster][cpu])
		goto out;

	sys_dreq = sysctrl + SC_CPU_RESET_DREQ(cluster);
	sys_status = sysctrl + SC_CPU_RESET_STATUS(cluster);
	if (hip04_cluster_is_down(cluster)) {
		data = CLUSTER_DEBUG_RESET_BIT;
		writel_relaxed(data, sys_dreq);
		do {
			cpu_relax();
			data = readl_relaxed(sys_status);
		} while (data & CLUSTER_DEBUG_RESET_STATUS);
		hip04_set_snoop_filter(cluster, 1);
	}

	data = CORE_RESET_BIT(cpu) | NEON_RESET_BIT(cpu) | \
	       CORE_DEBUG_RESET_BIT(cpu);
	writel_relaxed(data, sys_dreq);
	do {
		cpu_relax();
	} while (data == readl_relaxed(sys_status));

	/*
	 * We may fail to power up core again without this delay.
	 * It's not mentioned in document. It's found by test.
	 */
	udelay(20);

	arch_send_wakeup_ipi_mask(cpumask_of(l_cpu));

out:
	hip04_cpu_table[cluster][cpu]++;
	spin_unlock_irq(&boot_lock);

	return 0;
}

static void hip04_cpu_die(unsigned int l_cpu)
{
	unsigned int mpidr, cpu, cluster;
	bool last_man;

	mpidr = cpu_logical_map(l_cpu);
	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);

	spin_lock(&boot_lock);
	hip04_cpu_table[cluster][cpu]--;
	if (hip04_cpu_table[cluster][cpu] == 1) {
		/* A power_up request went ahead of us. */
		spin_unlock(&boot_lock);
		return;
	} else if (hip04_cpu_table[cluster][cpu] > 1) {
		pr_err("Cluster %d CPU%d boots multiple times\n", cluster, cpu);
		BUG();
	}

	last_man = hip04_cluster_is_down(cluster);
	spin_unlock(&boot_lock);
	if (last_man) {
		/* Since it's Cortex A15, disable L2 prefetching. */
		asm volatile(
		"mcr	p15, 1, %0, c15, c0, 3 \n\t"
		"isb	\n\t"
		"dsb	"
		: : "r" (0x400) );
		v7_exit_coherency_flush(all);
	} else {
		v7_exit_coherency_flush(louis);
	}

	for (;;)
		wfi();
}

static int hip04_cpu_kill(unsigned int l_cpu)
{
	unsigned int mpidr, cpu, cluster;
	unsigned int data, tries, count;

	mpidr = cpu_logical_map(l_cpu);
	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
	BUG_ON(cluster >= HIP04_MAX_CLUSTERS ||
	       cpu >= HIP04_MAX_CPUS_PER_CLUSTER);

	count = TIMEOUT_MSEC / POLL_MSEC;
	spin_lock_irq(&boot_lock);
	for (tries = 0; tries < count; tries++) {
		if (hip04_cpu_table[cluster][cpu])
			goto err;
		cpu_relax();
		data = readl_relaxed(sysctrl + SC_CPU_RESET_STATUS(cluster));
		if (data & CORE_WFI_STATUS(cpu))
			break;
		spin_unlock_irq(&boot_lock);
		/* Wait for clean L2 when the whole cluster is down. */
		msleep(POLL_MSEC);
		spin_lock_irq(&boot_lock);
	}
	if (tries >= count)
		goto err;
	data = CORE_RESET_BIT(cpu) | NEON_RESET_BIT(cpu) | \
	       CORE_DEBUG_RESET_BIT(cpu);
	writel_relaxed(data, sysctrl + SC_CPU_RESET_REQ(cluster));
	for (tries = 0; tries < count; tries++) {
		cpu_relax();
		data = readl_relaxed(sysctrl + SC_CPU_RESET_STATUS(cluster));
		if (data & CORE_RESET_STATUS(cpu))
			break;
	}
	if (tries >= count)
		goto err;
	if (hip04_cluster_is_down(cluster))
		hip04_set_snoop_filter(cluster, 0);
	spin_unlock_irq(&boot_lock);
	return 1;
err:
	spin_unlock_irq(&boot_lock);
	return 0;
}

static struct smp_operations __initdata hip04_smp_ops = {
	.smp_boot_secondary	= hip04_boot_secondary,
	.cpu_die		= hip04_cpu_die,
	.cpu_kill		= hip04_cpu_kill,
};

static bool __init hip04_cpu_table_init(void)
{
	unsigned int mpidr, cpu, cluster;

	mpidr = read_cpuid_mpidr();
	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);

	if (cluster >= HIP04_MAX_CLUSTERS ||
	    cpu >= HIP04_MAX_CPUS_PER_CLUSTER) {
		pr_err("%s: boot CPU is out of bound!\n", __func__);
		return false;
	}
	hip04_set_snoop_filter(cluster, 1);
	hip04_cpu_table[cluster][cpu] = 1;
	return true;
}

static int __init hip04_smp_init(void)
{
	struct device_node *np, *np_sctl, *np_fab;
	struct resource fab_res;
	void __iomem *relocation;
	int ret = -ENODEV;

	np = of_find_compatible_node(NULL, NULL, "hisilicon,hip04-bootwrapper");
	if (!np)
		goto err;
	ret = of_property_read_u32_array(np, "boot-method",
					 &hip04_boot_method[0], 4);
	if (ret)
		goto err;
	np_sctl = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
	if (!np_sctl)
		goto err;
	np_fab = of_find_compatible_node(NULL, NULL, "hisilicon,hip04-fabric");
	if (!np_fab)
		goto err;

	ret = memblock_reserve(hip04_boot_method[0], hip04_boot_method[1]);
	if (ret)
		goto err;

	relocation = ioremap(hip04_boot_method[2], hip04_boot_method[3]);
	if (!relocation) {
		pr_err("failed to map relocation space\n");
		ret = -ENOMEM;
		goto err_reloc;
	}
	sysctrl = of_iomap(np_sctl, 0);
	if (!sysctrl) {
		pr_err("failed to get sysctrl base\n");
		ret = -ENOMEM;
		goto err_sysctrl;
	}
	ret = of_address_to_resource(np_fab, 0, &fab_res);
	if (ret) {
		pr_err("failed to get fabric base phys\n");
		goto err_fabric;
	}
	fabric_phys_addr = fab_res.start;
	sync_cache_w(&fabric_phys_addr);
	fabric = of_iomap(np_fab, 0);
	if (!fabric) {
		pr_err("failed to get fabric base\n");
		ret = -ENOMEM;
		goto err_fabric;
	}

	if (!hip04_cpu_table_init()) {
		ret = -EINVAL;
		goto err_table;
	}

	/*
	 * Fill the instruction address that is used after secondary core
	 * out of reset.
	 */
	writel_relaxed(hip04_boot_method[0], relocation);
	writel_relaxed(0xa5a5a5a5, relocation + 4);	/* magic number */
	writel_relaxed(virt_to_phys(secondary_startup), relocation + 8);
	writel_relaxed(0, relocation + 12);
	iounmap(relocation);

	smp_set_ops(&hip04_smp_ops);
	return ret;
err_table:
	iounmap(fabric);
err_fabric:
	iounmap(sysctrl);
err_sysctrl:
	iounmap(relocation);
err_reloc:
	memblock_free(hip04_boot_method[0], hip04_boot_method[1]);
err:
	return ret;
}
early_initcall(hip04_smp_init);
Commit	Line	Data
9cdc9991 HZ	1	/*
	2	* Copyright (c) 2013-2014 Linaro Ltd.
	3	* Copyright (c) 2013-2014 Hisilicon Limited.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms and conditions of the GNU General Public License,
	7	* version 2, as published by the Free Software Foundation.
	8	*/
905cdf9d NP	9	#include <linux/init.h>
905cdf9d NP	10	#include <linux/smp.h>
9cdc9991 HZ	11	#include <linux/delay.h>
	12	#include <linux/io.h>
	13	#include <linux/memblock.h>
	14	#include <linux/of_address.h>
	15
	16	#include <asm/cputype.h>
	17	#include <asm/cp15.h>
905cdf9d NP	18	#include <asm/cacheflush.h>
	19	#include <asm/smp.h>
	20	#include <asm/smp_plat.h>
9cdc9991 HZ	21
	22	#include "core.h"
	23
	24	/* bits definition in SC_CPU_RESET_REQ[x]/SC_CPU_RESET_DREQ[x]
	25	* 1 -- unreset; 0 -- reset
	26	*/
	27	#define CORE_RESET_BIT(x) (1 << x)
	28	#define NEON_RESET_BIT(x) (1 << (x + 4))
	29	#define CORE_DEBUG_RESET_BIT(x) (1 << (x + 9))
	30	#define CLUSTER_L2_RESET_BIT (1 << 8)
	31	#define CLUSTER_DEBUG_RESET_BIT (1 << 13)
	32
	33	/*
	34	* bits definition in SC_CPU_RESET_STATUS[x]
	35	* 1 -- reset status; 0 -- unreset status
	36	*/
	37	#define CORE_RESET_STATUS(x) (1 << x)
	38	#define NEON_RESET_STATUS(x) (1 << (x + 4))
	39	#define CORE_DEBUG_RESET_STATUS(x) (1 << (x + 9))
	40	#define CLUSTER_L2_RESET_STATUS (1 << 8)
	41	#define CLUSTER_DEBUG_RESET_STATUS (1 << 13)
	42	#define CORE_WFI_STATUS(x) (1 << (x + 16))
	43	#define CORE_WFE_STATUS(x) (1 << (x + 20))
	44	#define CORE_DEBUG_ACK(x) (1 << (x + 24))
	45
	46	#define SC_CPU_RESET_REQ(x) (0x520 + (x << 3)) /* reset */
	47	#define SC_CPU_RESET_DREQ(x) (0x524 + (x << 3)) /* unreset */
	48	#define SC_CPU_RESET_STATUS(x) (0x1520 + (x << 3))
	49
	50	#define FAB_SF_MODE 0x0c
	51	#define FAB_SF_INVLD 0x10
	52
	53	/* bits definition in FB_SF_INVLD */
	54	#define FB_SF_INVLD_START (1 << 8)
	55
	56	#define HIP04_MAX_CLUSTERS 4
	57	#define HIP04_MAX_CPUS_PER_CLUSTER 4
	58
	59	#define POLL_MSEC 10
	60	#define TIMEOUT_MSEC 1000
	61
	62	static void __iomem sysctrl, fabric;
	63	static int hip04_cpu_table[HIP04_MAX_CLUSTERS][HIP04_MAX_CPUS_PER_CLUSTER];
	64	static DEFINE_SPINLOCK(boot_lock);
	65	static u32 fabric_phys_addr;
	66	/*
	67	* [0]: bootwrapper physical address
	68	* [1]: bootwrapper size
	69	* [2]: relocation address
	70	* [3]: relocation size
	71	*/
	72	static u32 hip04_boot_method[4];
	73
	74	static bool hip04_cluster_is_down(unsigned int cluster)
	75	{
	76	int i;
	77
	78	for (i = 0; i < HIP04_MAX_CPUS_PER_CLUSTER; i++)
	79	if (hip04_cpu_table[cluster][i])
	80	return false;
	81	return true;
	82	}
	83
	84	static void hip04_set_snoop_filter(unsigned int cluster, unsigned int on)
85	{
86	unsigned long data;
87
88	if (!fabric)
89	BUG();
90	data = readl_relaxed(fabric + FAB_SF_MODE);
91	if (on)
92	data \|= 1 << cluster;
93	else
94	data &= ~(1 << cluster);
95	writel_relaxed(data, fabric + FAB_SF_MODE);
96	do {
97	cpu_relax();
98	} while (data != readl_relaxed(fabric + FAB_SF_MODE));
99	}
100
905cdf9d	101	static int hip04_boot_secondary(unsigned int l_cpu, struct task_struct *idle)
9cdc9991	102	{
905cdf9d	103	unsigned int mpidr, cpu, cluster;
9cdc9991 HZ	104	unsigned long data;
	105	void __iomem sys_dreq, sys_status;
	106
905cdf9d NP	107	mpidr = cpu_logical_map(l_cpu);
	108	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
	109	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
	110
9cdc9991 HZ	111	if (!sysctrl)
	112	return -ENODEV;
	113	if (cluster >= HIP04_MAX_CLUSTERS \|\| cpu >= HIP04_MAX_CPUS_PER_CLUSTER)
	114	return -EINVAL;
	115
	116	spin_lock_irq(&boot_lock);
	117
	118	if (hip04_cpu_table[cluster][cpu])
	119	goto out;
	120
	121	sys_dreq = sysctrl + SC_CPU_RESET_DREQ(cluster);
	122	sys_status = sysctrl + SC_CPU_RESET_STATUS(cluster);
	123	if (hip04_cluster_is_down(cluster)) {
	124	data = CLUSTER_DEBUG_RESET_BIT;
	125	writel_relaxed(data, sys_dreq);
	126	do {
	127	cpu_relax();
	128	data = readl_relaxed(sys_status);
	129	} while (data & CLUSTER_DEBUG_RESET_STATUS);
905cdf9d	130	hip04_set_snoop_filter(cluster, 1);
9cdc9991 HZ	131	}
	132
	133	data = CORE_RESET_BIT(cpu) \| NEON_RESET_BIT(cpu) \| \
	134	CORE_DEBUG_RESET_BIT(cpu);
	135	writel_relaxed(data, sys_dreq);
	136	do {
	137	cpu_relax();
	138	} while (data == readl_relaxed(sys_status));
905cdf9d	139
9cdc9991 HZ	140	/*
	141	* We may fail to power up core again without this delay.
	142	* It's not mentioned in document. It's found by test.
	143	*/
	144	udelay(20);
905cdf9d NP	145
	146	arch_send_wakeup_ipi_mask(cpumask_of(l_cpu));
	147
9cdc9991 HZ	148	out:
	149	hip04_cpu_table[cluster][cpu]++;
	150	spin_unlock_irq(&boot_lock);
	151
	152	return 0;
	153	}
	154
905cdf9d	155	static void hip04_cpu_die(unsigned int l_cpu)
9cdc9991 HZ	156	{
9cdc9991 HZ	157	unsigned int mpidr, cpu, cluster;
905cdf9d	158	bool last_man;
9cdc9991	159
905cdf9d	160	mpidr = cpu_logical_map(l_cpu);
9cdc9991 HZ	161	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
	162	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
	163
9cdc9991	164	spin_lock(&boot_lock);
9cdc9991 HZ	165	hip04_cpu_table[cluster][cpu]--;
	166	if (hip04_cpu_table[cluster][cpu] == 1) {
	167	/* A power_up request went ahead of us. */
905cdf9d NP	168	spin_unlock(&boot_lock);
905cdf9d NP	169	return;
9cdc9991 HZ	170	} else if (hip04_cpu_table[cluster][cpu] > 1) {
	171	pr_err("Cluster %d CPU%d boots multiple times\n", cluster, cpu);
	172	BUG();
	173	}
	174
	175	last_man = hip04_cluster_is_down(cluster);
905cdf9d NP	176	spin_unlock(&boot_lock);
905cdf9d NP	177	if (last_man) {
9cdc9991 HZ	178	/* Since it's Cortex A15, disable L2 prefetching. */
	179	asm volatile(
	180	"mcr p15, 1, %0, c15, c0, 3 \n\t"
	181	"isb \n\t"
	182	"dsb "
	183	: : "r" (0x400) );
	184	v7_exit_coherency_flush(all);
9cdc9991	185	} else {
9cdc9991 HZ	186	v7_exit_coherency_flush(louis);
	187	}
	188
905cdf9d	189	for (;;)
9cdc9991 HZ	190	wfi();
	191	}
	192
905cdf9d	193	static int hip04_cpu_kill(unsigned int l_cpu)
9cdc9991	194	{
905cdf9d	195	unsigned int mpidr, cpu, cluster;
9cdc9991	196	unsigned int data, tries, count;
9cdc9991	197
905cdf9d NP	198	mpidr = cpu_logical_map(l_cpu);
	199	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
	200	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
9cdc9991 HZ	201	BUG_ON(cluster >= HIP04_MAX_CLUSTERS \|\|
	202	cpu >= HIP04_MAX_CPUS_PER_CLUSTER);
	203
	204	count = TIMEOUT_MSEC / POLL_MSEC;
	205	spin_lock_irq(&boot_lock);
	206	for (tries = 0; tries < count; tries++) {
905cdf9d	207	if (hip04_cpu_table[cluster][cpu])
9cdc9991	208	goto err;
9cdc9991 HZ	209	cpu_relax();
	210	data = readl_relaxed(sysctrl + SC_CPU_RESET_STATUS(cluster));
	211	if (data & CORE_WFI_STATUS(cpu))
	212	break;
	213	spin_unlock_irq(&boot_lock);
	214	/* Wait for clean L2 when the whole cluster is down. */
	215	msleep(POLL_MSEC);
	216	spin_lock_irq(&boot_lock);
	217	}
	218	if (tries >= count)
	219	goto err;
	220	data = CORE_RESET_BIT(cpu) \| NEON_RESET_BIT(cpu) \| \
	221	CORE_DEBUG_RESET_BIT(cpu);
	222	writel_relaxed(data, sysctrl + SC_CPU_RESET_REQ(cluster));
	223	for (tries = 0; tries < count; tries++) {
	224	cpu_relax();
	225	data = readl_relaxed(sysctrl + SC_CPU_RESET_STATUS(cluster));
	226	if (data & CORE_RESET_STATUS(cpu))
	227	break;
	228	}
	229	if (tries >= count)
	230	goto err;
905cdf9d NP	231	if (hip04_cluster_is_down(cluster))
905cdf9d NP	232	hip04_set_snoop_filter(cluster, 0);
9cdc9991	233	spin_unlock_irq(&boot_lock);
905cdf9d	234	return 1;
9cdc9991 HZ	235	err:
9cdc9991 HZ	236	spin_unlock_irq(&boot_lock);
905cdf9d	237	return 0;
9cdc9991 HZ	238	}
9cdc9991 HZ	239
905cdf9d NP	240	static struct smp_operations __initdata hip04_smp_ops = {
	241	.smp_boot_secondary = hip04_boot_secondary,
	242	.cpu_die = hip04_cpu_die,
	243	.cpu_kill = hip04_cpu_kill,
9cdc9991 HZ	244	};
	245
	246	static bool __init hip04_cpu_table_init(void)
	247	{
	248	unsigned int mpidr, cpu, cluster;
	249
	250	mpidr = read_cpuid_mpidr();
	251	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
	252	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
	253
	254	if (cluster >= HIP04_MAX_CLUSTERS \|\|
	255	cpu >= HIP04_MAX_CPUS_PER_CLUSTER) {
	256	pr_err("%s: boot CPU is out of bound!\n", __func__);
	257	return false;
	258	}
	259	hip04_set_snoop_filter(cluster, 1);
	260	hip04_cpu_table[cluster][cpu] = 1;
	261	return true;
	262	}
	263
905cdf9d	264	static int __init hip04_smp_init(void)
9cdc9991 HZ	265	{
	266	struct device_node np, np_sctl, *np_fab;
	267	struct resource fab_res;
	268	void __iomem *relocation;
	269	int ret = -ENODEV;
	270
	271	np = of_find_compatible_node(NULL, NULL, "hisilicon,hip04-bootwrapper");
	272	if (!np)
	273	goto err;
	274	ret = of_property_read_u32_array(np, "boot-method",
	275	&hip04_boot_method[0], 4);
	276	if (ret)
	277	goto err;
	278	np_sctl = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
	279	if (!np_sctl)
	280	goto err;
	281	np_fab = of_find_compatible_node(NULL, NULL, "hisilicon,hip04-fabric");
	282	if (!np_fab)
	283	goto err;
	284
	285	ret = memblock_reserve(hip04_boot_method[0], hip04_boot_method[1]);
	286	if (ret)
	287	goto err;
	288
	289	relocation = ioremap(hip04_boot_method[2], hip04_boot_method[3]);
	290	if (!relocation) {
	291	pr_err("failed to map relocation space\n");
	292	ret = -ENOMEM;
	293	goto err_reloc;
	294	}
	295	sysctrl = of_iomap(np_sctl, 0);
	296	if (!sysctrl) {
	297	pr_err("failed to get sysctrl base\n");
	298	ret = -ENOMEM;
	299	goto err_sysctrl;
	300	}
	301	ret = of_address_to_resource(np_fab, 0, &fab_res);
	302	if (ret) {
	303	pr_err("failed to get fabric base phys\n");
	304	goto err_fabric;
	305	}
	306	fabric_phys_addr = fab_res.start;
	307	sync_cache_w(&fabric_phys_addr);
	308	fabric = of_iomap(np_fab, 0);
	309	if (!fabric) {
	310	pr_err("failed to get fabric base\n");
	311	ret = -ENOMEM;
	312	goto err_fabric;
	313	}
	314
	315	if (!hip04_cpu_table_init()) {
	316	ret = -EINVAL;
	317	goto err_table;
	318	}
9cdc9991 HZ	319
	320	/*
	321	* Fill the instruction address that is used after secondary core
	322	* out of reset.
	323	*/
	324	writel_relaxed(hip04_boot_method[0], relocation);
	325	writel_relaxed(0xa5a5a5a5, relocation + 4); /* magic number */
905cdf9d	326	writel_relaxed(virt_to_phys(secondary_startup), relocation + 8);
9cdc9991 HZ	327	writel_relaxed(0, relocation + 12);
	328	iounmap(relocation);
	329
905cdf9d	330	smp_set_ops(&hip04_smp_ops);
9cdc9991 HZ	331	return ret;
	332	err_table:
	333	iounmap(fabric);
	334	err_fabric:
	335	iounmap(sysctrl);
	336	err_sysctrl:
	337	iounmap(relocation);
	338	err_reloc:
	339	memblock_free(hip04_boot_method[0], hip04_boot_method[1]);
	340	err:
	341	return ret;
	342	}
905cdf9d	343	early_initcall(hip04_smp_init);