Commit | Line | Data |
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52c543f9 | 1 | /* |
259bcaae JB |
2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. |
3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
17 | * MA 02110-1301, USA. | |
52c543f9 QJ |
18 | */ |
19 | ||
d7927e19 | 20 | #include <linux/module.h> |
259bcaae | 21 | #include <linux/irq.h> |
544496ab | 22 | #include <linux/irqdomain.h> |
fced80c7 | 23 | #include <linux/io.h> |
544496ab | 24 | #include <linux/of.h> |
d7927e19 | 25 | #include <asm/mach/irq.h> |
98de0cbb | 26 | #include <asm/exception.h> |
52c543f9 | 27 | |
e3372474 | 28 | #include "common.h" |
50f2de61 | 29 | #include "hardware.h" |
cdc3f106 PH |
30 | #include "irq-common.h" |
31 | ||
84c9fa43 SH |
32 | #define AVIC_INTCNTL 0x00 /* int control reg */ |
33 | #define AVIC_NIMASK 0x04 /* int mask reg */ | |
34 | #define AVIC_INTENNUM 0x08 /* int enable number reg */ | |
35 | #define AVIC_INTDISNUM 0x0C /* int disable number reg */ | |
36 | #define AVIC_INTENABLEH 0x10 /* int enable reg high */ | |
37 | #define AVIC_INTENABLEL 0x14 /* int enable reg low */ | |
38 | #define AVIC_INTTYPEH 0x18 /* int type reg high */ | |
39 | #define AVIC_INTTYPEL 0x1C /* int type reg low */ | |
40 | #define AVIC_NIPRIORITY(x) (0x20 + 4 * (7 - (x))) /* int priority */ | |
41 | #define AVIC_NIVECSR 0x40 /* norm int vector/status */ | |
42 | #define AVIC_FIVECSR 0x44 /* fast int vector/status */ | |
43 | #define AVIC_INTSRCH 0x48 /* int source reg high */ | |
44 | #define AVIC_INTSRCL 0x4C /* int source reg low */ | |
45 | #define AVIC_INTFRCH 0x50 /* int force reg high */ | |
46 | #define AVIC_INTFRCL 0x54 /* int force reg low */ | |
47 | #define AVIC_NIPNDH 0x58 /* norm int pending high */ | |
48 | #define AVIC_NIPNDL 0x5C /* norm int pending low */ | |
49 | #define AVIC_FIPNDH 0x60 /* fast int pending high */ | |
50 | #define AVIC_FIPNDL 0x64 /* fast int pending low */ | |
51 | ||
5a24d69c SH |
52 | #define AVIC_NUM_IRQS 64 |
53 | ||
ae00ac76 | 54 | static void __iomem *avic_base; |
544496ab | 55 | static struct irq_domain *domain; |
259bcaae | 56 | |
d7927e19 | 57 | #ifdef CONFIG_FIQ |
cdc3f106 | 58 | static int avic_set_irq_fiq(unsigned int irq, unsigned int type) |
d7927e19 | 59 | { |
544496ab | 60 | struct irq_data *d = irq_get_irq_data(irq); |
d7927e19 PZ |
61 | unsigned int irqt; |
62 | ||
544496ab SG |
63 | irq = d->hwirq; |
64 | ||
5a24d69c | 65 | if (irq >= AVIC_NUM_IRQS) |
d7927e19 PZ |
66 | return -EINVAL; |
67 | ||
5a24d69c | 68 | if (irq < AVIC_NUM_IRQS / 2) { |
c553138f JB |
69 | irqt = imx_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq); |
70 | imx_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL); | |
d7927e19 | 71 | } else { |
5a24d69c | 72 | irq -= AVIC_NUM_IRQS / 2; |
c553138f JB |
73 | irqt = imx_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq); |
74 | imx_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH); | |
d7927e19 PZ |
75 | } |
76 | ||
77 | return 0; | |
78 | } | |
d7927e19 PZ |
79 | #endif /* CONFIG_FIQ */ |
80 | ||
52c543f9 | 81 | |
3439a397 | 82 | static struct mxc_extra_irq avic_extra_irq = { |
cdc3f106 PH |
83 | #ifdef CONFIG_FIQ |
84 | .set_irq_fiq = avic_set_irq_fiq, | |
85 | #endif | |
52c543f9 QJ |
86 | }; |
87 | ||
3439a397 | 88 | #ifdef CONFIG_PM |
5fe839d9 FE |
89 | static u32 avic_saved_mask_reg[2]; |
90 | ||
3439a397 HW |
91 | static void avic_irq_suspend(struct irq_data *d) |
92 | { | |
93 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
94 | struct irq_chip_type *ct = gc->chip_types; | |
544496ab | 95 | int idx = d->hwirq >> 5; |
3439a397 | 96 | |
c553138f JB |
97 | avic_saved_mask_reg[idx] = imx_readl(avic_base + ct->regs.mask); |
98 | imx_writel(gc->wake_active, avic_base + ct->regs.mask); | |
3439a397 HW |
99 | } |
100 | ||
101 | static void avic_irq_resume(struct irq_data *d) | |
102 | { | |
103 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
104 | struct irq_chip_type *ct = gc->chip_types; | |
544496ab | 105 | int idx = d->hwirq >> 5; |
3439a397 | 106 | |
c553138f | 107 | imx_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask); |
3439a397 HW |
108 | } |
109 | ||
110 | #else | |
111 | #define avic_irq_suspend NULL | |
112 | #define avic_irq_resume NULL | |
113 | #endif | |
114 | ||
544496ab | 115 | static __init void avic_init_gc(int idx, unsigned int irq_start) |
3439a397 HW |
116 | { |
117 | struct irq_chip_generic *gc; | |
118 | struct irq_chip_type *ct; | |
3439a397 HW |
119 | |
120 | gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base, | |
121 | handle_level_irq); | |
122 | gc->private = &avic_extra_irq; | |
123 | gc->wake_enabled = IRQ_MSK(32); | |
124 | ||
125 | ct = gc->chip_types; | |
126 | ct->chip.irq_mask = irq_gc_mask_clr_bit; | |
127 | ct->chip.irq_unmask = irq_gc_mask_set_bit; | |
128 | ct->chip.irq_ack = irq_gc_mask_clr_bit; | |
129 | ct->chip.irq_set_wake = irq_gc_set_wake; | |
130 | ct->chip.irq_suspend = avic_irq_suspend; | |
131 | ct->chip.irq_resume = avic_irq_resume; | |
132 | ct->regs.mask = !idx ? AVIC_INTENABLEL : AVIC_INTENABLEH; | |
133 | ct->regs.ack = ct->regs.mask; | |
134 | ||
135 | irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0); | |
136 | } | |
137 | ||
000bf9ee | 138 | static void __exception_irq_entry avic_handle_irq(struct pt_regs *regs) |
b6de943b SH |
139 | { |
140 | u32 nivector; | |
141 | ||
142 | do { | |
c553138f | 143 | nivector = imx_readl(avic_base + AVIC_NIVECSR) >> 16; |
b6de943b SH |
144 | if (nivector == 0xffff) |
145 | break; | |
146 | ||
9705ca3d | 147 | handle_domain_irq(domain, nivector, regs); |
b6de943b SH |
148 | } while (1); |
149 | } | |
150 | ||
2c130fd5 | 151 | /* |
52c543f9 QJ |
152 | * This function initializes the AVIC hardware and disables all the |
153 | * interrupts. It registers the interrupt enable and disable functions | |
154 | * to the kernel for each interrupt source. | |
155 | */ | |
c5aa0ad0 | 156 | void __init mxc_init_irq(void __iomem *irqbase) |
52c543f9 | 157 | { |
544496ab SG |
158 | struct device_node *np; |
159 | int irq_base; | |
52c543f9 | 160 | int i; |
52c543f9 | 161 | |
c5aa0ad0 | 162 | avic_base = irqbase; |
84c9fa43 | 163 | |
52c543f9 QJ |
164 | /* put the AVIC into the reset value with |
165 | * all interrupts disabled | |
166 | */ | |
c553138f JB |
167 | imx_writel(0, avic_base + AVIC_INTCNTL); |
168 | imx_writel(0x1f, avic_base + AVIC_NIMASK); | |
52c543f9 QJ |
169 | |
170 | /* disable all interrupts */ | |
c553138f JB |
171 | imx_writel(0, avic_base + AVIC_INTENABLEH); |
172 | imx_writel(0, avic_base + AVIC_INTENABLEL); | |
52c543f9 QJ |
173 | |
174 | /* all IRQ no FIQ */ | |
c553138f JB |
175 | imx_writel(0, avic_base + AVIC_INTTYPEH); |
176 | imx_writel(0, avic_base + AVIC_INTTYPEL); | |
3439a397 | 177 | |
544496ab SG |
178 | irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id()); |
179 | WARN_ON(irq_base < 0); | |
180 | ||
181 | np = of_find_compatible_node(NULL, NULL, "fsl,avic"); | |
182 | domain = irq_domain_add_legacy(np, AVIC_NUM_IRQS, irq_base, 0, | |
183 | &irq_domain_simple_ops, NULL); | |
184 | WARN_ON(!domain); | |
185 | ||
186 | for (i = 0; i < AVIC_NUM_IRQS / 32; i++, irq_base += 32) | |
187 | avic_init_gc(i, irq_base); | |
52c543f9 | 188 | |
479c901f DA |
189 | /* Set default priority value (0) for all IRQ's */ |
190 | for (i = 0; i < 8; i++) | |
c553138f | 191 | imx_writel(0, avic_base + AVIC_NIPRIORITY(i)); |
52c543f9 | 192 | |
000bf9ee AS |
193 | set_handle_irq(avic_handle_irq); |
194 | ||
d7927e19 PZ |
195 | #ifdef CONFIG_FIQ |
196 | /* Initialize FIQ */ | |
bc89663a | 197 | init_FIQ(FIQ_START); |
d7927e19 PZ |
198 | #endif |
199 | ||
52c543f9 QJ |
200 | printk(KERN_INFO "MXC IRQ initialized\n"); |
201 | } |