[deliverable/linux.git] / arch / arm / mach-imx / avic.c

/*
 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA  02110-1301, USA.
 */

#include <linux/module.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/io.h>
#include <linux/of.h>
#include <asm/mach/irq.h>
#include <asm/exception.h>

#include "common.h"
#include "hardware.h"
#include "irq-common.h"

#define AVIC_INTCNTL		0x00	/* int control reg */
#define AVIC_NIMASK		0x04	/* int mask reg */
#define AVIC_INTENNUM		0x08	/* int enable number reg */
#define AVIC_INTDISNUM		0x0C	/* int disable number reg */
#define AVIC_INTENABLEH		0x10	/* int enable reg high */
#define AVIC_INTENABLEL		0x14	/* int enable reg low */
#define AVIC_INTTYPEH		0x18	/* int type reg high */
#define AVIC_INTTYPEL		0x1C	/* int type reg low */
#define AVIC_NIPRIORITY(x)	(0x20 + 4 * (7 - (x))) /* int priority */
#define AVIC_NIVECSR		0x40	/* norm int vector/status */
#define AVIC_FIVECSR		0x44	/* fast int vector/status */
#define AVIC_INTSRCH		0x48	/* int source reg high */
#define AVIC_INTSRCL		0x4C	/* int source reg low */
#define AVIC_INTFRCH		0x50	/* int force reg high */
#define AVIC_INTFRCL		0x54	/* int force reg low */
#define AVIC_NIPNDH		0x58	/* norm int pending high */
#define AVIC_NIPNDL		0x5C	/* norm int pending low */
#define AVIC_FIPNDH		0x60	/* fast int pending high */
#define AVIC_FIPNDL		0x64	/* fast int pending low */

#define AVIC_NUM_IRQS 64

static void __iomem *avic_base;
static struct irq_domain *domain;

#ifdef CONFIG_MXC_IRQ_PRIOR
static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
{
	struct irq_data *d = irq_get_irq_data(irq);
	unsigned int temp;
	unsigned int mask = 0x0F << irq % 8 * 4;

	irq = d->hwirq;

	if (irq >= AVIC_NUM_IRQS)
		return -EINVAL;

	temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8));
	temp &= ~mask;
	temp |= prio & mask;

	__raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8));

	return 0;
}
#endif

#ifdef CONFIG_FIQ
static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
{
	struct irq_data *d = irq_get_irq_data(irq);
	unsigned int irqt;

	irq = d->hwirq;

	if (irq >= AVIC_NUM_IRQS)
		return -EINVAL;

	if (irq < AVIC_NUM_IRQS / 2) {
		irqt = __raw_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq);
		__raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL);
	} else {
		irq -= AVIC_NUM_IRQS / 2;
		irqt = __raw_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq);
		__raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH);
	}

	return 0;
}
#endif /* CONFIG_FIQ */


static struct mxc_extra_irq avic_extra_irq = {
#ifdef CONFIG_MXC_IRQ_PRIOR
	.set_priority = avic_irq_set_priority,
#endif
#ifdef CONFIG_FIQ
	.set_irq_fiq = avic_set_irq_fiq,
#endif
};

#ifdef CONFIG_PM
static u32 avic_saved_mask_reg[2];

static void avic_irq_suspend(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = gc->chip_types;
	int idx = d->hwirq >> 5;

	avic_saved_mask_reg[idx] = __raw_readl(avic_base + ct->regs.mask);
	__raw_writel(gc->wake_active, avic_base + ct->regs.mask);
}

static void avic_irq_resume(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = gc->chip_types;
	int idx = d->hwirq >> 5;

	__raw_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);
}

#else
#define avic_irq_suspend NULL
#define avic_irq_resume NULL
#endif

static __init void avic_init_gc(int idx, unsigned int irq_start)
{
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;

	gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base,
				    handle_level_irq);
	gc->private = &avic_extra_irq;
	gc->wake_enabled = IRQ_MSK(32);

	ct = gc->chip_types;
	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	ct->chip.irq_ack = irq_gc_mask_clr_bit;
	ct->chip.irq_set_wake = irq_gc_set_wake;
	ct->chip.irq_suspend = avic_irq_suspend;
	ct->chip.irq_resume = avic_irq_resume;
	ct->regs.mask = !idx ? AVIC_INTENABLEL : AVIC_INTENABLEH;
	ct->regs.ack = ct->regs.mask;

	irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
}

asmlinkage void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
{
	u32 nivector;

	do {
		nivector = __raw_readl(avic_base + AVIC_NIVECSR) >> 16;
		if (nivector == 0xffff)
			break;

		handle_IRQ(irq_find_mapping(domain, nivector), regs);
	} while (1);
}

/*
 * This function initializes the AVIC hardware and disables all the
 * interrupts. It registers the interrupt enable and disable functions
 * to the kernel for each interrupt source.
 */
void __init mxc_init_irq(void __iomem *irqbase)
{
	struct device_node *np;
	int irq_base;
	int i;

	avic_base = irqbase;

	/* put the AVIC into the reset value with
	 * all interrupts disabled
	 */
	__raw_writel(0, avic_base + AVIC_INTCNTL);
	__raw_writel(0x1f, avic_base + AVIC_NIMASK);

	/* disable all interrupts */
	__raw_writel(0, avic_base + AVIC_INTENABLEH);
	__raw_writel(0, avic_base + AVIC_INTENABLEL);

	/* all IRQ no FIQ */
	__raw_writel(0, avic_base + AVIC_INTTYPEH);
	__raw_writel(0, avic_base + AVIC_INTTYPEL);

	irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id());
	WARN_ON(irq_base < 0);

	np = of_find_compatible_node(NULL, NULL, "fsl,avic");
	domain = irq_domain_add_legacy(np, AVIC_NUM_IRQS, irq_base, 0,
				       &irq_domain_simple_ops, NULL);
	WARN_ON(!domain);

	for (i = 0; i < AVIC_NUM_IRQS / 32; i++, irq_base += 32)
		avic_init_gc(i, irq_base);

	/* Set default priority value (0) for all IRQ's */
	for (i = 0; i < 8; i++)
		__raw_writel(0, avic_base + AVIC_NIPRIORITY(i));

#ifdef CONFIG_FIQ
	/* Initialize FIQ */
	init_FIQ(FIQ_START);
#endif

	printk(KERN_INFO "MXC IRQ initialized\n");
}
Commit	Line	Data
52c543f9	1	/*
259bcaae JB	2	* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	3	* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License
	7	* as published by the Free Software Foundation; either version 2
	8	* of the License, or (at your option) any later version.
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	17	* MA 02110-1301, USA.
52c543f9 QJ	18	*/
52c543f9 QJ	19
d7927e19	20	#include <linux/module.h>
259bcaae	21	#include <linux/irq.h>
544496ab	22	#include <linux/irqdomain.h>
fced80c7	23	#include <linux/io.h>
544496ab	24	#include <linux/of.h>
d7927e19	25	#include <asm/mach/irq.h>
98de0cbb	26	#include <asm/exception.h>
52c543f9	27
e3372474	28	#include "common.h"
50f2de61	29	#include "hardware.h"
cdc3f106 PH	30	#include "irq-common.h"
cdc3f106 PH	31
84c9fa43 SH	32	#define AVIC_INTCNTL 0x00 /* int control reg */
	33	#define AVIC_NIMASK 0x04 /* int mask reg */
	34	#define AVIC_INTENNUM 0x08 /* int enable number reg */
	35	#define AVIC_INTDISNUM 0x0C /* int disable number reg */
	36	#define AVIC_INTENABLEH 0x10 /* int enable reg high */
	37	#define AVIC_INTENABLEL 0x14 /* int enable reg low */
	38	#define AVIC_INTTYPEH 0x18 /* int type reg high */
	39	#define AVIC_INTTYPEL 0x1C /* int type reg low */
	40	#define AVIC_NIPRIORITY(x) (0x20 + 4 * (7 - (x))) /* int priority */
	41	#define AVIC_NIVECSR 0x40 /* norm int vector/status */
	42	#define AVIC_FIVECSR 0x44 /* fast int vector/status */
	43	#define AVIC_INTSRCH 0x48 /* int source reg high */
	44	#define AVIC_INTSRCL 0x4C /* int source reg low */
	45	#define AVIC_INTFRCH 0x50 /* int force reg high */
	46	#define AVIC_INTFRCL 0x54 /* int force reg low */
	47	#define AVIC_NIPNDH 0x58 /* norm int pending high */
	48	#define AVIC_NIPNDL 0x5C /* norm int pending low */
	49	#define AVIC_FIPNDH 0x60 /* fast int pending high */
	50	#define AVIC_FIPNDL 0x64 /* fast int pending low */
	51
5a24d69c SH	52	#define AVIC_NUM_IRQS 64
5a24d69c SH	53
ae00ac76	54	static void __iomem *avic_base;
544496ab	55	static struct irq_domain *domain;
259bcaae	56
3f203016	57	#ifdef CONFIG_MXC_IRQ_PRIOR
cdc3f106 PH	58	static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
cdc3f106 PH	59	{
544496ab	60	struct irq_data *d = irq_get_irq_data(irq);
479c901f DA	61	unsigned int temp;
	62	unsigned int mask = 0x0F << irq % 8 * 4;
	63
544496ab SG	64	irq = d->hwirq;
544496ab SG	65
5a24d69c	66	if (irq >= AVIC_NUM_IRQS)
a5a928c5	67	return -EINVAL;
479c901f	68
84c9fa43	69	temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8));
479c901f DA	70	temp &= ~mask;
	71	temp \|= prio & mask;
	72
84c9fa43	73	__raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8));
3f203016 DA	74
3f203016 DA	75	return 0;
479c901f	76	}
cdc3f106	77	#endif
479c901f	78
d7927e19	79	#ifdef CONFIG_FIQ
cdc3f106	80	static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
d7927e19	81	{
544496ab	82	struct irq_data *d = irq_get_irq_data(irq);
d7927e19 PZ	83	unsigned int irqt;
d7927e19 PZ	84
544496ab SG	85	irq = d->hwirq;
544496ab SG	86
5a24d69c	87	if (irq >= AVIC_NUM_IRQS)
d7927e19 PZ	88	return -EINVAL;
d7927e19 PZ	89
5a24d69c	90	if (irq < AVIC_NUM_IRQS / 2) {
84c9fa43 SH	91	irqt = __raw_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq);
84c9fa43 SH	92	__raw_writel(irqt \| (!!type << irq), avic_base + AVIC_INTTYPEL);
d7927e19	93	} else {
5a24d69c	94	irq -= AVIC_NUM_IRQS / 2;
84c9fa43 SH	95	irqt = __raw_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq);
84c9fa43 SH	96	__raw_writel(irqt \| (!!type << irq), avic_base + AVIC_INTTYPEH);
d7927e19 PZ	97	}
	98
	99	return 0;
	100	}
d7927e19 PZ	101	#endif /* CONFIG_FIQ */
d7927e19 PZ	102
52c543f9	103
3439a397	104	static struct mxc_extra_irq avic_extra_irq = {
cdc3f106 PH	105	#ifdef CONFIG_MXC_IRQ_PRIOR
	106	.set_priority = avic_irq_set_priority,
	107	#endif
	108	#ifdef CONFIG_FIQ
	109	.set_irq_fiq = avic_set_irq_fiq,
	110	#endif
52c543f9 QJ	111	};
52c543f9 QJ	112
3439a397	113	#ifdef CONFIG_PM
5fe839d9 FE	114	static u32 avic_saved_mask_reg[2];
5fe839d9 FE	115
3439a397 HW	116	static void avic_irq_suspend(struct irq_data *d)
	117	{
	118	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	119	struct irq_chip_type *ct = gc->chip_types;
544496ab	120	int idx = d->hwirq >> 5;
3439a397 HW	121
	122	avic_saved_mask_reg[idx] = __raw_readl(avic_base + ct->regs.mask);
	123	__raw_writel(gc->wake_active, avic_base + ct->regs.mask);
	124	}
	125
	126	static void avic_irq_resume(struct irq_data *d)
	127	{
	128	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	129	struct irq_chip_type *ct = gc->chip_types;
544496ab	130	int idx = d->hwirq >> 5;
3439a397 HW	131
	132	__raw_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);
	133	}
	134
	135	#else
	136	#define avic_irq_suspend NULL
	137	#define avic_irq_resume NULL
	138	#endif
	139
544496ab	140	static __init void avic_init_gc(int idx, unsigned int irq_start)
3439a397 HW	141	{
	142	struct irq_chip_generic *gc;
	143	struct irq_chip_type *ct;
3439a397 HW	144
	145	gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base,
	146	handle_level_irq);
	147	gc->private = &avic_extra_irq;
	148	gc->wake_enabled = IRQ_MSK(32);
	149
	150	ct = gc->chip_types;
	151	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	152	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	153	ct->chip.irq_ack = irq_gc_mask_clr_bit;
	154	ct->chip.irq_set_wake = irq_gc_set_wake;
	155	ct->chip.irq_suspend = avic_irq_suspend;
	156	ct->chip.irq_resume = avic_irq_resume;
	157	ct->regs.mask = !idx ? AVIC_INTENABLEL : AVIC_INTENABLEH;
	158	ct->regs.ack = ct->regs.mask;
	159
	160	irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
	161	}
	162
b6de943b SH	163	asmlinkage void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
	164	{
	165	u32 nivector;
	166
	167	do {
	168	nivector = __raw_readl(avic_base + AVIC_NIVECSR) >> 16;
	169	if (nivector == 0xffff)
	170	break;
	171
544496ab	172	handle_IRQ(irq_find_mapping(domain, nivector), regs);
b6de943b SH	173	} while (1);
	174	}
	175
2c130fd5	176	/*
52c543f9 QJ	177	* This function initializes the AVIC hardware and disables all the
	178	* interrupts. It registers the interrupt enable and disable functions
	179	* to the kernel for each interrupt source.
	180	*/
c5aa0ad0	181	void __init mxc_init_irq(void __iomem *irqbase)
52c543f9	182	{
544496ab SG	183	struct device_node *np;
544496ab SG	184	int irq_base;
52c543f9	185	int i;
52c543f9	186
c5aa0ad0	187	avic_base = irqbase;
84c9fa43	188
52c543f9 QJ	189	/* put the AVIC into the reset value with
	190	* all interrupts disabled
	191	*/
84c9fa43 SH	192	__raw_writel(0, avic_base + AVIC_INTCNTL);
84c9fa43 SH	193	__raw_writel(0x1f, avic_base + AVIC_NIMASK);
52c543f9 QJ	194
52c543f9 QJ	195	/* disable all interrupts */
84c9fa43 SH	196	__raw_writel(0, avic_base + AVIC_INTENABLEH);
84c9fa43 SH	197	__raw_writel(0, avic_base + AVIC_INTENABLEL);
52c543f9 QJ	198
52c543f9 QJ	199	/* all IRQ no FIQ */
84c9fa43 SH	200	__raw_writel(0, avic_base + AVIC_INTTYPEH);
84c9fa43 SH	201	__raw_writel(0, avic_base + AVIC_INTTYPEL);
3439a397	202
544496ab SG	203	irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id());
	204	WARN_ON(irq_base < 0);
	205
	206	np = of_find_compatible_node(NULL, NULL, "fsl,avic");
	207	domain = irq_domain_add_legacy(np, AVIC_NUM_IRQS, irq_base, 0,
	208	&irq_domain_simple_ops, NULL);
	209	WARN_ON(!domain);
	210
	211	for (i = 0; i < AVIC_NUM_IRQS / 32; i++, irq_base += 32)
	212	avic_init_gc(i, irq_base);
52c543f9	213
479c901f DA	214	/* Set default priority value (0) for all IRQ's */
479c901f DA	215	for (i = 0; i < 8; i++)
84c9fa43	216	__raw_writel(0, avic_base + AVIC_NIPRIORITY(i));
52c543f9	217
d7927e19 PZ	218	#ifdef CONFIG_FIQ
d7927e19 PZ	219	/* Initialize FIQ */
bc89663a	220	init_FIQ(FIQ_START);
d7927e19 PZ	221	#endif
d7927e19 PZ	222
52c543f9 QJ	223	printk(KERN_INFO "MXC IRQ initialized\n");
52c543f9 QJ	224	}