Commit | Line | Data |
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52c543f9 | 1 | /* |
259bcaae JB |
2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. |
3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
17 | * MA 02110-1301, USA. | |
52c543f9 QJ |
18 | */ |
19 | ||
d7927e19 | 20 | #include <linux/module.h> |
259bcaae | 21 | #include <linux/irq.h> |
544496ab | 22 | #include <linux/irqdomain.h> |
fced80c7 | 23 | #include <linux/io.h> |
544496ab | 24 | #include <linux/of.h> |
d7927e19 | 25 | #include <asm/mach/irq.h> |
98de0cbb | 26 | #include <asm/exception.h> |
52c543f9 | 27 | |
e3372474 | 28 | #include "common.h" |
50f2de61 | 29 | #include "hardware.h" |
cdc3f106 PH |
30 | #include "irq-common.h" |
31 | ||
84c9fa43 SH |
32 | #define AVIC_INTCNTL 0x00 /* int control reg */ |
33 | #define AVIC_NIMASK 0x04 /* int mask reg */ | |
34 | #define AVIC_INTENNUM 0x08 /* int enable number reg */ | |
35 | #define AVIC_INTDISNUM 0x0C /* int disable number reg */ | |
36 | #define AVIC_INTENABLEH 0x10 /* int enable reg high */ | |
37 | #define AVIC_INTENABLEL 0x14 /* int enable reg low */ | |
38 | #define AVIC_INTTYPEH 0x18 /* int type reg high */ | |
39 | #define AVIC_INTTYPEL 0x1C /* int type reg low */ | |
40 | #define AVIC_NIPRIORITY(x) (0x20 + 4 * (7 - (x))) /* int priority */ | |
41 | #define AVIC_NIVECSR 0x40 /* norm int vector/status */ | |
42 | #define AVIC_FIVECSR 0x44 /* fast int vector/status */ | |
43 | #define AVIC_INTSRCH 0x48 /* int source reg high */ | |
44 | #define AVIC_INTSRCL 0x4C /* int source reg low */ | |
45 | #define AVIC_INTFRCH 0x50 /* int force reg high */ | |
46 | #define AVIC_INTFRCL 0x54 /* int force reg low */ | |
47 | #define AVIC_NIPNDH 0x58 /* norm int pending high */ | |
48 | #define AVIC_NIPNDL 0x5C /* norm int pending low */ | |
49 | #define AVIC_FIPNDH 0x60 /* fast int pending high */ | |
50 | #define AVIC_FIPNDL 0x64 /* fast int pending low */ | |
51 | ||
5a24d69c SH |
52 | #define AVIC_NUM_IRQS 64 |
53 | ||
ae00ac76 | 54 | static void __iomem *avic_base; |
544496ab | 55 | static struct irq_domain *domain; |
259bcaae | 56 | |
d7927e19 | 57 | #ifdef CONFIG_FIQ |
d1e1c31c | 58 | static int avic_set_irq_fiq(unsigned int hwirq, unsigned int type) |
d7927e19 PZ |
59 | { |
60 | unsigned int irqt; | |
61 | ||
d1e1c31c | 62 | if (hwirq >= AVIC_NUM_IRQS) |
d7927e19 PZ |
63 | return -EINVAL; |
64 | ||
d1e1c31c AS |
65 | if (hwirq < AVIC_NUM_IRQS / 2) { |
66 | irqt = imx_readl(avic_base + AVIC_INTTYPEL) & ~(1 << hwirq); | |
67 | imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEL); | |
d7927e19 | 68 | } else { |
d1e1c31c AS |
69 | hwirq -= AVIC_NUM_IRQS / 2; |
70 | irqt = imx_readl(avic_base + AVIC_INTTYPEH) & ~(1 << hwirq); | |
71 | imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEH); | |
d7927e19 PZ |
72 | } |
73 | ||
74 | return 0; | |
75 | } | |
d7927e19 PZ |
76 | #endif /* CONFIG_FIQ */ |
77 | ||
52c543f9 | 78 | |
3439a397 | 79 | static struct mxc_extra_irq avic_extra_irq = { |
cdc3f106 PH |
80 | #ifdef CONFIG_FIQ |
81 | .set_irq_fiq = avic_set_irq_fiq, | |
82 | #endif | |
52c543f9 QJ |
83 | }; |
84 | ||
3439a397 | 85 | #ifdef CONFIG_PM |
5fe839d9 FE |
86 | static u32 avic_saved_mask_reg[2]; |
87 | ||
3439a397 HW |
88 | static void avic_irq_suspend(struct irq_data *d) |
89 | { | |
90 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
91 | struct irq_chip_type *ct = gc->chip_types; | |
544496ab | 92 | int idx = d->hwirq >> 5; |
3439a397 | 93 | |
c553138f JB |
94 | avic_saved_mask_reg[idx] = imx_readl(avic_base + ct->regs.mask); |
95 | imx_writel(gc->wake_active, avic_base + ct->regs.mask); | |
3439a397 HW |
96 | } |
97 | ||
98 | static void avic_irq_resume(struct irq_data *d) | |
99 | { | |
100 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
101 | struct irq_chip_type *ct = gc->chip_types; | |
544496ab | 102 | int idx = d->hwirq >> 5; |
3439a397 | 103 | |
c553138f | 104 | imx_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask); |
3439a397 HW |
105 | } |
106 | ||
107 | #else | |
108 | #define avic_irq_suspend NULL | |
109 | #define avic_irq_resume NULL | |
110 | #endif | |
111 | ||
544496ab | 112 | static __init void avic_init_gc(int idx, unsigned int irq_start) |
3439a397 HW |
113 | { |
114 | struct irq_chip_generic *gc; | |
115 | struct irq_chip_type *ct; | |
3439a397 HW |
116 | |
117 | gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base, | |
118 | handle_level_irq); | |
119 | gc->private = &avic_extra_irq; | |
120 | gc->wake_enabled = IRQ_MSK(32); | |
121 | ||
122 | ct = gc->chip_types; | |
123 | ct->chip.irq_mask = irq_gc_mask_clr_bit; | |
124 | ct->chip.irq_unmask = irq_gc_mask_set_bit; | |
125 | ct->chip.irq_ack = irq_gc_mask_clr_bit; | |
126 | ct->chip.irq_set_wake = irq_gc_set_wake; | |
127 | ct->chip.irq_suspend = avic_irq_suspend; | |
128 | ct->chip.irq_resume = avic_irq_resume; | |
129 | ct->regs.mask = !idx ? AVIC_INTENABLEL : AVIC_INTENABLEH; | |
130 | ct->regs.ack = ct->regs.mask; | |
131 | ||
132 | irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0); | |
133 | } | |
134 | ||
000bf9ee | 135 | static void __exception_irq_entry avic_handle_irq(struct pt_regs *regs) |
b6de943b SH |
136 | { |
137 | u32 nivector; | |
138 | ||
139 | do { | |
c553138f | 140 | nivector = imx_readl(avic_base + AVIC_NIVECSR) >> 16; |
b6de943b SH |
141 | if (nivector == 0xffff) |
142 | break; | |
143 | ||
9705ca3d | 144 | handle_domain_irq(domain, nivector, regs); |
b6de943b SH |
145 | } while (1); |
146 | } | |
147 | ||
2c130fd5 | 148 | /* |
52c543f9 QJ |
149 | * This function initializes the AVIC hardware and disables all the |
150 | * interrupts. It registers the interrupt enable and disable functions | |
151 | * to the kernel for each interrupt source. | |
152 | */ | |
c5aa0ad0 | 153 | void __init mxc_init_irq(void __iomem *irqbase) |
52c543f9 | 154 | { |
544496ab SG |
155 | struct device_node *np; |
156 | int irq_base; | |
52c543f9 | 157 | int i; |
52c543f9 | 158 | |
c5aa0ad0 | 159 | avic_base = irqbase; |
84c9fa43 | 160 | |
52c543f9 QJ |
161 | /* put the AVIC into the reset value with |
162 | * all interrupts disabled | |
163 | */ | |
c553138f JB |
164 | imx_writel(0, avic_base + AVIC_INTCNTL); |
165 | imx_writel(0x1f, avic_base + AVIC_NIMASK); | |
52c543f9 QJ |
166 | |
167 | /* disable all interrupts */ | |
c553138f JB |
168 | imx_writel(0, avic_base + AVIC_INTENABLEH); |
169 | imx_writel(0, avic_base + AVIC_INTENABLEL); | |
52c543f9 QJ |
170 | |
171 | /* all IRQ no FIQ */ | |
c553138f JB |
172 | imx_writel(0, avic_base + AVIC_INTTYPEH); |
173 | imx_writel(0, avic_base + AVIC_INTTYPEL); | |
3439a397 | 174 | |
544496ab SG |
175 | irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id()); |
176 | WARN_ON(irq_base < 0); | |
177 | ||
178 | np = of_find_compatible_node(NULL, NULL, "fsl,avic"); | |
179 | domain = irq_domain_add_legacy(np, AVIC_NUM_IRQS, irq_base, 0, | |
180 | &irq_domain_simple_ops, NULL); | |
181 | WARN_ON(!domain); | |
182 | ||
183 | for (i = 0; i < AVIC_NUM_IRQS / 32; i++, irq_base += 32) | |
184 | avic_init_gc(i, irq_base); | |
52c543f9 | 185 | |
479c901f DA |
186 | /* Set default priority value (0) for all IRQ's */ |
187 | for (i = 0; i < 8; i++) | |
c553138f | 188 | imx_writel(0, avic_base + AVIC_NIPRIORITY(i)); |
52c543f9 | 189 | |
000bf9ee AS |
190 | set_handle_irq(avic_handle_irq); |
191 | ||
d7927e19 PZ |
192 | #ifdef CONFIG_FIQ |
193 | /* Initialize FIQ */ | |
bc89663a | 194 | init_FIQ(FIQ_START); |
d7927e19 PZ |
195 | #endif |
196 | ||
52c543f9 QJ |
197 | printk(KERN_INFO "MXC IRQ initialized\n"); |
198 | } |