Commit | Line | Data |
---|---|---|
b75c0151 SH |
1 | /* |
2 | * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com> | |
3 | * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * Gated clock implementation | |
10 | */ | |
11 | ||
12 | #include <linux/clk-provider.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/slab.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/string.h> | |
d7b8c030 | 18 | #include "clk.h" |
b75c0151 SH |
19 | |
20 | /** | |
21 | * DOC: basic gatable clock which can gate and ungate it's ouput | |
22 | * | |
23 | * Traits of this clock: | |
24 | * prepare - clk_(un)prepare only ensures parent is (un)prepared | |
25 | * enable - clk_enable and clk_disable are functional & control gating | |
26 | * rate - inherits rate from parent. No clk_set_rate support | |
27 | * parent - fixed parent. No clk_set_parent support | |
28 | */ | |
29 | ||
54ee1471 SG |
30 | struct clk_gate2 { |
31 | struct clk_hw hw; | |
32 | void __iomem *reg; | |
33 | u8 bit_idx; | |
34 | u8 flags; | |
35 | spinlock_t *lock; | |
f9f28cdf | 36 | unsigned int *share_count; |
54ee1471 SG |
37 | }; |
38 | ||
39 | #define to_clk_gate2(_hw) container_of(_hw, struct clk_gate2, hw) | |
b75c0151 SH |
40 | |
41 | static int clk_gate2_enable(struct clk_hw *hw) | |
42 | { | |
54ee1471 | 43 | struct clk_gate2 *gate = to_clk_gate2(hw); |
b75c0151 SH |
44 | u32 reg; |
45 | unsigned long flags = 0; | |
46 | ||
94b5c028 | 47 | spin_lock_irqsave(gate->lock, flags); |
b75c0151 | 48 | |
f9f28cdf SG |
49 | if (gate->share_count && (*gate->share_count)++ > 0) |
50 | goto out; | |
51 | ||
b75c0151 SH |
52 | reg = readl(gate->reg); |
53 | reg |= 3 << gate->bit_idx; | |
54 | writel(reg, gate->reg); | |
55 | ||
f9f28cdf | 56 | out: |
94b5c028 | 57 | spin_unlock_irqrestore(gate->lock, flags); |
b75c0151 SH |
58 | |
59 | return 0; | |
60 | } | |
61 | ||
62 | static void clk_gate2_disable(struct clk_hw *hw) | |
63 | { | |
54ee1471 | 64 | struct clk_gate2 *gate = to_clk_gate2(hw); |
b75c0151 SH |
65 | u32 reg; |
66 | unsigned long flags = 0; | |
67 | ||
94b5c028 | 68 | spin_lock_irqsave(gate->lock, flags); |
b75c0151 | 69 | |
63288b72 SG |
70 | if (gate->share_count) { |
71 | if (WARN_ON(*gate->share_count == 0)) | |
72 | goto out; | |
73 | else if (--(*gate->share_count) > 0) | |
74 | goto out; | |
75 | } | |
f9f28cdf | 76 | |
b75c0151 SH |
77 | reg = readl(gate->reg); |
78 | reg &= ~(3 << gate->bit_idx); | |
79 | writel(reg, gate->reg); | |
80 | ||
f9f28cdf | 81 | out: |
94b5c028 | 82 | spin_unlock_irqrestore(gate->lock, flags); |
b75c0151 SH |
83 | } |
84 | ||
63288b72 | 85 | static int clk_gate2_reg_is_enabled(void __iomem *reg, u8 bit_idx) |
b75c0151 | 86 | { |
63288b72 | 87 | u32 val = readl(reg); |
b75c0151 | 88 | |
63288b72 | 89 | if (((val >> bit_idx) & 1) == 1) |
b75c0151 SH |
90 | return 1; |
91 | ||
92 | return 0; | |
93 | } | |
94 | ||
63288b72 SG |
95 | static int clk_gate2_is_enabled(struct clk_hw *hw) |
96 | { | |
97 | struct clk_gate2 *gate = to_clk_gate2(hw); | |
98 | ||
99 | if (gate->share_count) | |
100 | return !!(*gate->share_count); | |
101 | else | |
102 | return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx); | |
103 | } | |
104 | ||
b75c0151 SH |
105 | static struct clk_ops clk_gate2_ops = { |
106 | .enable = clk_gate2_enable, | |
107 | .disable = clk_gate2_disable, | |
108 | .is_enabled = clk_gate2_is_enabled, | |
109 | }; | |
110 | ||
111 | struct clk *clk_register_gate2(struct device *dev, const char *name, | |
112 | const char *parent_name, unsigned long flags, | |
113 | void __iomem *reg, u8 bit_idx, | |
f9f28cdf SG |
114 | u8 clk_gate2_flags, spinlock_t *lock, |
115 | unsigned int *share_count) | |
b75c0151 | 116 | { |
54ee1471 | 117 | struct clk_gate2 *gate; |
b75c0151 SH |
118 | struct clk *clk; |
119 | struct clk_init_data init; | |
120 | ||
54ee1471 | 121 | gate = kzalloc(sizeof(struct clk_gate2), GFP_KERNEL); |
b75c0151 SH |
122 | if (!gate) |
123 | return ERR_PTR(-ENOMEM); | |
124 | ||
54ee1471 | 125 | /* struct clk_gate2 assignments */ |
b75c0151 SH |
126 | gate->reg = reg; |
127 | gate->bit_idx = bit_idx; | |
128 | gate->flags = clk_gate2_flags; | |
129 | gate->lock = lock; | |
63288b72 SG |
130 | |
131 | /* Initialize share_count per hardware state */ | |
132 | if (share_count) | |
133 | *share_count = clk_gate2_reg_is_enabled(reg, bit_idx) ? 1 : 0; | |
f9f28cdf | 134 | gate->share_count = share_count; |
b75c0151 SH |
135 | |
136 | init.name = name; | |
137 | init.ops = &clk_gate2_ops; | |
138 | init.flags = flags; | |
139 | init.parent_names = parent_name ? &parent_name : NULL; | |
140 | init.num_parents = parent_name ? 1 : 0; | |
141 | ||
142 | gate->hw.init = &init; | |
143 | ||
144 | clk = clk_register(dev, &gate->hw); | |
145 | if (IS_ERR(clk)) | |
ecf026dc | 146 | kfree(gate); |
b75c0151 SH |
147 | |
148 | return clk; | |
149 | } |