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cd73785f SH |
1 | /* |
2 | * Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License along | |
14 | * with this program; if not, write to the Free Software Foundation, Inc., | |
15 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. | |
16 | */ | |
17 | ||
18 | #include <linux/kernel.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/clk.h> | |
21 | #include <linux/io.h> | |
22 | #include <linux/clkdev.h> | |
23 | #include <linux/err.h> | |
24 | ||
cd73785f | 25 | #include "clk.h" |
e3372474 | 26 | #include "common.h" |
50f2de61 | 27 | #include "hardware.h" |
cd73785f SH |
28 | |
29 | /* CCM register addresses */ | |
30 | #define IO_ADDR_CCM(off) (MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR + (off))) | |
31 | ||
32 | #define CCM_CSCR IO_ADDR_CCM(0x0) | |
33 | #define CCM_MPCTL0 IO_ADDR_CCM(0x4) | |
34 | #define CCM_SPCTL0 IO_ADDR_CCM(0xc) | |
35 | #define CCM_PCDR IO_ADDR_CCM(0x20) | |
36 | ||
37 | /* SCM register addresses */ | |
38 | #define IO_ADDR_SCM(off) (MX1_IO_ADDRESS(MX1_SCM_BASE_ADDR + (off))) | |
39 | ||
40 | #define SCM_GCCR IO_ADDR_SCM(0xc) | |
41 | ||
42 | static const char *prem_sel_clks[] = { "clk32_premult", "clk16m", }; | |
402e4a4c AS |
43 | static const char *clko_sel_clks[] = { "per1", "hclk", "clk48m", "clk16m", |
44 | "prem", "fclk", }; | |
45 | ||
cd73785f | 46 | enum imx1_clks { |
402e4a4c AS |
47 | dummy, clk32, clk16m_ext, clk16m, clk32_premult, prem, mpll, mpll_gate, |
48 | spll, spll_gate, mcu, fclk, hclk, clk48m, per1, per2, per3, clko, | |
49 | uart3_gate, ssi2_gate, brom_gate, dma_gate, csi_gate, mma_gate, | |
50 | usbd_gate, clk_max | |
cd73785f SH |
51 | }; |
52 | ||
53 | static struct clk *clk[clk_max]; | |
54 | ||
55 | int __init mx1_clocks_init(unsigned long fref) | |
56 | { | |
57 | int i; | |
58 | ||
59 | clk[dummy] = imx_clk_fixed("dummy", 0); | |
60 | clk[clk32] = imx_clk_fixed("clk32", fref); | |
61 | clk[clk16m_ext] = imx_clk_fixed("clk16m_ext", 16000000); | |
62 | clk[clk16m] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17); | |
63 | clk[clk32_premult] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1); | |
64 | clk[prem] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks, | |
65 | ARRAY_SIZE(prem_sel_clks)); | |
66 | clk[mpll] = imx_clk_pllv1("mpll", "clk32_premult", CCM_MPCTL0); | |
402e4a4c | 67 | clk[mpll_gate] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0); |
cd73785f | 68 | clk[spll] = imx_clk_pllv1("spll", "prem", CCM_SPCTL0); |
402e4a4c | 69 | clk[spll_gate] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); |
cd73785f | 70 | clk[mcu] = imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1); |
402e4a4c AS |
71 | clk[fclk] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 15, 1); |
72 | clk[hclk] = imx_clk_divider("hclk", "spll_gate", CCM_CSCR, 10, 4); | |
73 | clk[clk48m] = imx_clk_divider("clk48m", "spll_gate", CCM_CSCR, 26, 3); | |
74 | clk[per1] = imx_clk_divider("per1", "spll_gate", CCM_PCDR, 0, 4); | |
75 | clk[per2] = imx_clk_divider("per2", "spll_gate", CCM_PCDR, 4, 4); | |
76 | clk[per3] = imx_clk_divider("per3", "spll_gate", CCM_PCDR, 16, 7); | |
cd73785f SH |
77 | clk[clko] = imx_clk_mux("clko", CCM_CSCR, 29, 3, clko_sel_clks, |
78 | ARRAY_SIZE(clko_sel_clks)); | |
402e4a4c AS |
79 | clk[uart3_gate] = imx_clk_gate("uart3_gate", "hclk", SCM_GCCR, 6); |
80 | clk[ssi2_gate] = imx_clk_gate("ssi2_gate", "hclk", SCM_GCCR, 5); | |
81 | clk[brom_gate] = imx_clk_gate("brom_gate", "hclk", SCM_GCCR, 4); | |
82 | clk[dma_gate] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 3); | |
cd73785f SH |
83 | clk[csi_gate] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2); |
84 | clk[mma_gate] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1); | |
85 | clk[usbd_gate] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0); | |
86 | ||
87 | for (i = 0; i < ARRAY_SIZE(clk); i++) | |
88 | if (IS_ERR(clk[i])) | |
89 | pr_err("imx1 clk %d: register failed with %ld\n", | |
90 | i, PTR_ERR(clk[i])); | |
91 | ||
e51d0f0a SG |
92 | clk_register_clkdev(clk[dma_gate], "ahb", "imx1-dma"); |
93 | clk_register_clkdev(clk[hclk], "ipg", "imx1-dma"); | |
cd73785f SH |
94 | clk_register_clkdev(clk[per1], "per", "imx-gpt.0"); |
95 | clk_register_clkdev(clk[hclk], "ipg", "imx-gpt.0"); | |
96 | clk_register_clkdev(clk[per1], "per", "imx1-uart.0"); | |
97 | clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.0"); | |
98 | clk_register_clkdev(clk[per1], "per", "imx1-uart.1"); | |
99 | clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.1"); | |
100 | clk_register_clkdev(clk[per1], "per", "imx1-uart.2"); | |
402e4a4c | 101 | clk_register_clkdev(clk[uart3_gate], "ipg", "imx1-uart.2"); |
5bdfba29 | 102 | clk_register_clkdev(clk[hclk], NULL, "imx1-i2c.0"); |
cd73785f SH |
103 | clk_register_clkdev(clk[per2], "per", "imx1-cspi.0"); |
104 | clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.0"); | |
105 | clk_register_clkdev(clk[per2], "per", "imx1-cspi.1"); | |
106 | clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.1"); | |
e69dc9a9 SG |
107 | clk_register_clkdev(clk[per2], "per", "imx1-fb.0"); |
108 | clk_register_clkdev(clk[dummy], "ipg", "imx1-fb.0"); | |
109 | clk_register_clkdev(clk[dummy], "ahb", "imx1-fb.0"); | |
cd73785f | 110 | |
2cfb4518 | 111 | mxc_timer_init(MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR), MX1_TIM1_INT); |
cd73785f SH |
112 | |
113 | return 0; | |
114 | } |