[deliverable/linux.git] / arch / arm / mach-imx / clk-imx21.c

/*
 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
 * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clkdev.h>

#include "clk.h"
#include "common.h"
#include "hardware.h"

#define IO_ADDR_CCM(off)	(MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off)))

/* Register offsets */
#define CCM_CSCR		IO_ADDR_CCM(0x0)
#define CCM_MPCTL0		IO_ADDR_CCM(0x4)
#define CCM_SPCTL0		IO_ADDR_CCM(0xc)
#define CCM_PCDR0		IO_ADDR_CCM(0x18)
#define CCM_PCDR1		IO_ADDR_CCM(0x1c)
#define CCM_PCCR0		IO_ADDR_CCM(0x20)
#define CCM_PCCR1		IO_ADDR_CCM(0x24)

static const char *mpll_osc_sel_clks[] = { "ckih_gate", "ckih_div1p5", };
static const char *mpll_sel_clks[] = { "fpm_gate", "mpll_osc_sel", };
static const char *spll_sel_clks[] = { "fpm_gate", "mpll_osc_sel", };
static const char *ssi_sel_clks[] = { "spll_gate", "mpll_gate", };

enum imx21_clks {
	dummy, ckil, ckih, fpm, ckih_div1p5, mpll_gate, spll_gate, fpm_gate,
	ckih_gate, mpll_osc_sel, ipg, hclk, mpll_sel, spll_sel, ssi1_sel,
	ssi2_sel, usb_div, fclk, mpll, spll, nfc_div, ssi1_div, ssi2_div, per1,
	per2, per3, per4, uart1_ipg_gate, uart2_ipg_gate, uart3_ipg_gate,
	uart4_ipg_gate, cspi1_ipg_gate, cspi2_ipg_gate, ssi1_gate, ssi2_gate,
	sdhc1_ipg_gate, sdhc2_ipg_gate, gpio_gate, i2c_gate, dma_gate, usb_gate,
	emma_gate, ssi2_baud_gate, ssi1_baud_gate, lcdc_ipg_gate, nfc_gate,
	lcdc_hclk_gate, per4_gate, bmi_gate, usb_hclk_gate, slcdc_gate,
	slcdc_hclk_gate, emma_hclk_gate, brom_gate, dma_hclk_gate,
	csi_hclk_gate, cspi3_ipg_gate, wdog_gate, gpt1_ipg_gate, gpt2_ipg_gate,
	gpt3_ipg_gate, pwm_ipg_gate, rtc_gate, kpp_gate, owire_gate, clk_max
};

static struct clk *clk[clk_max];

int __init mx21_clocks_init(unsigned long lref, unsigned long href)
{
	clk[dummy] = imx_clk_fixed("dummy", 0);
	clk[ckil] = imx_clk_fixed("ckil", lref);
	clk[ckih] = imx_clk_fixed("ckih", href);
	clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 512, 1);
	clk[ckih_div1p5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3);

	clk[mpll_gate] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0);
	clk[spll_gate] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
	clk[fpm_gate] = imx_clk_gate("fpm_gate", "fpm", CCM_CSCR, 2);
	clk[ckih_gate] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3);
	clk[mpll_osc_sel] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY_SIZE(mpll_osc_sel_clks));
	clk[ipg] = imx_clk_divider("ipg", "hclk", CCM_CSCR, 9, 1);
	clk[hclk] = imx_clk_divider("hclk", "fclk", CCM_CSCR, 10, 4);
	clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_sel_clks));
	clk[spll_sel] = imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks, ARRAY_SIZE(spll_sel_clks));
	clk[ssi1_sel] = imx_clk_mux("ssi1_sel", CCM_CSCR, 19, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
	clk[ssi2_sel] = imx_clk_mux("ssi2_sel", CCM_CSCR, 20, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
	clk[usb_div] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 26, 3);
	clk[fclk] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 29, 3);

	clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);

	clk[spll] = imx_clk_pllv1("spll", "spll_sel", CCM_SPCTL0);

	clk[nfc_div] = imx_clk_divider("nfc_div", "fclk", CCM_PCDR0, 12, 4);
	clk[ssi1_div] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);
	clk[ssi2_div] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6);

	clk[per1] = imx_clk_divider("per1", "mpll_gate", CCM_PCDR1, 0, 6);
	clk[per2] = imx_clk_divider("per2", "mpll_gate", CCM_PCDR1, 8, 6);
	clk[per3] = imx_clk_divider("per3", "mpll_gate", CCM_PCDR1, 16, 6);
	clk[per4] = imx_clk_divider("per4", "mpll_gate", CCM_PCDR1, 24, 6);

	clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR0, 0);
	clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR0, 1);
	clk[uart3_ipg_gate] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR0, 2);
	clk[uart4_ipg_gate] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR0, 3);
	clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 4);
	clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 5);
	clk[ssi1_gate] = imx_clk_gate("ssi1_gate", "ipg", CCM_PCCR0, 6);
	clk[ssi2_gate] = imx_clk_gate("ssi2_gate", "ipg", CCM_PCCR0, 7);
	clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 9);
	clk[sdhc2_ipg_gate] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 10);
	clk[gpio_gate] = imx_clk_gate("gpio_gate", "ipg", CCM_PCCR0, 11);
	clk[i2c_gate] = imx_clk_gate("i2c_gate", "ipg", CCM_PCCR0, 12);
	clk[dma_gate] = imx_clk_gate("dma_gate", "ipg", CCM_PCCR0, 13);
	clk[usb_gate] = imx_clk_gate("usb_gate", "usb_div", CCM_PCCR0, 14);
	clk[emma_gate] = imx_clk_gate("emma_gate", "ipg", CCM_PCCR0, 15);
	clk[ssi2_baud_gate] = imx_clk_gate("ssi2_baud_gate", "ipg", CCM_PCCR0, 16);
	clk[ssi1_baud_gate] = imx_clk_gate("ssi1_baud_gate", "ipg", CCM_PCCR0, 17);
	clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 18);
	clk[nfc_gate] = imx_clk_gate("nfc_gate", "nfc_div", CCM_PCCR0, 19);
	clk[slcdc_hclk_gate] = imx_clk_gate("slcdc_hclk_gate", "hclk", CCM_PCCR0, 21);
	clk[per4_gate] = imx_clk_gate("per4_gate", "per4", CCM_PCCR0, 22);
	clk[bmi_gate] = imx_clk_gate("bmi_gate", "hclk", CCM_PCCR0, 23);
	clk[usb_hclk_gate] = imx_clk_gate("usb_hclk_gate", "hclk", CCM_PCCR0, 24);
	clk[slcdc_gate] = imx_clk_gate("slcdc_gate", "hclk", CCM_PCCR0, 25);
	clk[lcdc_hclk_gate] = imx_clk_gate("lcdc_hclk_gate", "hclk", CCM_PCCR0, 26);
	clk[emma_hclk_gate] = imx_clk_gate("emma_hclk_gate", "hclk", CCM_PCCR0, 27);
	clk[brom_gate] = imx_clk_gate("brom_gate", "hclk", CCM_PCCR0, 28);
	clk[dma_hclk_gate] = imx_clk_gate("dma_hclk_gate", "hclk", CCM_PCCR0, 30);
	clk[csi_hclk_gate] = imx_clk_gate("csi_hclk_gate", "hclk", CCM_PCCR0, 31);

	clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR1, 23);
	clk[wdog_gate] = imx_clk_gate("wdog_gate", "ipg", CCM_PCCR1, 24);
	clk[gpt1_ipg_gate] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR1, 25);
	clk[gpt2_ipg_gate] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR1, 26);
	clk[gpt3_ipg_gate] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR1, 27);
	clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR1, 28);
	clk[rtc_gate] = imx_clk_gate("rtc_gate", "ipg", CCM_PCCR1, 29);
	clk[kpp_gate] = imx_clk_gate("kpp_gate", "ipg", CCM_PCCR1, 30);
	clk[owire_gate] = imx_clk_gate("owire_gate", "ipg", CCM_PCCR1, 31);

	imx_check_clocks(clk, ARRAY_SIZE(clk));

	clk_register_clkdev(clk[per1], "per", "imx21-uart.0");
	clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
	clk_register_clkdev(clk[per1], "per", "imx21-uart.1");
	clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
	clk_register_clkdev(clk[per1], "per", "imx21-uart.2");
	clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
	clk_register_clkdev(clk[per1], "per", "imx21-uart.3");
	clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
	clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0");
	clk_register_clkdev(clk[per1], "per", "imx-gpt.0");
	clk_register_clkdev(clk[per2], "per", "imx21-cspi.0");
	clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx21-cspi.0");
	clk_register_clkdev(clk[per2], "per", "imx21-cspi.1");
	clk_register_clkdev(clk[cspi2_ipg_gate], "ipg", "imx21-cspi.1");
	clk_register_clkdev(clk[per2], "per", "imx21-cspi.2");
	clk_register_clkdev(clk[cspi3_ipg_gate], "ipg", "imx21-cspi.2");
	clk_register_clkdev(clk[per3], "per", "imx21-fb.0");
	clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx21-fb.0");
	clk_register_clkdev(clk[lcdc_hclk_gate], "ahb", "imx21-fb.0");
	clk_register_clkdev(clk[usb_gate], "per", "imx21-hcd.0");
	clk_register_clkdev(clk[usb_hclk_gate], "ahb", "imx21-hcd.0");
	clk_register_clkdev(clk[nfc_gate], NULL, "imx21-nand.0");
	clk_register_clkdev(clk[dma_hclk_gate], "ahb", "imx21-dma");
	clk_register_clkdev(clk[dma_gate], "ipg", "imx21-dma");
	clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
	clk_register_clkdev(clk[i2c_gate], NULL, "imx21-i2c.0");
	clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0");

	mxc_timer_init(MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR), MX21_INT_GPT1);

	return 0;
}
Commit	Line	Data
93421e42 SH	1	/*
	2	* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	3	* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
	4	* Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
93421e42 SH	10	*/
	11
	12	#include <linux/clk.h>
93421e42	13	#include <linux/clk-provider.h>
548694b9	14	#include <linux/clkdev.h>
93421e42	15
93421e42	16	#include "clk.h"
e3372474	17	#include "common.h"
50f2de61	18	#include "hardware.h"
93421e42 SH	19
	20	#define IO_ADDR_CCM(off) (MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off)))
	21
	22	/* Register offsets */
	23	#define CCM_CSCR IO_ADDR_CCM(0x0)
	24	#define CCM_MPCTL0 IO_ADDR_CCM(0x4)
93421e42	25	#define CCM_SPCTL0 IO_ADDR_CCM(0xc)
93421e42 SH	26	#define CCM_PCDR0 IO_ADDR_CCM(0x18)
	27	#define CCM_PCDR1 IO_ADDR_CCM(0x1c)
	28	#define CCM_PCCR0 IO_ADDR_CCM(0x20)
	29	#define CCM_PCCR1 IO_ADDR_CCM(0x24)
93421e42	30
65251690 AS	31	static const char *mpll_osc_sel_clks[] = { "ckih_gate", "ckih_div1p5", };
	32	static const char *mpll_sel_clks[] = { "fpm_gate", "mpll_osc_sel", };
	33	static const char *spll_sel_clks[] = { "fpm_gate", "mpll_osc_sel", };
	34	static const char *ssi_sel_clks[] = { "spll_gate", "mpll_gate", };
93421e42 SH	35
93421e42 SH	36	enum imx21_clks {
65251690 AS	37	dummy, ckil, ckih, fpm, ckih_div1p5, mpll_gate, spll_gate, fpm_gate,
	38	ckih_gate, mpll_osc_sel, ipg, hclk, mpll_sel, spll_sel, ssi1_sel,
	39	ssi2_sel, usb_div, fclk, mpll, spll, nfc_div, ssi1_div, ssi2_div, per1,
93421e42	40	per2, per3, per4, uart1_ipg_gate, uart2_ipg_gate, uart3_ipg_gate,
65251690 AS	41	uart4_ipg_gate, cspi1_ipg_gate, cspi2_ipg_gate, ssi1_gate, ssi2_gate,
	42	sdhc1_ipg_gate, sdhc2_ipg_gate, gpio_gate, i2c_gate, dma_gate, usb_gate,
	43	emma_gate, ssi2_baud_gate, ssi1_baud_gate, lcdc_ipg_gate, nfc_gate,
	44	lcdc_hclk_gate, per4_gate, bmi_gate, usb_hclk_gate, slcdc_gate,
	45	slcdc_hclk_gate, emma_hclk_gate, brom_gate, dma_hclk_gate,
	46	csi_hclk_gate, cspi3_ipg_gate, wdog_gate, gpt1_ipg_gate, gpt2_ipg_gate,
	47	gpt3_ipg_gate, pwm_ipg_gate, rtc_gate, kpp_gate, owire_gate, clk_max
93421e42 SH	48	};
	49
	50	static struct clk *clk[clk_max];
	51
93421e42 SH	52	int __init mx21_clocks_init(unsigned long lref, unsigned long href)
93421e42 SH	53	{
65251690	54	clk[dummy] = imx_clk_fixed("dummy", 0);
93421e42 SH	55	clk[ckil] = imx_clk_fixed("ckil", lref);
	56	clk[ckih] = imx_clk_fixed("ckih", href);
	57	clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 512, 1);
65251690 AS	58	clk[ckih_div1p5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3);
	59
	60	clk[mpll_gate] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0);
	61	clk[spll_gate] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
	62	clk[fpm_gate] = imx_clk_gate("fpm_gate", "fpm", CCM_CSCR, 2);
	63	clk[ckih_gate] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3);
	64	clk[mpll_osc_sel] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY_SIZE(mpll_osc_sel_clks));
	65	clk[ipg] = imx_clk_divider("ipg", "hclk", CCM_CSCR, 9, 1);
	66	clk[hclk] = imx_clk_divider("hclk", "fclk", CCM_CSCR, 10, 4);
	67	clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_sel_clks));
	68	clk[spll_sel] = imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks, ARRAY_SIZE(spll_sel_clks));
	69	clk[ssi1_sel] = imx_clk_mux("ssi1_sel", CCM_CSCR, 19, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
	70	clk[ssi2_sel] = imx_clk_mux("ssi2_sel", CCM_CSCR, 20, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
	71	clk[usb_div] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 26, 3);
	72	clk[fclk] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 29, 3);
	73
93421e42	74	clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
65251690	75
93421e42	76	clk[spll] = imx_clk_pllv1("spll", "spll_sel", CCM_SPCTL0);
65251690 AS	77
	78	clk[nfc_div] = imx_clk_divider("nfc_div", "fclk", CCM_PCDR0, 12, 4);
	79	clk[ssi1_div] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);
	80	clk[ssi2_div] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6);
	81
	82	clk[per1] = imx_clk_divider("per1", "mpll_gate", CCM_PCDR1, 0, 6);
	83	clk[per2] = imx_clk_divider("per2", "mpll_gate", CCM_PCDR1, 8, 6);
	84	clk[per3] = imx_clk_divider("per3", "mpll_gate", CCM_PCDR1, 16, 6);
	85	clk[per4] = imx_clk_divider("per4", "mpll_gate", CCM_PCDR1, 24, 6);
	86
93421e42 SH	87	clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR0, 0);
	88	clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR0, 1);
	89	clk[uart3_ipg_gate] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR0, 2);
	90	clk[uart4_ipg_gate] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR0, 3);
93421e42	91	clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 4);
65251690	92	clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 5);
93421e42 SH	93	clk[ssi1_gate] = imx_clk_gate("ssi1_gate", "ipg", CCM_PCCR0, 6);
93421e42 SH	94	clk[ssi2_gate] = imx_clk_gate("ssi2_gate", "ipg", CCM_PCCR0, 7);
65251690 AS	95	clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 9);
	96	clk[sdhc2_ipg_gate] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 10);
	97	clk[gpio_gate] = imx_clk_gate("gpio_gate", "ipg", CCM_PCCR0, 11);
	98	clk[i2c_gate] = imx_clk_gate("i2c_gate", "ipg", CCM_PCCR0, 12);
93421e42	99	clk[dma_gate] = imx_clk_gate("dma_gate", "ipg", CCM_PCCR0, 13);
65251690	100	clk[usb_gate] = imx_clk_gate("usb_gate", "usb_div", CCM_PCCR0, 14);
93421e42	101	clk[emma_gate] = imx_clk_gate("emma_gate", "ipg", CCM_PCCR0, 15);
65251690 AS	102	clk[ssi2_baud_gate] = imx_clk_gate("ssi2_baud_gate", "ipg", CCM_PCCR0, 16);
	103	clk[ssi1_baud_gate] = imx_clk_gate("ssi1_baud_gate", "ipg", CCM_PCCR0, 17);
	104	clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 18);
	105	clk[nfc_gate] = imx_clk_gate("nfc_gate", "nfc_div", CCM_PCCR0, 19);
93421e42	106	clk[slcdc_hclk_gate] = imx_clk_gate("slcdc_hclk_gate", "hclk", CCM_PCCR0, 21);
65251690 AS	107	clk[per4_gate] = imx_clk_gate("per4_gate", "per4", CCM_PCCR0, 22);
	108	clk[bmi_gate] = imx_clk_gate("bmi_gate", "hclk", CCM_PCCR0, 23);
	109	clk[usb_hclk_gate] = imx_clk_gate("usb_hclk_gate", "hclk", CCM_PCCR0, 24);
	110	clk[slcdc_gate] = imx_clk_gate("slcdc_gate", "hclk", CCM_PCCR0, 25);
	111	clk[lcdc_hclk_gate] = imx_clk_gate("lcdc_hclk_gate", "hclk", CCM_PCCR0, 26);
	112	clk[emma_hclk_gate] = imx_clk_gate("emma_hclk_gate", "hclk", CCM_PCCR0, 27);
	113	clk[brom_gate] = imx_clk_gate("brom_gate", "hclk", CCM_PCCR0, 28);
	114	clk[dma_hclk_gate] = imx_clk_gate("dma_hclk_gate", "hclk", CCM_PCCR0, 30);
	115	clk[csi_hclk_gate] = imx_clk_gate("csi_hclk_gate", "hclk", CCM_PCCR0, 31);
	116
	117	clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR1, 23);
93421e42	118	clk[wdog_gate] = imx_clk_gate("wdog_gate", "ipg", CCM_PCCR1, 24);
65251690 AS	119	clk[gpt1_ipg_gate] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR1, 25);
	120	clk[gpt2_ipg_gate] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR1, 26);
	121	clk[gpt3_ipg_gate] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR1, 27);
	122	clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR1, 28);
	123	clk[rtc_gate] = imx_clk_gate("rtc_gate", "ipg", CCM_PCCR1, 29);
93421e42 SH	124	clk[kpp_gate] = imx_clk_gate("kpp_gate", "ipg", CCM_PCCR1, 30);
93421e42 SH	125	clk[owire_gate] = imx_clk_gate("owire_gate", "ipg", CCM_PCCR1, 31);
93421e42	126
229be9c1	127	imx_check_clocks(clk, ARRAY_SIZE(clk));
93421e42	128
93421e42 SH	129	clk_register_clkdev(clk[per1], "per", "imx21-uart.0");
	130	clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
	131	clk_register_clkdev(clk[per1], "per", "imx21-uart.1");
	132	clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
	133	clk_register_clkdev(clk[per1], "per", "imx21-uart.2");
	134	clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
	135	clk_register_clkdev(clk[per1], "per", "imx21-uart.3");
	136	clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
	137	clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0");
	138	clk_register_clkdev(clk[per1], "per", "imx-gpt.0");
93421e42 SH	139	clk_register_clkdev(clk[per2], "per", "imx21-cspi.0");
	140	clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx21-cspi.0");
	141	clk_register_clkdev(clk[per2], "per", "imx21-cspi.1");
	142	clk_register_clkdev(clk[cspi2_ipg_gate], "ipg", "imx21-cspi.1");
	143	clk_register_clkdev(clk[per2], "per", "imx21-cspi.2");
	144	clk_register_clkdev(clk[cspi3_ipg_gate], "ipg", "imx21-cspi.2");
e69dc9a9 SG	145	clk_register_clkdev(clk[per3], "per", "imx21-fb.0");
	146	clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx21-fb.0");
	147	clk_register_clkdev(clk[lcdc_hclk_gate], "ahb", "imx21-fb.0");
93421e42 SH	148	clk_register_clkdev(clk[usb_gate], "per", "imx21-hcd.0");
93421e42 SH	149	clk_register_clkdev(clk[usb_hclk_gate], "ahb", "imx21-hcd.0");
4d62435f	150	clk_register_clkdev(clk[nfc_gate], NULL, "imx21-nand.0");
e51d0f0a SG	151	clk_register_clkdev(clk[dma_hclk_gate], "ahb", "imx21-dma");
e51d0f0a SG	152	clk_register_clkdev(clk[dma_gate], "ipg", "imx21-dma");
93421e42	153	clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
5bdfba29	154	clk_register_clkdev(clk[i2c_gate], NULL, "imx21-i2c.0");
93421e42	155	clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0");
93421e42	156
2cfb4518 SH	157	mxc_timer_init(MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR), MX21_INT_GPT1);
2cfb4518 SH	158
93421e42 SH	159	return 0;
93421e42 SH	160	}