Commit | Line | Data |
---|---|---|
e038ed50 SH |
1 | #include <linux/clk.h> |
2 | #include <linux/io.h> | |
3 | #include <linux/module.h> | |
4 | #include <linux/clkdev.h> | |
5 | #include <linux/err.h> | |
6 | #include <linux/clk-provider.h> | |
7 | #include <linux/of.h> | |
8 | ||
e038ed50 | 9 | #include "clk.h" |
e3372474 | 10 | #include "common.h" |
50f2de61 | 11 | #include "hardware.h" |
e038ed50 SH |
12 | |
13 | #define IO_ADDR_CCM(off) (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off))) | |
14 | ||
15 | /* Register offsets */ | |
16 | #define CCM_CSCR IO_ADDR_CCM(0x0) | |
17 | #define CCM_MPCTL0 IO_ADDR_CCM(0x4) | |
18 | #define CCM_MPCTL1 IO_ADDR_CCM(0x8) | |
19 | #define CCM_SPCTL0 IO_ADDR_CCM(0xc) | |
20 | #define CCM_SPCTL1 IO_ADDR_CCM(0x10) | |
21 | #define CCM_OSC26MCTL IO_ADDR_CCM(0x14) | |
22 | #define CCM_PCDR0 IO_ADDR_CCM(0x18) | |
23 | #define CCM_PCDR1 IO_ADDR_CCM(0x1c) | |
24 | #define CCM_PCCR0 IO_ADDR_CCM(0x20) | |
25 | #define CCM_PCCR1 IO_ADDR_CCM(0x24) | |
26 | #define CCM_CCSR IO_ADDR_CCM(0x28) | |
27 | #define CCM_PMCTL IO_ADDR_CCM(0x2c) | |
28 | #define CCM_PMCOUNT IO_ADDR_CCM(0x30) | |
29 | #define CCM_WKGDCTL IO_ADDR_CCM(0x34) | |
30 | ||
31 | #define CCM_CSCR_UPDATE_DIS (1 << 31) | |
32 | #define CCM_CSCR_SSI2 (1 << 23) | |
33 | #define CCM_CSCR_SSI1 (1 << 22) | |
34 | #define CCM_CSCR_VPU (1 << 21) | |
35 | #define CCM_CSCR_MSHC (1 << 20) | |
36 | #define CCM_CSCR_SPLLRES (1 << 19) | |
37 | #define CCM_CSCR_MPLLRES (1 << 18) | |
38 | #define CCM_CSCR_SP (1 << 17) | |
39 | #define CCM_CSCR_MCU (1 << 16) | |
40 | #define CCM_CSCR_OSC26MDIV (1 << 4) | |
41 | #define CCM_CSCR_OSC26M (1 << 3) | |
42 | #define CCM_CSCR_FPM (1 << 2) | |
43 | #define CCM_CSCR_SPEN (1 << 1) | |
44 | #define CCM_CSCR_MPEN (1 << 0) | |
45 | ||
46 | /* i.MX27 TO 2+ */ | |
47 | #define CCM_CSCR_ARM_SRC (1 << 15) | |
48 | ||
49 | #define CCM_SPCTL1_LF (1 << 15) | |
50 | #define CCM_SPCTL1_BRMO (1 << 6) | |
51 | ||
52 | static const char *vpu_sel_clks[] = { "spll", "mpll_main2", }; | |
53 | static const char *cpu_sel_clks[] = { "mpll_main2", "mpll", }; | |
4ea9e857 SH |
54 | static const char *mpll_sel_clks[] = { "fpm", "mpll_osc_sel", }; |
55 | static const char *mpll_osc_sel_clks[] = { "ckih", "ckih_div1p5", }; | |
e038ed50 | 56 | static const char *clko_sel_clks[] = { |
4ea9e857 | 57 | "ckil", "fpm", "ckih", "ckih", |
e038ed50 SH |
58 | "ckih", "mpll", "spll", "cpu_div", |
59 | "ahb", "ipg", "per1_div", "per2_div", | |
60 | "per3_div", "per4_div", "ssi1_div", "ssi2_div", | |
61 | "nfc_div", "mshc_div", "vpu_div", "60m", | |
62 | "32k", "usb_div", "dptc", | |
63 | }; | |
64 | ||
b7eed207 | 65 | static const char *ssi_sel_clks[] = { "spll_gate", "mpll", }; |
e038ed50 SH |
66 | |
67 | enum mx27_clks { | |
68 | dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div, | |
69 | per2_div, per3_div, per4_div, vpu_sel, vpu_div, usb_div, cpu_sel, | |
70 | clko_sel, cpu_div, clko_div, ssi1_sel, ssi2_sel, ssi1_div, ssi2_div, | |
71 | clko_en, ssi2_ipg_gate, ssi1_ipg_gate, slcdc_ipg_gate, sdhc3_ipg_gate, | |
72 | sdhc2_ipg_gate, sdhc1_ipg_gate, scc_ipg_gate, sahara_ipg_gate, | |
73 | rtc_ipg_gate, pwm_ipg_gate, owire_ipg_gate, lcdc_ipg_gate, | |
74 | kpp_ipg_gate, iim_ipg_gate, i2c2_ipg_gate, i2c1_ipg_gate, | |
75 | gpt6_ipg_gate, gpt5_ipg_gate, gpt4_ipg_gate, gpt3_ipg_gate, | |
76 | gpt2_ipg_gate, gpt1_ipg_gate, gpio_ipg_gate, fec_ipg_gate, | |
77 | emma_ipg_gate, dma_ipg_gate, cspi3_ipg_gate, cspi2_ipg_gate, | |
78 | cspi1_ipg_gate, nfc_baud_gate, ssi2_baud_gate, ssi1_baud_gate, | |
79 | vpu_baud_gate, per4_gate, per3_gate, per2_gate, per1_gate, | |
80 | usb_ahb_gate, slcdc_ahb_gate, sahara_ahb_gate, lcdc_ahb_gate, | |
81 | vpu_ahb_gate, fec_ahb_gate, emma_ahb_gate, emi_ahb_gate, dma_ahb_gate, | |
82 | csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate, | |
83 | uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate, | |
4ea9e857 | 84 | uart2_ipg_gate, uart1_ipg_gate, ckih_div1p5, fpm, mpll_osc_sel, |
7654874e AS |
85 | mpll_sel, spll_gate, mshc_div, rtic_ipg_gate, mshc_ipg_gate, |
86 | rtic_ahb_gate, mshc_baud_gate, clk_max | |
e038ed50 SH |
87 | }; |
88 | ||
89 | static struct clk *clk[clk_max]; | |
c20736f1 | 90 | static struct clk_onecell_data clk_data; |
e038ed50 SH |
91 | |
92 | int __init mx27_clocks_init(unsigned long fref) | |
93 | { | |
94 | int i; | |
c20736f1 | 95 | struct device_node *np; |
e038ed50 SH |
96 | |
97 | clk[dummy] = imx_clk_fixed("dummy", 0); | |
98 | clk[ckih] = imx_clk_fixed("ckih", fref); | |
99 | clk[ckil] = imx_clk_fixed("ckil", 32768); | |
4ea9e857 SH |
100 | clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1); |
101 | clk[ckih_div1p5] = imx_clk_fixed_factor("ckih_div1p5", "ckih", 2, 3); | |
102 | ||
103 | clk[mpll_osc_sel] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, | |
104 | mpll_osc_sel_clks, | |
105 | ARRAY_SIZE(mpll_osc_sel_clks)); | |
106 | clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, | |
107 | ARRAY_SIZE(mpll_sel_clks)); | |
108 | clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0); | |
e038ed50 | 109 | clk[spll] = imx_clk_pllv1("spll", "ckih", CCM_SPCTL0); |
b7eed207 | 110 | clk[spll_gate] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); |
e038ed50 SH |
111 | clk[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3); |
112 | ||
113 | if (mx27_revision() >= IMX_CHIP_REVISION_2_0) { | |
114 | clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2); | |
115 | clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); | |
116 | } else { | |
117 | clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4); | |
118 | clk[ipg] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1); | |
119 | } | |
120 | ||
7654874e | 121 | clk[mshc_div] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6); |
e038ed50 SH |
122 | clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4); |
123 | clk[per1_div] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6); | |
124 | clk[per2_div] = imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6); | |
125 | clk[per3_div] = imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6); | |
126 | clk[per4_div] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6); | |
127 | clk[vpu_sel] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks)); | |
3b4d6c82 | 128 | clk[vpu_div] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6); |
b7eed207 | 129 | clk[usb_div] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 28, 3); |
e038ed50 SH |
130 | clk[cpu_sel] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks)); |
131 | clk[clko_sel] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks)); | |
132 | if (mx27_revision() >= IMX_CHIP_REVISION_2_0) | |
133 | clk[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 12, 2); | |
134 | else | |
135 | clk[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 13, 3); | |
136 | clk[clko_div] = imx_clk_divider("clko_div", "clko_sel", CCM_PCDR0, 22, 3); | |
137 | clk[ssi1_sel] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks)); | |
138 | clk[ssi2_sel] = imx_clk_mux("ssi2_sel", CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks)); | |
139 | clk[ssi1_div] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6); | |
3b4d6c82 | 140 | clk[ssi2_div] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6); |
e038ed50 SH |
141 | clk[clko_en] = imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0); |
142 | clk[ssi2_ipg_gate] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0); | |
143 | clk[ssi1_ipg_gate] = imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1); | |
144 | clk[slcdc_ipg_gate] = imx_clk_gate("slcdc_ipg_gate", "ipg", CCM_PCCR0, 2); | |
145 | clk[sdhc3_ipg_gate] = imx_clk_gate("sdhc3_ipg_gate", "ipg", CCM_PCCR0, 3); | |
146 | clk[sdhc2_ipg_gate] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 4); | |
147 | clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5); | |
148 | clk[scc_ipg_gate] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6); | |
149 | clk[sahara_ipg_gate] = imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7); | |
7654874e | 150 | clk[rtic_ipg_gate] = imx_clk_gate("rtic_ipg_gate", "ipg", CCM_PCCR0, 8); |
e038ed50 SH |
151 | clk[rtc_ipg_gate] = imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9); |
152 | clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11); | |
153 | clk[owire_ipg_gate] = imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12); | |
7654874e | 154 | clk[mshc_ipg_gate] = imx_clk_gate("mshc_ipg_gate", "ipg", CCM_PCCR0, 13); |
e038ed50 SH |
155 | clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14); |
156 | clk[kpp_ipg_gate] = imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15); | |
157 | clk[iim_ipg_gate] = imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16); | |
158 | clk[i2c2_ipg_gate] = imx_clk_gate("i2c2_ipg_gate", "ipg", CCM_PCCR0, 17); | |
159 | clk[i2c1_ipg_gate] = imx_clk_gate("i2c1_ipg_gate", "ipg", CCM_PCCR0, 18); | |
160 | clk[gpt6_ipg_gate] = imx_clk_gate("gpt6_ipg_gate", "ipg", CCM_PCCR0, 19); | |
161 | clk[gpt5_ipg_gate] = imx_clk_gate("gpt5_ipg_gate", "ipg", CCM_PCCR0, 20); | |
162 | clk[gpt4_ipg_gate] = imx_clk_gate("gpt4_ipg_gate", "ipg", CCM_PCCR0, 21); | |
163 | clk[gpt3_ipg_gate] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR0, 22); | |
164 | clk[gpt2_ipg_gate] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR0, 23); | |
165 | clk[gpt1_ipg_gate] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR0, 24); | |
166 | clk[gpio_ipg_gate] = imx_clk_gate("gpio_ipg_gate", "ipg", CCM_PCCR0, 25); | |
167 | clk[fec_ipg_gate] = imx_clk_gate("fec_ipg_gate", "ipg", CCM_PCCR0, 26); | |
168 | clk[emma_ipg_gate] = imx_clk_gate("emma_ipg_gate", "ipg", CCM_PCCR0, 27); | |
169 | clk[dma_ipg_gate] = imx_clk_gate("dma_ipg_gate", "ipg", CCM_PCCR0, 28); | |
170 | clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29); | |
171 | clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30); | |
172 | clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31); | |
7654874e | 173 | clk[mshc_baud_gate] = imx_clk_gate("mshc_baud_gate", "mshc_div", CCM_PCCR1, 2); |
e038ed50 SH |
174 | clk[nfc_baud_gate] = imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1, 3); |
175 | clk[ssi2_baud_gate] = imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1, 4); | |
176 | clk[ssi1_baud_gate] = imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1, 5); | |
177 | clk[vpu_baud_gate] = imx_clk_gate("vpu_baud_gate", "vpu_div", CCM_PCCR1, 6); | |
178 | clk[per4_gate] = imx_clk_gate("per4_gate", "per4_div", CCM_PCCR1, 7); | |
179 | clk[per3_gate] = imx_clk_gate("per3_gate", "per3_div", CCM_PCCR1, 8); | |
180 | clk[per2_gate] = imx_clk_gate("per2_gate", "per2_div", CCM_PCCR1, 9); | |
181 | clk[per1_gate] = imx_clk_gate("per1_gate", "per1_div", CCM_PCCR1, 10); | |
182 | clk[usb_ahb_gate] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11); | |
183 | clk[slcdc_ahb_gate] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12); | |
184 | clk[sahara_ahb_gate] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13); | |
7654874e | 185 | clk[rtic_ahb_gate] = imx_clk_gate("rtic_ahb_gate", "ahb", CCM_PCCR1, 14); |
e038ed50 SH |
186 | clk[lcdc_ahb_gate] = imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15); |
187 | clk[vpu_ahb_gate] = imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16); | |
188 | clk[fec_ahb_gate] = imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17); | |
189 | clk[emma_ahb_gate] = imx_clk_gate("emma_ahb_gate", "ahb", CCM_PCCR1, 18); | |
190 | clk[emi_ahb_gate] = imx_clk_gate("emi_ahb_gate", "ahb", CCM_PCCR1, 19); | |
191 | clk[dma_ahb_gate] = imx_clk_gate("dma_ahb_gate", "ahb", CCM_PCCR1, 20); | |
192 | clk[csi_ahb_gate] = imx_clk_gate("csi_ahb_gate", "ahb", CCM_PCCR1, 21); | |
193 | clk[brom_ahb_gate] = imx_clk_gate("brom_ahb_gate", "ahb", CCM_PCCR1, 22); | |
194 | clk[ata_ahb_gate] = imx_clk_gate("ata_ahb_gate", "ahb", CCM_PCCR1, 23); | |
195 | clk[wdog_ipg_gate] = imx_clk_gate("wdog_ipg_gate", "ipg", CCM_PCCR1, 24); | |
196 | clk[usb_ipg_gate] = imx_clk_gate("usb_ipg_gate", "ipg", CCM_PCCR1, 25); | |
197 | clk[uart6_ipg_gate] = imx_clk_gate("uart6_ipg_gate", "ipg", CCM_PCCR1, 26); | |
198 | clk[uart5_ipg_gate] = imx_clk_gate("uart5_ipg_gate", "ipg", CCM_PCCR1, 27); | |
199 | clk[uart4_ipg_gate] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR1, 28); | |
200 | clk[uart3_ipg_gate] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR1, 29); | |
201 | clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30); | |
202 | clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31); | |
203 | ||
204 | for (i = 0; i < ARRAY_SIZE(clk); i++) | |
205 | if (IS_ERR(clk[i])) | |
206 | pr_err("i.MX27 clk %d: register failed with %ld\n", | |
207 | i, PTR_ERR(clk[i])); | |
208 | ||
c20736f1 FE |
209 | np = of_find_compatible_node(NULL, NULL, "fsl,imx27-ccm"); |
210 | if (np) { | |
211 | clk_data.clks = clk; | |
212 | clk_data.clk_num = ARRAY_SIZE(clk); | |
213 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | |
214 | } | |
215 | ||
e038ed50 SH |
216 | clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0"); |
217 | clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.0"); | |
218 | clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1"); | |
219 | clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.1"); | |
220 | clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2"); | |
221 | clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.2"); | |
222 | clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3"); | |
223 | clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.3"); | |
224 | clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4"); | |
225 | clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.4"); | |
226 | clk_register_clkdev(clk[uart6_ipg_gate], "ipg", "imx21-uart.5"); | |
227 | clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.5"); | |
228 | clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0"); | |
229 | clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.0"); | |
7f917a8d SG |
230 | clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.0"); |
231 | clk_register_clkdev(clk[sdhc1_ipg_gate], "ipg", "imx21-mmc.0"); | |
232 | clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.1"); | |
233 | clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.1"); | |
234 | clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.2"); | |
235 | clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.2"); | |
4a3ef226 GGM |
236 | clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.0"); |
237 | clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx27-cspi.0"); | |
238 | clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.1"); | |
239 | clk_register_clkdev(clk[cspi2_ipg_gate], "ipg", "imx27-cspi.1"); | |
240 | clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.2"); | |
241 | clk_register_clkdev(clk[cspi3_ipg_gate], "ipg", "imx27-cspi.2"); | |
e69dc9a9 SG |
242 | clk_register_clkdev(clk[per3_gate], "per", "imx21-fb.0"); |
243 | clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx21-fb.0"); | |
244 | clk_register_clkdev(clk[lcdc_ahb_gate], "ahb", "imx21-fb.0"); | |
27b76486 | 245 | clk_register_clkdev(clk[csi_ahb_gate], "ahb", "imx27-camera.0"); |
6efc7823 | 246 | clk_register_clkdev(clk[per4_gate], "per", "imx27-camera.0"); |
61c4b560 PC |
247 | clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27"); |
248 | clk_register_clkdev(clk[usb_ipg_gate], "ipg", "imx-udc-mx27"); | |
249 | clk_register_clkdev(clk[usb_ahb_gate], "ahb", "imx-udc-mx27"); | |
e038ed50 SH |
250 | clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0"); |
251 | clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.0"); | |
252 | clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.0"); | |
253 | clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1"); | |
254 | clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.1"); | |
255 | clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.1"); | |
256 | clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2"); | |
257 | clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.2"); | |
258 | clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.2"); | |
259 | clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0"); | |
260 | clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1"); | |
4d62435f | 261 | clk_register_clkdev(clk[nfc_baud_gate], NULL, "imx27-nand.0"); |
6d8c4529 JM |
262 | clk_register_clkdev(clk[vpu_baud_gate], "per", "coda-imx27.0"); |
263 | clk_register_clkdev(clk[vpu_ahb_gate], "ahb", "coda-imx27.0"); | |
e51d0f0a SG |
264 | clk_register_clkdev(clk[dma_ahb_gate], "ahb", "imx27-dma"); |
265 | clk_register_clkdev(clk[dma_ipg_gate], "ipg", "imx27-dma"); | |
e038ed50 SH |
266 | clk_register_clkdev(clk[fec_ipg_gate], "ipg", "imx27-fec.0"); |
267 | clk_register_clkdev(clk[fec_ahb_gate], "ahb", "imx27-fec.0"); | |
268 | clk_register_clkdev(clk[wdog_ipg_gate], NULL, "imx2-wdt.0"); | |
5bdfba29 SG |
269 | clk_register_clkdev(clk[i2c1_ipg_gate], NULL, "imx21-i2c.0"); |
270 | clk_register_clkdev(clk[i2c2_ipg_gate], NULL, "imx21-i2c.1"); | |
e038ed50 SH |
271 | clk_register_clkdev(clk[owire_ipg_gate], NULL, "mxc_w1.0"); |
272 | clk_register_clkdev(clk[kpp_ipg_gate], NULL, "imx-keypad"); | |
27b76486 SG |
273 | clk_register_clkdev(clk[emma_ahb_gate], "emma-ahb", "imx27-camera.0"); |
274 | clk_register_clkdev(clk[emma_ipg_gate], "emma-ipg", "imx27-camera.0"); | |
9de76b6d JM |
275 | clk_register_clkdev(clk[emma_ahb_gate], "ahb", "m2m-emmaprp.0"); |
276 | clk_register_clkdev(clk[emma_ipg_gate], "ipg", "m2m-emmaprp.0"); | |
3d10a887 | 277 | clk_register_clkdev(clk[cpu_div], NULL, "cpu0"); |
e038ed50 | 278 | |
2cfb4518 | 279 | mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1); |
e038ed50 SH |
280 | |
281 | clk_prepare_enable(clk[emi_ahb_gate]); | |
282 | ||
1b76b74d FE |
283 | imx_print_silicon_rev("i.MX27", mx27_revision()); |
284 | ||
e038ed50 SH |
285 | return 0; |
286 | } | |
287 | ||
e038ed50 SH |
288 | int __init mx27_clocks_init_dt(void) |
289 | { | |
290 | struct device_node *np; | |
291 | u32 fref = 26000000; /* default */ | |
292 | ||
293 | for_each_compatible_node(np, NULL, "fixed-clock") { | |
294 | if (!of_device_is_compatible(np, "fsl,imx-osc26m")) | |
295 | continue; | |
296 | ||
297 | if (!of_property_read_u32(np, "clock-frequency", &fref)) | |
298 | break; | |
299 | } | |
300 | ||
301 | return mx27_clocks_init(fref); | |
302 | } |