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ARM: imx: add clk-pllv1 type support
[deliverable/linux.git] / arch / arm / mach-imx / clk-imx31.c
CommitLineData
95878cbe
SH		 1/*
2 * Copyright (C) 2012 Sascha Hauer <kernel@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation.
16 */
17
18#include <linux/module.h>
19#include <linux/clk.h>
20#include <linux/clkdev.h>
21#include <linux/io.h>
22#include <linux/err.h>
d2a37b3d 23#include <linux/of.h>
95878cbe 24
95878cbe 25#include "clk.h"
e3372474 26#include "common.h"
95878cbe 27#include "crmregs-imx3.h"
50f2de61
SG		 28#include "hardware.h"
29#include "mx31.h"
95878cbe
SH		 30
31static const char *mcu_main_sel[] = { "spll", "mpll", };
32static const char *per_sel[] = { "per_div", "ipg", };
33static const char *csi_sel[] = { "upll", "spll", };
34static const char *fir_sel[] = { "mcu_main", "upll", "spll" };
35
36enum mx31_clks {
8a1a9540
FE		 37 dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg,
38 per_div, per, csi, fir, csi_div, usb_div_pre, usb_div_post, fir_div_pre,
95878cbe
SH		 39 fir_div_post, sdhc1_gate, sdhc2_gate, gpt_gate, epit1_gate, epit2_gate,
40 iim_gate, ata_gate, sdma_gate, cspi3_gate, rng_gate, uart1_gate,
41 uart2_gate, ssi1_gate, i2c1_gate, i2c2_gate, i2c3_gate, hantro_gate,
42 mstick1_gate, mstick2_gate, csi_gate, rtc_gate, wdog_gate, pwm_gate,
43 sim_gate, ect_gate, usb_gate, kpp_gate, ipu_gate, uart3_gate,
44 uart4_gate, uart5_gate, owire_gate, ssi2_gate, cspi1_gate, cspi2_gate,
45 gacc_gate, emi_gate, rtic_gate, firi_gate, clk_max
46};
47
48static struct clk *clk[clk_max];
ef0e4a60 49static struct clk_onecell_data clk_data;
95878cbe
SH		 50
51int __init mx31_clocks_init(unsigned long fref)
52{
5ab96a8d 53 void __iomem *base;
ef0e4a60 54 struct device_node *np;
95878cbe 55
5ab96a8d
SG		 56 base = ioremap(MX31_CCM_BASE_ADDR, SZ_4K);
57 BUG_ON(!base);
58
8a1a9540 59 clk[dummy] = imx_clk_fixed("dummy", 0);
95878cbe
SH		 60 clk[ckih] = imx_clk_fixed("ckih", fref);
61 clk[ckil] = imx_clk_fixed("ckil", 32768);
3bec5f81
SG		 62 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "mpll", "ckih", base + MXC_CCM_MPCTL);
63 clk[spll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "spll", "ckih", base + MXC_CCM_SRPCTL);
64 clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "upll", "ckih", base + MXC_CCM_UPCTL);
95878cbe
SH		 65 clk[mcu_main] = imx_clk_mux("mcu_main", base + MXC_CCM_PMCR0, 31, 1, mcu_main_sel, ARRAY_SIZE(mcu_main_sel));
66 clk[hsp] = imx_clk_divider("hsp", "mcu_main", base + MXC_CCM_PDR0, 11, 3);
67 clk[ahb] = imx_clk_divider("ahb", "mcu_main", base + MXC_CCM_PDR0, 3, 3);
68 clk[nfc] = imx_clk_divider("nfc", "ahb", base + MXC_CCM_PDR0, 8, 3);
69 clk[ipg] = imx_clk_divider("ipg", "ahb", base + MXC_CCM_PDR0, 6, 2);
70 clk[per_div] = imx_clk_divider("per_div", "upll", base + MXC_CCM_PDR0, 16, 5);
71 clk[per] = imx_clk_mux("per", base + MXC_CCM_CCMR, 24, 1, per_sel, ARRAY_SIZE(per_sel));
72 clk[csi] = imx_clk_mux("csi_sel", base + MXC_CCM_CCMR, 25, 1, csi_sel, ARRAY_SIZE(csi_sel));
73 clk[fir] = imx_clk_mux("fir_sel", base + MXC_CCM_CCMR, 11, 2, fir_sel, ARRAY_SIZE(fir_sel));
74 clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MXC_CCM_PDR0, 23, 9);
75 clk[usb_div_pre] = imx_clk_divider("usb_div_pre", "upll", base + MXC_CCM_PDR1, 30, 2);
76 clk[usb_div_post] = imx_clk_divider("usb_div_post", "usb_div_pre", base + MXC_CCM_PDR1, 27, 3);
77 clk[fir_div_pre] = imx_clk_divider("fir_div_pre", "fir_sel", base + MXC_CCM_PDR1, 24, 3);
78 clk[fir_div_post] = imx_clk_divider("fir_div_post", "fir_div_pre", base + MXC_CCM_PDR1, 23, 6);
79 clk[sdhc1_gate] = imx_clk_gate2("sdhc1_gate", "per", base + MXC_CCM_CGR0, 0);
80 clk[sdhc2_gate] = imx_clk_gate2("sdhc2_gate", "per", base + MXC_CCM_CGR0, 2);
81 clk[gpt_gate] = imx_clk_gate2("gpt_gate", "per", base + MXC_CCM_CGR0, 4);
82 clk[epit1_gate] = imx_clk_gate2("epit1_gate", "per", base + MXC_CCM_CGR0, 6);
83 clk[epit2_gate] = imx_clk_gate2("epit2_gate", "per", base + MXC_CCM_CGR0, 8);
84 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MXC_CCM_CGR0, 10);
85 clk[ata_gate] = imx_clk_gate2("ata_gate", "ipg", base + MXC_CCM_CGR0, 12);
86 clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MXC_CCM_CGR0, 14);
87 clk[cspi3_gate] = imx_clk_gate2("cspi3_gate", "ipg", base + MXC_CCM_CGR0, 16);
88 clk[rng_gate] = imx_clk_gate2("rng_gate", "ipg", base + MXC_CCM_CGR0, 18);
89 clk[uart1_gate] = imx_clk_gate2("uart1_gate", "per", base + MXC_CCM_CGR0, 20);
90 clk[uart2_gate] = imx_clk_gate2("uart2_gate", "per", base + MXC_CCM_CGR0, 22);
91 clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "spll", base + MXC_CCM_CGR0, 24);
92 clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per", base + MXC_CCM_CGR0, 26);
93 clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per", base + MXC_CCM_CGR0, 28);
94 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per", base + MXC_CCM_CGR0, 30);
95 clk[hantro_gate] = imx_clk_gate2("hantro_gate", "per", base + MXC_CCM_CGR1, 0);
96 clk[mstick1_gate] = imx_clk_gate2("mstick1_gate", "per", base + MXC_CCM_CGR1, 2);
97 clk[mstick2_gate] = imx_clk_gate2("mstick2_gate", "per", base + MXC_CCM_CGR1, 4);
98 clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MXC_CCM_CGR1, 6);
99 clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MXC_CCM_CGR1, 8);
100 clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MXC_CCM_CGR1, 10);
101 clk[pwm_gate] = imx_clk_gate2("pwm_gate", "per", base + MXC_CCM_CGR1, 12);
102 clk[sim_gate] = imx_clk_gate2("sim_gate", "per", base + MXC_CCM_CGR1, 14);
103 clk[ect_gate] = imx_clk_gate2("ect_gate", "per", base + MXC_CCM_CGR1, 16);
104 clk[usb_gate] = imx_clk_gate2("usb_gate", "ahb", base + MXC_CCM_CGR1, 18);
105 clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MXC_CCM_CGR1, 20);
106 clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MXC_CCM_CGR1, 22);
107 clk[uart3_gate] = imx_clk_gate2("uart3_gate", "per", base + MXC_CCM_CGR1, 24);
108 clk[uart4_gate] = imx_clk_gate2("uart4_gate", "per", base + MXC_CCM_CGR1, 26);
109 clk[uart5_gate] = imx_clk_gate2("uart5_gate", "per", base + MXC_CCM_CGR1, 28);
110 clk[owire_gate] = imx_clk_gate2("owire_gate", "per", base + MXC_CCM_CGR1, 30);
111 clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "spll", base + MXC_CCM_CGR2, 0);
112 clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MXC_CCM_CGR2, 2);
113 clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MXC_CCM_CGR2, 4);
114 clk[gacc_gate] = imx_clk_gate2("gacc_gate", "per", base + MXC_CCM_CGR2, 6);
115 clk[emi_gate] = imx_clk_gate2("emi_gate", "ahb", base + MXC_CCM_CGR2, 8);
116 clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10);
117 clk[firi_gate] = imx_clk_gate2("firi_gate", "upll", base+MXC_CCM_CGR2, 12);
118
229be9c1 119 imx_check_clocks(clk, ARRAY_SIZE(clk));
95878cbe 120
ef0e4a60
FE		 121 np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm");
122
123 if (np) {
124 clk_data.clks = clk;
125 clk_data.clk_num = ARRAY_SIZE(clk);
126 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
127 }
128
95878cbe
SH		 129 clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
130 clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
131 clk_register_clkdev(clk[cspi1_gate], NULL, "imx31-cspi.0");
132 clk_register_clkdev(clk[cspi2_gate], NULL, "imx31-cspi.1");
133 clk_register_clkdev(clk[cspi3_gate], NULL, "imx31-cspi.2");
134 clk_register_clkdev(clk[pwm_gate], "pwm", NULL);
135 clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
bb1d34a2 136 clk_register_clkdev(clk[rtc_gate], NULL, "imx21-rtc");
95878cbe
SH		 137 clk_register_clkdev(clk[epit1_gate], "epit", NULL);
138 clk_register_clkdev(clk[epit2_gate], "epit", NULL);
4d62435f 139 clk_register_clkdev(clk[nfc], NULL, "imx27-nand.0");
95878cbe
SH		 140 clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core");
141 clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
8cc7a2b9 142 clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad");
95878cbe
SH		 143 clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.0");
144 clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.0");
145 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
146 clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.1");
147 clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.1");
148 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1");
149 clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.2");
150 clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.2");
151 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
61c4b560
PC		 152 clk_register_clkdev(clk[usb_div_post], "per", "imx-udc-mx27");
153 clk_register_clkdev(clk[usb_gate], "ahb", "imx-udc-mx27");
154 clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27");
95878cbe
SH		 155 clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");
156 /* i.mx31 has the i.mx21 type uart */
157 clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");
158 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");
159 clk_register_clkdev(clk[uart2_gate], "per", "imx21-uart.1");
160 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1");
161 clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2");
162 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2");
163 clk_register_clkdev(clk[uart4_gate], "per", "imx21-uart.3");
164 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.3");
165 clk_register_clkdev(clk[uart5_gate], "per", "imx21-uart.4");
166 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.4");
5bdfba29
SG		 167 clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0");
168 clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1");
169 clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2");
95878cbe 170 clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0");
7f917a8d
SG		 171 clk_register_clkdev(clk[sdhc1_gate], NULL, "imx31-mmc.0");
172 clk_register_clkdev(clk[sdhc2_gate], NULL, "imx31-mmc.1");
95878cbe
SH		 173 clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");
174 clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1");
175 clk_register_clkdev(clk[firi_gate], "firi", NULL);
176 clk_register_clkdev(clk[ata_gate], NULL, "pata_imx");
177 clk_register_clkdev(clk[rtic_gate], "rtic", NULL);
14ac5b88 178 clk_register_clkdev(clk[rng_gate], NULL, "mxc_rnga");
95878cbe
SH		 179 clk_register_clkdev(clk[sdma_gate], NULL, "imx31-sdma");
180 clk_register_clkdev(clk[iim_gate], "iim", NULL);
181
182 clk_set_parent(clk[csi], clk[upll]);
183 clk_prepare_enable(clk[emi_gate]);
184 clk_prepare_enable(clk[iim_gate]);
185 mx31_revision();
186 clk_disable_unprepare(clk[iim_gate]);
187
6c529c49 188 mxc_timer_init(MX31_GPT1_BASE_ADDR, MX31_INT_GPT);
95878cbe
SH		 189
190 return 0;
191}
d2a37b3d 192
d2a37b3d
DGC		 193int __init mx31_clocks_init_dt(void)
194{
195 struct device_node *np;
196 u32 fref = 26000000; /* default */
197
198 for_each_compatible_node(np, NULL, "fixed-clock") {
199 if (!of_device_is_compatible(np, "fsl,imx-osc26m"))
200 continue;
201
202 if (!of_property_read_u32(np, "clock-frequency", &fref))
203 break;
204 }
205
206 return mx31_clocks_init(fref);
207}
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