projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
staging: drm/imx: Use SRC to reset IPU
[deliverable/linux.git] / arch / arm / mach-imx / clk-imx51-imx53.c
CommitLineData
b8d4176f
SH		 1/*
2 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9#include <linux/mm.h>
10#include <linux/delay.h>
11#include <linux/clk.h>
12#include <linux/io.h>
13#include <linux/clkdev.h>
14#include <linux/of.h>
15#include <linux/err.h>
16
b8d4176f
SH		 17#include "crm-regs-imx5.h"
18#include "clk.h"
e3372474 19#include "common.h"
50f2de61 20#include "hardware.h"
b8d4176f
SH		 21
22/* Low-power Audio Playback Mode clock */
23static const char *lp_apm_sel[] = { "osc", };
24
25/* This is used multiple times */
26static const char *standard_pll_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "lp_apm", };
27static const char *periph_apm_sel[] = { "pll1_sw", "pll3_sw", "lp_apm", };
28static const char *main_bus_sel[] = { "pll2_sw", "periph_apm", };
29static const char *per_lp_apm_sel[] = { "main_bus", "lp_apm", };
30static const char *per_root_sel[] = { "per_podf", "ipg", };
31static const char *esdhc_c_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
32static const char *esdhc_d_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
13b3a07a
SG		 33static const char *ssi_apm_sels[] = { "ckih1", "lp_amp", "ckih2", };
34static const char *ssi_clk_sels[] = { "pll1_sw", "pll2_sw", "pll3_sw", "ssi_apm", };
35static const char *ssi3_clk_sels[] = { "ssi1_root_gate", "ssi2_root_gate", };
36static const char *ssi_ext1_com_sels[] = { "ssi_ext1_podf", "ssi1_root_gate", };
37static const char *ssi_ext2_com_sels[] = { "ssi_ext2_podf", "ssi2_root_gate", };
b8d4176f
SH		 38static const char *emi_slow_sel[] = { "main_bus", "ahb", };
39static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", };
40static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", };
51f66191 41static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0_gate", };
b8d4176f
SH		 42static const char *mx53_ldb_di0_sel[] = { "pll3_sw", "pll4_sw", };
43static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", };
51f66191 44static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1_gate", };
b8d4176f
SH		 45static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", };
46static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", };
47static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", };
48static const char *tve_sel[] = { "tve_pred", "tve_ext_sel", };
49static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
8ecb167f
PZ		 50static const char *gpu3d_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" };
51static const char *gpu2d_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" };
b8d4176f 52static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
a745f039 53static const char *mx53_can_sel[] = { "ipg", "ckih1", "ckih2", "lp_apm", };
b8d4176f
SH		 54
55enum imx5_clks {
56 dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred,
57 uart_root, esdhc_a_pred, esdhc_b_pred, esdhc_c_s, esdhc_d_s,
58 emi_sel, emi_slow_podf, nfc_podf, ecspi_pred, ecspi_podf, usboh3_pred,
59 usboh3_podf, usb_phy_pred, usb_phy_podf, cpu_podf, di_pred, tve_di,
60 tve_s, uart1_ipg_gate, uart1_per_gate, uart2_ipg_gate,
61 uart2_per_gate, uart3_ipg_gate, uart3_per_gate, i2c1_gate, i2c2_gate,
62 gpt_ipg_gate, pwm1_ipg_gate, pwm1_hf_gate, pwm2_ipg_gate, pwm2_hf_gate,
0f3557c3 63 gpt_hf_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate,
b8d4176f
SH		 64 esdhc3_ipg_gate, esdhc4_ipg_gate, ssi1_ipg_gate, ssi2_ipg_gate,
65 ssi3_ipg_gate, ecspi1_ipg_gate, ecspi1_per_gate, ecspi2_ipg_gate,
66 ecspi2_per_gate, cspi_ipg_gate, sdma_gate, emi_slow_gate, ipu_s,
67 ipu_gate, nfc_gate, ipu_di1_gate, vpu_s, vpu_gate,
68 vpu_reference_gate, uart4_ipg_gate, uart4_per_gate, uart5_ipg_gate,
69 uart5_per_gate, tve_gate, tve_pred, esdhc1_per_gate, esdhc2_per_gate,
70 esdhc3_per_gate, esdhc4_per_gate, usb_phy_gate, hsi2c_gate,
71 mipi_hsc1_gate, mipi_hsc2_gate, mipi_esc_gate, mipi_hsp_gate,
72 ldb_di1_div_3_5, ldb_di1_div, ldb_di0_div_3_5, ldb_di0_div,
73 ldb_di1_gate, can2_serial_gate, can2_ipg_gate, i2c3_gate, lp_apm,
74 periph_apm, main_bus, ahb_max, aips_tz1, aips_tz2, tmax1, tmax2,
75 tmax3, spba, uart_sel, esdhc_a_sel, esdhc_b_sel, esdhc_a_podf,
76 esdhc_b_podf, ecspi_sel, usboh3_sel, usb_phy_sel, iim_gate,
77 usboh3_gate, emi_fast_gate, ipu_di0_gate,gpc_dvfs, pll1_sw, pll2_sw,
78 pll3_sw, ipu_di0_sel, ipu_di1_sel, tve_ext_sel, mx51_mipi, pll4_sw,
79 ldb_di1_sel, di_pll4_podf, ldb_di0_sel, ldb_di0_gate, usb_phy1_gate,
80 usb_phy2_gate, per_lp_apm, per_pred1, per_pred2, per_podf, per_root,
13b3a07a
SG		 81 ssi_apm, ssi1_root_sel, ssi2_root_sel, ssi3_root_sel, ssi_ext1_sel,
82 ssi_ext2_sel, ssi_ext1_com_sel, ssi_ext2_com_sel, ssi1_root_pred,
83 ssi1_root_podf, ssi2_root_pred, ssi2_root_podf, ssi_ext1_pred,
84 ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate,
85 ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate,
d1e9e0ea 86 epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate,
a745f039 87 can_sel, can1_serial_gate, can1_ipg_gate,
8ecb167f 88 owire_gate, gpu3d_s, gpu2d_s, gpu3d_gate, gpu2d_gate, garb_gate,
b8d4176f
SH		 89 clk_max
90};
91
92static struct clk *clk[clk_max];
f40f38d1 93static struct clk_onecell_data clk_data;
b8d4176f
SH		 94
95static void __init mx5_clocks_common_init(unsigned long rate_ckil,
96 unsigned long rate_osc, unsigned long rate_ckih1,
97 unsigned long rate_ckih2)
98{
99 int i;
100
101 clk[dummy] = imx_clk_fixed("dummy", 0);
102 clk[ckil] = imx_clk_fixed("ckil", rate_ckil);
103 clk[osc] = imx_clk_fixed("osc", rate_osc);
104 clk[ckih1] = imx_clk_fixed("ckih1", rate_ckih1);
105 clk[ckih2] = imx_clk_fixed("ckih2", rate_ckih2);
106
107 clk[lp_apm] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
108 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
109 clk[periph_apm] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
110 periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
111 clk[main_bus] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
112 main_bus_sel, ARRAY_SIZE(main_bus_sel));
c040be00 113 clk[per_lp_apm] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1,
b8d4176f
SH		 114 per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
115 clk[per_pred1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2);
116 clk[per_pred2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3);
117 clk[per_podf] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3);
c040be00 118 clk[per_root] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1,
b8d4176f
SH		 119 per_root_sel, ARRAY_SIZE(per_root_sel));
120 clk[ahb] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3);
121 clk[ahb_max] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28);
122 clk[aips_tz1] = imx_clk_gate2("aips_tz1", "ahb", MXC_CCM_CCGR0, 24);
123 clk[aips_tz2] = imx_clk_gate2("aips_tz2", "ahb", MXC_CCM_CCGR0, 26);
124 clk[tmax1] = imx_clk_gate2("tmax1", "ahb", MXC_CCM_CCGR1, 0);
125 clk[tmax2] = imx_clk_gate2("tmax2", "ahb", MXC_CCM_CCGR1, 2);
126 clk[tmax3] = imx_clk_gate2("tmax3", "ahb", MXC_CCM_CCGR1, 4);
127 clk[spba] = imx_clk_gate2("spba", "ipg", MXC_CCM_CCGR5, 0);
128 clk[ipg] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2);
129 clk[axi_a] = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3);
130 clk[axi_b] = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3);
131 clk[uart_sel] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2,
132 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
133 clk[uart_pred] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3);
134 clk[uart_root] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3);
135
136 clk[esdhc_a_sel] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,
137 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
138 clk[esdhc_b_sel] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
139 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
140 clk[esdhc_a_pred] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3);
141 clk[esdhc_a_podf] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3);
142 clk[esdhc_b_pred] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3);
143 clk[esdhc_b_podf] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3);
144 clk[esdhc_c_s] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
145 clk[esdhc_d_s] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
146
147 clk[emi_sel] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1,
148 emi_slow_sel, ARRAY_SIZE(emi_slow_sel));
149 clk[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3);
150 clk[nfc_podf] = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3);
151 clk[ecspi_sel] = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2,
152 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
153 clk[ecspi_pred] = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3);
154 clk[ecspi_podf] = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6);
155 clk[usboh3_sel] = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2,
156 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
157 clk[usboh3_pred] = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3);
158 clk[usboh3_podf] = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2);
159 clk[usb_phy_pred] = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3);
160 clk[usb_phy_podf] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3);
161 clk[usb_phy_sel] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1,
162 usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
163 clk[cpu_podf] = imx_clk_divider("cpu_podf", "pll1_sw", MXC_CCM_CACRR, 0, 3);
164 clk[di_pred] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3);
165 clk[tve_di] = imx_clk_fixed("tve_di", 65000000); /* FIXME */
166 clk[tve_s] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1, tve_sel, ARRAY_SIZE(tve_sel));
167 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30);
168 clk[uart1_ipg_gate] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6);
169 clk[uart1_per_gate] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8);
170 clk[uart2_ipg_gate] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10);
171 clk[uart2_per_gate] = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12);
172 clk[uart3_ipg_gate] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14);
173 clk[uart3_per_gate] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16);
174 clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18);
175 clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20);
b8d4176f 176 clk[pwm1_ipg_gate] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10);
796b72cc 177 clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12);
b8d4176f 178 clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14);
796b72cc 179 clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16);
0f3557c3
AS		 180 clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18);
181 clk[gpt_hf_gate] = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20);
b8d4176f
SH		 182 clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24);
183 clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26);
184 clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28);
185 clk[esdhc1_ipg_gate] = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0);
186 clk[esdhc2_ipg_gate] = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4);
187 clk[esdhc3_ipg_gate] = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8);
188 clk[esdhc4_ipg_gate] = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12);
189 clk[ssi1_ipg_gate] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16);
190 clk[ssi2_ipg_gate] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20);
191 clk[ssi3_ipg_gate] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24);
192 clk[ecspi1_ipg_gate] = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18);
193 clk[ecspi1_per_gate] = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20);
194 clk[ecspi2_ipg_gate] = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22);
195 clk[ecspi2_per_gate] = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24);
196 clk[cspi_ipg_gate] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26);
197 clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30);
198 clk[emi_fast_gate] = imx_clk_gate2("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14);
199 clk[emi_slow_gate] = imx_clk_gate2("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16);
200 clk[ipu_s] = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel));
201 clk[ipu_gate] = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10);
202 clk[nfc_gate] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20);
203 clk[ipu_di0_gate] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10);
204 clk[ipu_di1_gate] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12);
8ecb167f
PZ		 205 clk[gpu3d_s] = imx_clk_mux("gpu3d_sel", MXC_CCM_CBCMR, 4, 2, gpu3d_sel, ARRAY_SIZE(gpu3d_sel));
206 clk[gpu2d_s] = imx_clk_mux("gpu2d_sel", MXC_CCM_CBCMR, 16, 2, gpu2d_sel, ARRAY_SIZE(gpu2d_sel));
207 clk[gpu3d_gate] = imx_clk_gate2("gpu3d_gate", "gpu3d_sel", MXC_CCM_CCGR5, 2);
208 clk[garb_gate] = imx_clk_gate2("garb_gate", "axi_a", MXC_CCM_CCGR5, 4);
209 clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "gpu2d_sel", MXC_CCM_CCGR6, 14);
b8d4176f
SH		 210 clk[vpu_s] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel));
211 clk[vpu_gate] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6);
212 clk[vpu_reference_gate] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8);
213 clk[uart4_ipg_gate] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8);
214 clk[uart4_per_gate] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10);
215 clk[uart5_ipg_gate] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12);
216 clk[uart5_per_gate] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
217 clk[gpc_dvfs] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24);
218
13b3a07a
SG		 219 clk[ssi_apm] = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels));
220 clk[ssi1_root_sel] = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1, 14, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
221 clk[ssi2_root_sel] = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1, 12, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
222 clk[ssi3_root_sel] = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sels, ARRAY_SIZE(ssi3_clk_sels));
223 clk[ssi_ext1_sel] = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1, 28, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
224 clk[ssi_ext2_sel] = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1, 30, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
225 clk[ssi_ext1_com_sel] = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1, 0, 1, ssi_ext1_com_sels, ARRAY_SIZE(ssi_ext1_com_sels));
226 clk[ssi_ext2_com_sel] = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1, 1, 1, ssi_ext2_com_sels, ARRAY_SIZE(ssi_ext2_com_sels));
227 clk[ssi1_root_pred] = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR, 6, 3);
228 clk[ssi1_root_podf] = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR, 0, 6);
229 clk[ssi2_root_pred] = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR, 6, 3);
230 clk[ssi2_root_podf] = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR, 0, 6);
231 clk[ssi_ext1_pred] = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR, 22, 3);
232 clk[ssi_ext1_podf] = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR, 16, 6);
233 clk[ssi_ext2_pred] = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR, 22, 3);
234 clk[ssi_ext2_podf] = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR, 16, 6);
235 clk[ssi1_root_gate] = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3, 18);
236 clk[ssi2_root_gate] = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3, 22);
237 clk[ssi3_root_gate] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26);
238 clk[ssi_ext1_gate] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28);
239 clk[ssi_ext2_gate] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30);
d1e9e0ea
AS		 240 clk[epit1_ipg_gate] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2);
241 clk[epit1_hf_gate] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4);
242 clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
243 clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
f1550a1c 244 clk[owire_gate] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
13b3a07a 245
b8d4176f
SH		 246 for (i = 0; i < ARRAY_SIZE(clk); i++)
247 if (IS_ERR(clk[i]))
248 pr_err("i.MX5 clk %d: register failed with %ld\n",
249 i, PTR_ERR(clk[i]));
f1550a1c 250
0f3557c3 251 clk_register_clkdev(clk[gpt_hf_gate], "per", "imx-gpt.0");
b8d4176f
SH		 252 clk_register_clkdev(clk[gpt_ipg_gate], "ipg", "imx-gpt.0");
253 clk_register_clkdev(clk[uart1_per_gate], "per", "imx21-uart.0");
254 clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
255 clk_register_clkdev(clk[uart2_per_gate], "per", "imx21-uart.1");
256 clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
257 clk_register_clkdev(clk[uart3_per_gate], "per", "imx21-uart.2");
258 clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
259 clk_register_clkdev(clk[uart4_per_gate], "per", "imx21-uart.3");
260 clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
261 clk_register_clkdev(clk[uart5_per_gate], "per", "imx21-uart.4");
262 clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4");
263 clk_register_clkdev(clk[ecspi1_per_gate], "per", "imx51-ecspi.0");
264 clk_register_clkdev(clk[ecspi1_ipg_gate], "ipg", "imx51-ecspi.0");
265 clk_register_clkdev(clk[ecspi2_per_gate], "per", "imx51-ecspi.1");
266 clk_register_clkdev(clk[ecspi2_ipg_gate], "ipg", "imx51-ecspi.1");
e0c29dce 267 clk_register_clkdev(clk[cspi_ipg_gate], NULL, "imx35-cspi.2");
b8d4176f
SH		 268 clk_register_clkdev(clk[pwm1_ipg_gate], "pwm", "mxc_pwm.0");
269 clk_register_clkdev(clk[pwm2_ipg_gate], "pwm", "mxc_pwm.1");
5bdfba29
SG		 270 clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0");
271 clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1");
b8d4176f
SH		 272 clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.0");
273 clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.0");
274 clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.0");
275 clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.1");
276 clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.1");
277 clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.1");
278 clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.2");
279 clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.2");
280 clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.2");
61c4b560
PC		 281 clk_register_clkdev(clk[usboh3_per_gate], "per", "imx-udc-mx51");
282 clk_register_clkdev(clk[usboh3_gate], "ipg", "imx-udc-mx51");
283 clk_register_clkdev(clk[usboh3_gate], "ahb", "imx-udc-mx51");
4d62435f 284 clk_register_clkdev(clk[nfc_gate], NULL, "imx51-nand");
b8d4176f
SH		 285 clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
286 clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
287 clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2");
13b3a07a
SG		 288 clk_register_clkdev(clk[ssi_ext1_gate], "ssi_ext1", NULL);
289 clk_register_clkdev(clk[ssi_ext2_gate], "ssi_ext2", NULL);
b8d4176f
SH		 290 clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
291 clk_register_clkdev(clk[cpu_podf], "cpu", NULL);
292 clk_register_clkdev(clk[iim_gate], "iim", NULL);
293 clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.0");
294 clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.1");
295 clk_register_clkdev(clk[dummy], NULL, "imx-keypad");
296 clk_register_clkdev(clk[tve_gate], NULL, "imx-tve.0");
297 clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx-tve.0");
aa96a18d 298 clk_register_clkdev(clk[gpc_dvfs], "gpc_dvfs", NULL);
d1e9e0ea
AS		 299 clk_register_clkdev(clk[epit1_ipg_gate], "ipg", "imx-epit.0");
300 clk_register_clkdev(clk[epit1_hf_gate], "per", "imx-epit.0");
301 clk_register_clkdev(clk[epit2_ipg_gate], "ipg", "imx-epit.1");
302 clk_register_clkdev(clk[epit2_hf_gate], "per", "imx-epit.1");
b8d4176f
SH		 303
304 /* Set SDHC parents to be PLL2 */
305 clk_set_parent(clk[esdhc_a_sel], clk[pll2_sw]);
306 clk_set_parent(clk[esdhc_b_sel], clk[pll2_sw]);
307
308 /* move usb phy clk to 24MHz */
309 clk_set_parent(clk[usb_phy_sel], clk[osc]);
310
311 clk_prepare_enable(clk[gpc_dvfs]);
312 clk_prepare_enable(clk[ahb_max]); /* esdhc3 */
313 clk_prepare_enable(clk[aips_tz1]);
314 clk_prepare_enable(clk[aips_tz2]); /* fec */
315 clk_prepare_enable(clk[spba]);
316 clk_prepare_enable(clk[emi_fast_gate]); /* fec */
68b0562d 317 clk_prepare_enable(clk[emi_slow_gate]); /* eim */
9a2d4825
SH		 318 clk_prepare_enable(clk[mipi_hsc1_gate]);
319 clk_prepare_enable(clk[mipi_hsc2_gate]);
320 clk_prepare_enable(clk[mipi_esc_gate]);
321 clk_prepare_enable(clk[mipi_hsp_gate]);
b8d4176f
SH		 322 clk_prepare_enable(clk[tmax1]);
323 clk_prepare_enable(clk[tmax2]); /* esdhc2, fec */
324 clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */
325}
326
327int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
328 unsigned long rate_ckih1, unsigned long rate_ckih2)
329{
330 int i;
69155fd6 331 u32 val;
f40f38d1 332 struct device_node *np;
b8d4176f
SH		 333
334 clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
335 clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE);
336 clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX51_DPLL3_BASE);
337 clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
338 mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel));
339 clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
340 mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel));
341 clk[tve_ext_sel] = imx_clk_mux("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
342 mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel));
343 clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30);
344 clk[tve_pred] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3);
345 clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
346 clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6);
347 clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10);
348 clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
349 clk[usb_phy_gate] = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0);
350 clk[hsi2c_gate] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22);
351 clk[mipi_hsc1_gate] = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6);
352 clk[mipi_hsc2_gate] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8);
353 clk[mipi_esc_gate] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10);
354 clk[mipi_hsp_gate] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12);
355
356 for (i = 0; i < ARRAY_SIZE(clk); i++)
357 if (IS_ERR(clk[i]))
358 pr_err("i.MX51 clk %d: register failed with %ld\n",
359 i, PTR_ERR(clk[i]));
360
f40f38d1
FE		 361 np = of_find_compatible_node(NULL, NULL, "fsl,imx51-ccm");
362 clk_data.clks = clk;
363 clk_data.clk_num = ARRAY_SIZE(clk);
364 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
365
b8d4176f
SH		 366 mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
367
5bdfba29 368 clk_register_clkdev(clk[hsi2c_gate], NULL, "imx21-i2c.2");
b8d4176f
SH		 369 clk_register_clkdev(clk[mx51_mipi], "mipi_hsp", NULL);
370 clk_register_clkdev(clk[vpu_gate], NULL, "imx51-vpu.0");
371 clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
9a2d4825
SH		 372 clk_register_clkdev(clk[ipu_gate], "bus", "40000000.ipu");
373 clk_register_clkdev(clk[ipu_di0_gate], "di0", "40000000.ipu");
374 clk_register_clkdev(clk[ipu_di1_gate], "di1", "40000000.ipu");
b8d4176f
SH		 375 clk_register_clkdev(clk[usb_phy_gate], "phy", "mxc-ehci.0");
376 clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx51.0");
377 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.0");
378 clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx51.0");
379 clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx51.1");
380 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.1");
381 clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx51.1");
382 clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx51.2");
383 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.2");
384 clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx51.2");
385 clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx51.3");
386 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.3");
387 clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx51.3");
388
389 /* set the usboh3 parent to pll2_sw */
390 clk_set_parent(clk[usboh3_sel], clk[pll2_sw]);
391
392 /* set SDHC root clock to 166.25MHZ*/
393 clk_set_rate(clk[esdhc_a_podf], 166250000);
394 clk_set_rate(clk[esdhc_b_podf], 166250000);
395
396 /* System timer */
2cfb4518 397 mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT);
b8d4176f
SH		 398
399 clk_prepare_enable(clk[iim_gate]);
400 imx_print_silicon_rev("i.MX51", mx51_revision());
401 clk_disable_unprepare(clk[iim_gate]);
69155fd6
SH		 402
403 /*
404 * Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no
405 * longer supported. Set to one for better power saving.
406 *
407 * The effect of not setting these bits is that MIPI clocks can't be
408 * enabled without the IPU clock being enabled aswell.
409 */
410 val = readl(MXC_CCM_CCDR);
411 val |= 1 << 18;
412 writel(val, MXC_CCM_CCDR);
413
414 val = readl(MXC_CCM_CLPCR);
415 val |= 1 << 23;
416 writel(val, MXC_CCM_CLPCR);
b8d4176f
SH		 417
418 return 0;
419}
420
421int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
422 unsigned long rate_ckih1, unsigned long rate_ckih2)
423{
424 int i;
425 unsigned long r;
f40f38d1 426 struct device_node *np;
b8d4176f
SH		 427
428 clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
429 clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
430 clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
431 clk[pll4_sw] = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE);
432
b8d4176f 433 clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
cc7b6339
PZ		 434 clk[ldb_di1_div] = imx_clk_divider_flags("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1, 0);
435 clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1,
436 mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel), CLK_SET_RATE_PARENT);
b8d4176f 437 clk[di_pll4_podf] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3);
b8d4176f 438 clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
cc7b6339
PZ		 439 clk[ldb_di0_div] = imx_clk_divider_flags("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1, 0);
440 clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1,
441 mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT);
b8d4176f
SH		 442 clk[ldb_di0_gate] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28);
443 clk[ldb_di1_gate] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30);
444 clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
445 mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel));
446 clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
447 mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel));
448 clk[tve_ext_sel] = imx_clk_mux("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
449 mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel));
450 clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30);
451 clk[tve_pred] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3);
452 clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
453 clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
454 clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
455 clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
456 clk[usb_phy1_gate] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
457 clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
a745f039
SH		 458 clk[can_sel] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2,
459 mx53_can_sel, ARRAY_SIZE(mx53_can_sel));
460 clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22);
461 clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20);
462 clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
463 clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
b8d4176f
SH		 464 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
465
466 for (i = 0; i < ARRAY_SIZE(clk); i++)
467 if (IS_ERR(clk[i]))
468 pr_err("i.MX53 clk %d: register failed with %ld\n",
469 i, PTR_ERR(clk[i]));
470
f40f38d1
FE		 471 np = of_find_compatible_node(NULL, NULL, "fsl,imx53-ccm");
472 clk_data.clks = clk;
473 clk_data.clk_num = ARRAY_SIZE(clk);
474 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
475
b8d4176f
SH		 476 mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
477
478 clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0");
5bdfba29 479 clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2");
b8d4176f 480 clk_register_clkdev(clk[fec_gate], NULL, "imx25-fec.0");
9a2d4825
SH		 481 clk_register_clkdev(clk[ipu_gate], "bus", "18000000.ipu");
482 clk_register_clkdev(clk[ipu_di0_gate], "di0", "18000000.ipu");
483 clk_register_clkdev(clk[ipu_di1_gate], "di1", "18000000.ipu");
484 clk_register_clkdev(clk[ipu_gate], "hsp", "18000000.ipu");
b8d4176f
SH		 485 clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0");
486 clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx53.0");
487 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.0");
488 clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx53.0");
489 clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx53.1");
490 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.1");
491 clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx53.1");
492 clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx53.2");
493 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.2");
494 clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx53.2");
495 clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx53.3");
496 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.3");
497 clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx53.3");
498
499 /* set SDHC root clock to 200MHZ*/
500 clk_set_rate(clk[esdhc_a_podf], 200000000);
501 clk_set_rate(clk[esdhc_b_podf], 200000000);
502
503 /* System timer */
2cfb4518 504 mxc_timer_init(MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), MX53_INT_GPT);
b8d4176f
SH		 505
506 clk_prepare_enable(clk[iim_gate]);
507 imx_print_silicon_rev("i.MX53", mx53_revision());
508 clk_disable_unprepare(clk[iim_gate]);
509
510 r = clk_round_rate(clk[usboh3_per_gate], 54000000);
511 clk_set_rate(clk[usboh3_per_gate], r);
512
513 return 0;
514}
515
516#ifdef CONFIG_OF
517static void __init clk_get_freq_dt(unsigned long *ckil, unsigned long *osc,
518 unsigned long *ckih1, unsigned long *ckih2)
519{
520 struct device_node *np;
521
522 /* retrieve the freqency of fixed clocks from device tree */
523 for_each_compatible_node(np, NULL, "fixed-clock") {
524 u32 rate;
525 if (of_property_read_u32(np, "clock-frequency", &rate))
526 continue;
527
528 if (of_device_is_compatible(np, "fsl,imx-ckil"))
529 *ckil = rate;
530 else if (of_device_is_compatible(np, "fsl,imx-osc"))
531 *osc = rate;
532 else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
533 *ckih1 = rate;
534 else if (of_device_is_compatible(np, "fsl,imx-ckih2"))
535 *ckih2 = rate;
536 }
537}
538
539int __init mx51_clocks_init_dt(void)
540{
541 unsigned long ckil, osc, ckih1, ckih2;
542
543 clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
544 return mx51_clocks_init(ckil, osc, ckih1, ckih2);
545}
546
547int __init mx53_clocks_init_dt(void)
548{
549 unsigned long ckil, osc, ckih1, ckih2;
550
551 clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
552 return mx53_clocks_init(ckil, osc, ckih1, ckih2);
553}
554#endif
Linux kernel - Deliverables
This page took 0.083389 seconds and 5 git commands to generate.