projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ARM: imx_v6_v7_defconfig: Select CONFIG_HIGHMEM
[deliverable/linux.git] / arch / arm / mach-imx / clk-imx51-imx53.c
CommitLineData
b8d4176f
SH		 1/*
2 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9#include <linux/mm.h>
10#include <linux/delay.h>
11#include <linux/clk.h>
12#include <linux/io.h>
13#include <linux/clkdev.h>
4d9d18a5 14#include <linux/clk-provider.h>
b8d4176f 15#include <linux/err.h>
bfcc7bce
FE		 16#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/of_irq.h>
b8d4176f 19
b8d4176f
SH		 20#include "crm-regs-imx5.h"
21#include "clk.h"
e3372474 22#include "common.h"
50f2de61 23#include "hardware.h"
b8d4176f
SH		 24
25/* Low-power Audio Playback Mode clock */
26static const char *lp_apm_sel[] = { "osc", };
27
28/* This is used multiple times */
29static const char *standard_pll_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "lp_apm", };
30static const char *periph_apm_sel[] = { "pll1_sw", "pll3_sw", "lp_apm", };
31static const char *main_bus_sel[] = { "pll2_sw", "periph_apm", };
32static const char *per_lp_apm_sel[] = { "main_bus", "lp_apm", };
33static const char *per_root_sel[] = { "per_podf", "ipg", };
34static const char *esdhc_c_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
35static const char *esdhc_d_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
13b3a07a
SG		 36static const char *ssi_apm_sels[] = { "ckih1", "lp_amp", "ckih2", };
37static const char *ssi_clk_sels[] = { "pll1_sw", "pll2_sw", "pll3_sw", "ssi_apm", };
38static const char *ssi3_clk_sels[] = { "ssi1_root_gate", "ssi2_root_gate", };
39static const char *ssi_ext1_com_sels[] = { "ssi_ext1_podf", "ssi1_root_gate", };
40static const char *ssi_ext2_com_sels[] = { "ssi_ext2_podf", "ssi2_root_gate", };
b8d4176f
SH		 41static const char *emi_slow_sel[] = { "main_bus", "ahb", };
42static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", };
43static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", };
51f66191 44static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0_gate", };
b8d4176f
SH		 45static const char *mx53_ldb_di0_sel[] = { "pll3_sw", "pll4_sw", };
46static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", };
51f66191 47static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1_gate", };
b8d4176f
SH		 48static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", };
49static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", };
50static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", };
3f487bed 51static const char *mx51_tve_sel[] = { "tve_pred", "tve_ext_sel", };
b8d4176f 52static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
8ecb167f
PZ		 53static const char *gpu3d_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" };
54static const char *gpu2d_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" };
b8d4176f 55static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
a745f039 56static const char *mx53_can_sel[] = { "ipg", "ckih1", "ckih2", "lp_apm", };
04b41e84
MF		 57static const char *mx53_cko1_sel[] = {
58 "cpu_podf", "pll1_sw", "pll2_sw", "pll3_sw",
59 "emi_slow_podf", "pll4_sw", "nfc_podf", "dummy",
60 "di_pred", "dummy", "dummy", "ahb",
61 "ipg", "per_root", "ckil", "dummy",};
62static const char *mx53_cko2_sel[] = {
63 "dummy"/* dptc_core */, "dummy"/* dptc_perich */,
64 "dummy", "esdhc_a_podf",
65 "usboh3_podf", "dummy"/* wrck_clk_root */,
66 "ecspi_podf", "dummy"/* pll1_ref_clk */,
67 "esdhc_b_podf", "dummy"/* ddr_clk_root */,
68 "dummy"/* arm_axi_clk_root */, "dummy"/* usb_phy_out */,
69 "vpu_sel", "ipu_sel",
70 "osc", "ckih1",
71 "dummy", "esdhc_c_sel",
72 "ssi1_root_podf", "ssi2_root_podf",
73 "dummy", "dummy",
74 "dummy"/* lpsr_clk_root */, "dummy"/* pgc_clk_root */,
75 "dummy"/* tve_out */, "usb_phy_sel",
76 "tve_sel", "lp_apm",
77 "uart_root", "dummy"/* spdif0_clk_root */,
78 "dummy", "dummy", };
beb2d1c1
PZ		 79static const char *mx51_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", };
80static const char *mx53_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", "pll4_sw", };
81static const char *spdif_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_sel", };
82static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", };
83static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", };
84
b8d4176f
SH		 85
86enum imx5_clks {
87 dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred,
88 uart_root, esdhc_a_pred, esdhc_b_pred, esdhc_c_s, esdhc_d_s,
89 emi_sel, emi_slow_podf, nfc_podf, ecspi_pred, ecspi_podf, usboh3_pred,
d24de495 90 usboh3_podf, usb_phy_pred, usb_phy_podf, cpu_podf, di_pred, tve_di_unused,
b8d4176f
SH		 91 tve_s, uart1_ipg_gate, uart1_per_gate, uart2_ipg_gate,
92 uart2_per_gate, uart3_ipg_gate, uart3_per_gate, i2c1_gate, i2c2_gate,
93 gpt_ipg_gate, pwm1_ipg_gate, pwm1_hf_gate, pwm2_ipg_gate, pwm2_hf_gate,
0f3557c3 94 gpt_hf_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate,
b8d4176f
SH		 95 esdhc3_ipg_gate, esdhc4_ipg_gate, ssi1_ipg_gate, ssi2_ipg_gate,
96 ssi3_ipg_gate, ecspi1_ipg_gate, ecspi1_per_gate, ecspi2_ipg_gate,
97 ecspi2_per_gate, cspi_ipg_gate, sdma_gate, emi_slow_gate, ipu_s,
98 ipu_gate, nfc_gate, ipu_di1_gate, vpu_s, vpu_gate,
99 vpu_reference_gate, uart4_ipg_gate, uart4_per_gate, uart5_ipg_gate,
100 uart5_per_gate, tve_gate, tve_pred, esdhc1_per_gate, esdhc2_per_gate,
101 esdhc3_per_gate, esdhc4_per_gate, usb_phy_gate, hsi2c_gate,
102 mipi_hsc1_gate, mipi_hsc2_gate, mipi_esc_gate, mipi_hsp_gate,
103 ldb_di1_div_3_5, ldb_di1_div, ldb_di0_div_3_5, ldb_di0_div,
104 ldb_di1_gate, can2_serial_gate, can2_ipg_gate, i2c3_gate, lp_apm,
105 periph_apm, main_bus, ahb_max, aips_tz1, aips_tz2, tmax1, tmax2,
106 tmax3, spba, uart_sel, esdhc_a_sel, esdhc_b_sel, esdhc_a_podf,
107 esdhc_b_podf, ecspi_sel, usboh3_sel, usb_phy_sel, iim_gate,
108 usboh3_gate, emi_fast_gate, ipu_di0_gate,gpc_dvfs, pll1_sw, pll2_sw,
109 pll3_sw, ipu_di0_sel, ipu_di1_sel, tve_ext_sel, mx51_mipi, pll4_sw,
110 ldb_di1_sel, di_pll4_podf, ldb_di0_sel, ldb_di0_gate, usb_phy1_gate,
111 usb_phy2_gate, per_lp_apm, per_pred1, per_pred2, per_podf, per_root,
13b3a07a
SG		 112 ssi_apm, ssi1_root_sel, ssi2_root_sel, ssi3_root_sel, ssi_ext1_sel,
113 ssi_ext2_sel, ssi_ext1_com_sel, ssi_ext2_com_sel, ssi1_root_pred,
114 ssi1_root_podf, ssi2_root_pred, ssi2_root_podf, ssi_ext1_pred,
115 ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate,
116 ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate,
d1e9e0ea 117 epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate,
a745f039 118 can_sel, can1_serial_gate, can1_ipg_gate,
8ecb167f 119 owire_gate, gpu3d_s, gpu2d_s, gpu3d_gate, gpu2d_gate, garb_gate,
04b41e84
MF		 120 cko1_sel, cko1_podf, cko1,
121 cko2_sel, cko2_podf, cko2,
beb2d1c1
PZ		 122 srtc_gate, pata_gate, sata_gate, spdif_xtal_sel, spdif0_sel,
123 spdif1_sel, spdif0_pred, spdif0_podf, spdif1_pred, spdif1_podf,
124 spdif0_com_s, spdif1_com_sel, spdif0_gate, spdif1_gate, spdif_ipg_gate,
9b015e5a 125 ocram, sahara_ipg_gate, clk_max
b8d4176f
SH		 126};
127
128static struct clk *clk[clk_max];
f40f38d1 129static struct clk_onecell_data clk_data;
b8d4176f
SH		 130
131static void __init mx5_clocks_common_init(unsigned long rate_ckil,
132 unsigned long rate_osc, unsigned long rate_ckih1,
133 unsigned long rate_ckih2)
134{
135 int i;
136
137 clk[dummy] = imx_clk_fixed("dummy", 0);
75f83d06
MF		 138 clk[ckil] = imx_obtain_fixed_clock("ckil", rate_ckil);
139 clk[osc] = imx_obtain_fixed_clock("osc", rate_osc);
140 clk[ckih1] = imx_obtain_fixed_clock("ckih1", rate_ckih1);
141 clk[ckih2] = imx_obtain_fixed_clock("ckih2", rate_ckih2);
b8d4176f
SH		 142
143 clk[lp_apm] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
144 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
145 clk[periph_apm] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
146 periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
147 clk[main_bus] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
148 main_bus_sel, ARRAY_SIZE(main_bus_sel));
c040be00 149 clk[per_lp_apm] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1,
b8d4176f
SH		 150 per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
151 clk[per_pred1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2);
152 clk[per_pred2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3);
153 clk[per_podf] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3);
c040be00 154 clk[per_root] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1,
b8d4176f
SH		 155 per_root_sel, ARRAY_SIZE(per_root_sel));
156 clk[ahb] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3);
157 clk[ahb_max] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28);
158 clk[aips_tz1] = imx_clk_gate2("aips_tz1", "ahb", MXC_CCM_CCGR0, 24);
159 clk[aips_tz2] = imx_clk_gate2("aips_tz2", "ahb", MXC_CCM_CCGR0, 26);
160 clk[tmax1] = imx_clk_gate2("tmax1", "ahb", MXC_CCM_CCGR1, 0);
161 clk[tmax2] = imx_clk_gate2("tmax2", "ahb", MXC_CCM_CCGR1, 2);
162 clk[tmax3] = imx_clk_gate2("tmax3", "ahb", MXC_CCM_CCGR1, 4);
163 clk[spba] = imx_clk_gate2("spba", "ipg", MXC_CCM_CCGR5, 0);
164 clk[ipg] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2);
165 clk[axi_a] = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3);
166 clk[axi_b] = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3);
167 clk[uart_sel] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2,
168 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
169 clk[uart_pred] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3);
170 clk[uart_root] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3);
171
172 clk[esdhc_a_sel] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,
173 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
174 clk[esdhc_b_sel] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
175 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
176 clk[esdhc_a_pred] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3);
177 clk[esdhc_a_podf] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3);
178 clk[esdhc_b_pred] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3);
179 clk[esdhc_b_podf] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3);
180 clk[esdhc_c_s] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
181 clk[esdhc_d_s] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
182
183 clk[emi_sel] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1,
184 emi_slow_sel, ARRAY_SIZE(emi_slow_sel));
185 clk[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3);
186 clk[nfc_podf] = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3);
187 clk[ecspi_sel] = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2,
188 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
189 clk[ecspi_pred] = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3);
190 clk[ecspi_podf] = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6);
191 clk[usboh3_sel] = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2,
192 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
193 clk[usboh3_pred] = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3);
194 clk[usboh3_podf] = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2);
195 clk[usb_phy_pred] = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3);
196 clk[usb_phy_podf] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3);
197 clk[usb_phy_sel] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1,
198 usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
199 clk[cpu_podf] = imx_clk_divider("cpu_podf", "pll1_sw", MXC_CCM_CACRR, 0, 3);
200 clk[di_pred] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3);
b8d4176f
SH		 201 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30);
202 clk[uart1_ipg_gate] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6);
203 clk[uart1_per_gate] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8);
204 clk[uart2_ipg_gate] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10);
205 clk[uart2_per_gate] = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12);
206 clk[uart3_ipg_gate] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14);
207 clk[uart3_per_gate] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16);
208 clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18);
209 clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20);
b8d4176f 210 clk[pwm1_ipg_gate] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10);
796b72cc 211 clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12);
b8d4176f 212 clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14);
796b72cc 213 clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16);
0f3557c3
AS		 214 clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18);
215 clk[gpt_hf_gate] = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20);
b8d4176f
SH		 216 clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24);
217 clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26);
218 clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28);
219 clk[esdhc1_ipg_gate] = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0);
220 clk[esdhc2_ipg_gate] = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4);
221 clk[esdhc3_ipg_gate] = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8);
222 clk[esdhc4_ipg_gate] = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12);
223 clk[ssi1_ipg_gate] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16);
224 clk[ssi2_ipg_gate] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20);
225 clk[ssi3_ipg_gate] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24);
226 clk[ecspi1_ipg_gate] = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18);
227 clk[ecspi1_per_gate] = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20);
228 clk[ecspi2_ipg_gate] = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22);
229 clk[ecspi2_per_gate] = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24);
230 clk[cspi_ipg_gate] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26);
231 clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30);
232 clk[emi_fast_gate] = imx_clk_gate2("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14);
233 clk[emi_slow_gate] = imx_clk_gate2("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16);
234 clk[ipu_s] = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel));
235 clk[ipu_gate] = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10);
236 clk[nfc_gate] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20);
237 clk[ipu_di0_gate] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10);
238 clk[ipu_di1_gate] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12);
8ecb167f
PZ		 239 clk[gpu3d_s] = imx_clk_mux("gpu3d_sel", MXC_CCM_CBCMR, 4, 2, gpu3d_sel, ARRAY_SIZE(gpu3d_sel));
240 clk[gpu2d_s] = imx_clk_mux("gpu2d_sel", MXC_CCM_CBCMR, 16, 2, gpu2d_sel, ARRAY_SIZE(gpu2d_sel));
241 clk[gpu3d_gate] = imx_clk_gate2("gpu3d_gate", "gpu3d_sel", MXC_CCM_CCGR5, 2);
242 clk[garb_gate] = imx_clk_gate2("garb_gate", "axi_a", MXC_CCM_CCGR5, 4);
243 clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "gpu2d_sel", MXC_CCM_CCGR6, 14);
b8d4176f
SH		 244 clk[vpu_s] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel));
245 clk[vpu_gate] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6);
246 clk[vpu_reference_gate] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8);
247 clk[uart4_ipg_gate] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8);
248 clk[uart4_per_gate] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10);
249 clk[uart5_ipg_gate] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12);
250 clk[uart5_per_gate] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
251 clk[gpc_dvfs] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24);
252
13b3a07a
SG		 253 clk[ssi_apm] = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels));
254 clk[ssi1_root_sel] = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1, 14, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
255 clk[ssi2_root_sel] = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1, 12, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
256 clk[ssi3_root_sel] = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sels, ARRAY_SIZE(ssi3_clk_sels));
257 clk[ssi_ext1_sel] = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1, 28, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
258 clk[ssi_ext2_sel] = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1, 30, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
259 clk[ssi_ext1_com_sel] = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1, 0, 1, ssi_ext1_com_sels, ARRAY_SIZE(ssi_ext1_com_sels));
260 clk[ssi_ext2_com_sel] = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1, 1, 1, ssi_ext2_com_sels, ARRAY_SIZE(ssi_ext2_com_sels));
261 clk[ssi1_root_pred] = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR, 6, 3);
262 clk[ssi1_root_podf] = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR, 0, 6);
263 clk[ssi2_root_pred] = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR, 6, 3);
264 clk[ssi2_root_podf] = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR, 0, 6);
265 clk[ssi_ext1_pred] = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR, 22, 3);
266 clk[ssi_ext1_podf] = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR, 16, 6);
267 clk[ssi_ext2_pred] = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR, 22, 3);
268 clk[ssi_ext2_podf] = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR, 16, 6);
269 clk[ssi1_root_gate] = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3, 18);
270 clk[ssi2_root_gate] = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3, 22);
271 clk[ssi3_root_gate] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26);
272 clk[ssi_ext1_gate] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28);
273 clk[ssi_ext2_gate] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30);
d1e9e0ea
AS		 274 clk[epit1_ipg_gate] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2);
275 clk[epit1_hf_gate] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4);
276 clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
277 clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
f1550a1c 278 clk[owire_gate] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
5d530bb0
SH		 279 clk[srtc_gate] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28);
280 clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0);
beb2d1c1
PZ		 281 clk[spdif0_sel] = imx_clk_mux("spdif0_sel", MXC_CCM_CSCMR2, 0, 2, spdif_sel, ARRAY_SIZE(spdif_sel));
282 clk[spdif0_pred] = imx_clk_divider("spdif0_pred", "spdif0_sel", MXC_CCM_CDCDR, 25, 3);
283 clk[spdif0_podf] = imx_clk_divider("spdif0_podf", "spdif0_pred", MXC_CCM_CDCDR, 19, 6);
284 clk[spdif0_com_s] = imx_clk_mux_flags("spdif0_com_sel", MXC_CCM_CSCMR2, 4, 1,
285 spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT);
286 clk[spdif0_gate] = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26);
287 clk[spdif_ipg_gate] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30);
9b015e5a 288 clk[sahara_ipg_gate] = imx_clk_gate2("sahara_ipg_gate", "ipg", MXC_CCM_CCGR4, 14);
13b3a07a 289
b8d4176f
SH		 290 for (i = 0; i < ARRAY_SIZE(clk); i++)
291 if (IS_ERR(clk[i]))
292 pr_err("i.MX5 clk %d: register failed with %ld\n",
293 i, PTR_ERR(clk[i]));
f1550a1c 294
0f3557c3 295 clk_register_clkdev(clk[gpt_hf_gate], "per", "imx-gpt.0");
b8d4176f
SH		 296 clk_register_clkdev(clk[gpt_ipg_gate], "ipg", "imx-gpt.0");
297 clk_register_clkdev(clk[uart1_per_gate], "per", "imx21-uart.0");
298 clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
299 clk_register_clkdev(clk[uart2_per_gate], "per", "imx21-uart.1");
300 clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
301 clk_register_clkdev(clk[uart3_per_gate], "per", "imx21-uart.2");
302 clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
303 clk_register_clkdev(clk[uart4_per_gate], "per", "imx21-uart.3");
304 clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
305 clk_register_clkdev(clk[uart5_per_gate], "per", "imx21-uart.4");
306 clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4");
307 clk_register_clkdev(clk[ecspi1_per_gate], "per", "imx51-ecspi.0");
308 clk_register_clkdev(clk[ecspi1_ipg_gate], "ipg", "imx51-ecspi.0");
309 clk_register_clkdev(clk[ecspi2_per_gate], "per", "imx51-ecspi.1");
310 clk_register_clkdev(clk[ecspi2_ipg_gate], "ipg", "imx51-ecspi.1");
e0c29dce 311 clk_register_clkdev(clk[cspi_ipg_gate], NULL, "imx35-cspi.2");
b8d4176f
SH		 312 clk_register_clkdev(clk[pwm1_ipg_gate], "pwm", "mxc_pwm.0");
313 clk_register_clkdev(clk[pwm2_ipg_gate], "pwm", "mxc_pwm.1");
5bdfba29
SG		 314 clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0");
315 clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1");
b8d4176f
SH		 316 clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.0");
317 clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.0");
318 clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.0");
319 clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.1");
320 clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.1");
321 clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.1");
322 clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.2");
323 clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.2");
324 clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.2");
61c4b560
PC		 325 clk_register_clkdev(clk[usboh3_per_gate], "per", "imx-udc-mx51");
326 clk_register_clkdev(clk[usboh3_gate], "ipg", "imx-udc-mx51");
327 clk_register_clkdev(clk[usboh3_gate], "ahb", "imx-udc-mx51");
4d62435f 328 clk_register_clkdev(clk[nfc_gate], NULL, "imx51-nand");
b8d4176f
SH		 329 clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
330 clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
331 clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2");
332 clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
3d10a887 333 clk_register_clkdev(clk[cpu_podf], NULL, "cpu0");
b8d4176f
SH		 334 clk_register_clkdev(clk[iim_gate], "iim", NULL);
335 clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.0");
336 clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.1");
337 clk_register_clkdev(clk[dummy], NULL, "imx-keypad");
b8d4176f 338 clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx-tve.0");
aa96a18d 339 clk_register_clkdev(clk[gpc_dvfs], "gpc_dvfs", NULL);
d1e9e0ea
AS		 340 clk_register_clkdev(clk[epit1_ipg_gate], "ipg", "imx-epit.0");
341 clk_register_clkdev(clk[epit1_hf_gate], "per", "imx-epit.0");
342 clk_register_clkdev(clk[epit2_ipg_gate], "ipg", "imx-epit.1");
343 clk_register_clkdev(clk[epit2_hf_gate], "per", "imx-epit.1");
b8d4176f
SH		 344
345 /* Set SDHC parents to be PLL2 */
346 clk_set_parent(clk[esdhc_a_sel], clk[pll2_sw]);
347 clk_set_parent(clk[esdhc_b_sel], clk[pll2_sw]);
348
349 /* move usb phy clk to 24MHz */
350 clk_set_parent(clk[usb_phy_sel], clk[osc]);
351
352 clk_prepare_enable(clk[gpc_dvfs]);
353 clk_prepare_enable(clk[ahb_max]); /* esdhc3 */
354 clk_prepare_enable(clk[aips_tz1]);
355 clk_prepare_enable(clk[aips_tz2]); /* fec */
356 clk_prepare_enable(clk[spba]);
357 clk_prepare_enable(clk[emi_fast_gate]); /* fec */
68b0562d 358 clk_prepare_enable(clk[emi_slow_gate]); /* eim */
9a2d4825
SH		 359 clk_prepare_enable(clk[mipi_hsc1_gate]);
360 clk_prepare_enable(clk[mipi_hsc2_gate]);
361 clk_prepare_enable(clk[mipi_esc_gate]);
362 clk_prepare_enable(clk[mipi_hsp_gate]);
b8d4176f
SH		 363 clk_prepare_enable(clk[tmax1]);
364 clk_prepare_enable(clk[tmax2]); /* esdhc2, fec */
365 clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */
366}
367
7a9cc1ad
GU		 368static void __init mx50_clocks_init(struct device_node *np)
369{
370 void __iomem *base;
371 unsigned long r;
372 int i, irq;
373
374 clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
375 clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
376 clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
377
378 clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
379 clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
380 clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
381 clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
382 clk[usb_phy1_gate] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
383 clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
384 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
385
386 clk[cko1_sel] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
387 mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
388 clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3);
389 clk[cko1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7);
390
391 clk[cko2_sel] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5,
392 mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
393 clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
394 clk[cko2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
395
396 for (i = 0; i < ARRAY_SIZE(clk); i++)
397 if (IS_ERR(clk[i]))
398 pr_err("i.MX50 clk %d: register failed with %ld\n",
399 i, PTR_ERR(clk[i]));
400
401 clk_data.clks = clk;
402 clk_data.clk_num = ARRAY_SIZE(clk);
403 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
404
405 mx5_clocks_common_init(0, 0, 0, 0);
406
407 /* set SDHC root clock to 200MHZ*/
408 clk_set_rate(clk[esdhc_a_podf], 200000000);
409 clk_set_rate(clk[esdhc_b_podf], 200000000);
410
411 clk_prepare_enable(clk[iim_gate]);
412 imx_print_silicon_rev("i.MX50", IMX_CHIP_REVISION_1_1);
413 clk_disable_unprepare(clk[iim_gate]);
414
415 r = clk_round_rate(clk[usboh3_per_gate], 54000000);
416 clk_set_rate(clk[usboh3_per_gate], r);
417
418 np = of_find_compatible_node(NULL, NULL, "fsl,imx50-gpt");
419 base = of_iomap(np, 0);
420 WARN_ON(!base);
421 irq = irq_of_parse_and_map(np, 0);
422 mxc_timer_init(base, irq);
423}
424CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);
425
b8d4176f
SH		 426int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
427 unsigned long rate_ckih1, unsigned long rate_ckih2)
428{
429 int i;
69155fd6 430 u32 val;
f40f38d1 431 struct device_node *np;
b8d4176f
SH		 432
433 clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
434 clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE);
435 clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX51_DPLL3_BASE);
436 clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
437 mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel));
438 clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
439 mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel));
80f72d2d
PZ		 440 clk[tve_ext_sel] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
441 mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel), CLK_SET_RATE_PARENT);
3f487bed
PZ		 442 clk[tve_s] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1,
443 mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel));
b8d4176f
SH		 444 clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30);
445 clk[tve_pred] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3);
446 clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
447 clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6);
448 clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10);
449 clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
450 clk[usb_phy_gate] = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0);
451 clk[hsi2c_gate] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22);
452 clk[mipi_hsc1_gate] = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6);
453 clk[mipi_hsc2_gate] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8);
454 clk[mipi_esc_gate] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10);
455 clk[mipi_hsp_gate] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12);
beb2d1c1
PZ		 456 clk[spdif_xtal_sel] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
457 mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel));
458 clk[spdif1_sel] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2,
459 spdif_sel, ARRAY_SIZE(spdif_sel));
5d5248a6 460 clk[spdif1_pred] = imx_clk_divider("spdif1_pred", "spdif1_sel", MXC_CCM_CDCDR, 16, 3);
beb2d1c1
PZ		 461 clk[spdif1_podf] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6);
462 clk[spdif1_com_sel] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1,
463 mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));
464 clk[spdif1_gate] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28);
b8d4176f
SH		 465
466 for (i = 0; i < ARRAY_SIZE(clk); i++)
467 if (IS_ERR(clk[i]))
468 pr_err("i.MX51 clk %d: register failed with %ld\n",
469 i, PTR_ERR(clk[i]));
470
f40f38d1
FE		 471 np = of_find_compatible_node(NULL, NULL, "fsl,imx51-ccm");
472 clk_data.clks = clk;
473 clk_data.clk_num = ARRAY_SIZE(clk);
474 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
475
b8d4176f
SH		 476 mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
477
5bdfba29 478 clk_register_clkdev(clk[hsi2c_gate], NULL, "imx21-i2c.2");
b8d4176f
SH		 479 clk_register_clkdev(clk[mx51_mipi], "mipi_hsp", NULL);
480 clk_register_clkdev(clk[vpu_gate], NULL, "imx51-vpu.0");
481 clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
b8d4176f
SH		 482 clk_register_clkdev(clk[usb_phy_gate], "phy", "mxc-ehci.0");
483 clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx51.0");
484 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.0");
485 clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx51.0");
486 clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx51.1");
487 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.1");
488 clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx51.1");
489 clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx51.2");
490 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.2");
491 clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx51.2");
492 clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx51.3");
493 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.3");
494 clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx51.3");
495
496 /* set the usboh3 parent to pll2_sw */
497 clk_set_parent(clk[usboh3_sel], clk[pll2_sw]);
498
499 /* set SDHC root clock to 166.25MHZ*/
500 clk_set_rate(clk[esdhc_a_podf], 166250000);
501 clk_set_rate(clk[esdhc_b_podf], 166250000);
502
503 /* System timer */
2cfb4518 504 mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT);
b8d4176f
SH		 505
506 clk_prepare_enable(clk[iim_gate]);
507 imx_print_silicon_rev("i.MX51", mx51_revision());
508 clk_disable_unprepare(clk[iim_gate]);
69155fd6
SH		 509
510 /*
511 * Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no
512 * longer supported. Set to one for better power saving.
513 *
514 * The effect of not setting these bits is that MIPI clocks can't be
515 * enabled without the IPU clock being enabled aswell.
516 */
517 val = readl(MXC_CCM_CCDR);
518 val |= 1 << 18;
519 writel(val, MXC_CCM_CCDR);
520
521 val = readl(MXC_CCM_CLPCR);
522 val |= 1 << 23;
523 writel(val, MXC_CCM_CLPCR);
b8d4176f
SH		 524
525 return 0;
526}
527
4d9d18a5
SH		 528static void __init mx51_clocks_init_dt(struct device_node *np)
529{
530 mx51_clocks_init(0, 0, 0, 0);
531}
532CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init_dt);
533
534static void __init mx53_clocks_init(struct device_node *np)
b8d4176f 535{
bfcc7bce 536 int i, irq;
b8d4176f 537 unsigned long r;
bfcc7bce 538 void __iomem *base;
b8d4176f
SH		 539
540 clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
541 clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
542 clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
543 clk[pll4_sw] = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE);
544
b8d4176f 545 clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
cc7b6339
PZ		 546 clk[ldb_di1_div] = imx_clk_divider_flags("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1, 0);
547 clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1,
548 mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel), CLK_SET_RATE_PARENT);
b8d4176f 549 clk[di_pll4_podf] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3);
b8d4176f 550 clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
cc7b6339
PZ		 551 clk[ldb_di0_div] = imx_clk_divider_flags("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1, 0);
552 clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1,
553 mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT);
b8d4176f
SH		 554 clk[ldb_di0_gate] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28);
555 clk[ldb_di1_gate] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30);
556 clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
557 mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel));
558 clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
559 mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel));
f550e701
PZ		 560 clk[tve_ext_sel] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
561 mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT);
b8d4176f
SH		 562 clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30);
563 clk[tve_pred] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3);
564 clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
565 clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
566 clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
567 clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
568 clk[usb_phy1_gate] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
569 clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
a745f039
SH		 570 clk[can_sel] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2,
571 mx53_can_sel, ARRAY_SIZE(mx53_can_sel));
572 clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22);
573 clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20);
ea257a03 574 clk[ocram] = imx_clk_gate2("ocram", "ahb", MXC_CCM_CCGR6, 2);
a745f039
SH		 575 clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
576 clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
b8d4176f 577 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
c9a74f55 578 clk[sata_gate] = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4, 2);
b8d4176f 579
04b41e84
MF		 580 clk[cko1_sel] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
581 mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
582 clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3);
583 clk[cko1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7);
584
585 clk[cko2_sel] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5,
586 mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
587 clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
588 clk[cko2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
beb2d1c1
PZ		 589 clk[spdif_xtal_sel] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
590 mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
04b41e84 591
b8d4176f
SH		 592 for (i = 0; i < ARRAY_SIZE(clk); i++)
593 if (IS_ERR(clk[i]))
594 pr_err("i.MX53 clk %d: register failed with %ld\n",
595 i, PTR_ERR(clk[i]));
596
f40f38d1
FE		 597 clk_data.clks = clk;
598 clk_data.clk_num = ARRAY_SIZE(clk);
599 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
600
4d9d18a5 601 mx5_clocks_common_init(0, 0, 0, 0);
b8d4176f
SH		 602
603 clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0");
5bdfba29 604 clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2");
b8d4176f 605 clk_register_clkdev(clk[fec_gate], NULL, "imx25-fec.0");
b8d4176f
SH		 606 clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0");
607 clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx53.0");
608 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.0");
609 clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx53.0");
610 clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx53.1");
611 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.1");
612 clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx53.1");
613 clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx53.2");
614 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.2");
615 clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx53.2");
616 clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx53.3");
617 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.3");
618 clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx53.3");
619
620 /* set SDHC root clock to 200MHZ*/
621 clk_set_rate(clk[esdhc_a_podf], 200000000);
622 clk_set_rate(clk[esdhc_b_podf], 200000000);
623
b8d4176f
SH		 624 clk_prepare_enable(clk[iim_gate]);
625 imx_print_silicon_rev("i.MX53", mx53_revision());
626 clk_disable_unprepare(clk[iim_gate]);
627
628 r = clk_round_rate(clk[usboh3_per_gate], 54000000);
629 clk_set_rate(clk[usboh3_per_gate], r);
bfcc7bce
FE		 630
631 np = of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt");
632 base = of_iomap(np, 0);
633 WARN_ON(!base);
634 irq = irq_of_parse_and_map(np, 0);
635 mxc_timer_init(base, irq);
b8d4176f 636}
4d9d18a5 637CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init);
Linux kernel - Deliverables
This page took 0.115181 seconds and 5 git commands to generate.