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45fe6810 | 1 | /* |
848db4a0 | 2 | * Copyright 2013-2014 Freescale Semiconductor, Inc. |
45fe6810 SG |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | */ | |
9 | ||
10 | #include <linux/clk.h> | |
11 | #include <linux/clkdev.h> | |
12 | #include <linux/err.h> | |
13 | #include <linux/of.h> | |
14 | #include <linux/of_address.h> | |
15 | #include <linux/of_irq.h> | |
16 | #include <dt-bindings/clock/imx6sl-clock.h> | |
17 | ||
18 | #include "clk.h" | |
19 | #include "common.h" | |
20 | ||
6e6cdf66 AH |
21 | #define CCSR 0xc |
22 | #define BM_CCSR_PLL1_SW_CLK_SEL (1 << 2) | |
23 | #define CACRR 0x10 | |
24 | #define CDHIPR 0x48 | |
25 | #define BM_CDHIPR_ARM_PODF_BUSY (1 << 16) | |
26 | #define ARM_WAIT_DIV_396M 2 | |
27 | #define ARM_WAIT_DIV_792M 4 | |
28 | #define ARM_WAIT_DIV_996M 6 | |
29 | ||
30 | #define PLL_ARM 0x0 | |
31 | #define BM_PLL_ARM_DIV_SELECT (0x7f << 0) | |
32 | #define BM_PLL_ARM_POWERDOWN (1 << 12) | |
33 | #define BM_PLL_ARM_ENABLE (1 << 13) | |
34 | #define BM_PLL_ARM_LOCK (1 << 31) | |
35 | #define PLL_ARM_DIV_792M 66 | |
36 | ||
b21c22e3 LY |
37 | static const char *step_sels[] = { "osc", "pll2_pfd2", }; |
38 | static const char *pll1_sw_sels[] = { "pll1_sys", "step", }; | |
39 | static const char *ocram_alt_sels[] = { "pll2_pfd2", "pll3_pfd1", }; | |
40 | static const char *ocram_sels[] = { "periph", "ocram_alt_sels", }; | |
41 | static const char *pre_periph_sels[] = { "pll2_bus", "pll2_pfd2", "pll2_pfd0", "pll2_198m", }; | |
42 | static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", }; | |
43 | static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", }; | |
44 | static const char *periph_sels[] = { "pre_periph_sel", "periph_clk2_podf", }; | |
45 | static const char *periph2_sels[] = { "pre_periph2_sel", "periph2_clk2_podf", }; | |
bad66c3e FE |
46 | static const char *csi_sels[] = { "osc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", }; |
47 | static const char *lcdif_axi_sels[] = { "pll2_bus", "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", }; | |
b21c22e3 LY |
48 | static const char *usdhc_sels[] = { "pll2_pfd2", "pll2_pfd0", }; |
49 | static const char *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_audio_div", "dummy", }; | |
50 | static const char *perclk_sels[] = { "ipg", "osc", }; | |
e37c1ad0 FF |
51 | static const char *pxp_axi_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd3", }; |
52 | static const char *epdc_axi_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd2", }; | |
b21c22e3 LY |
53 | static const char *gpu2d_ovg_sels[] = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", }; |
54 | static const char *gpu2d_sels[] = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", }; | |
55 | static const char *lcdif_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", }; | |
56 | static const char *epdc_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", }; | |
57 | static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", }; | |
58 | static const char *ecspi_sels[] = { "pll3_60m", "osc", }; | |
59 | static const char *uart_sels[] = { "pll3_80m", "osc", }; | |
45fe6810 SG |
60 | |
61 | static struct clk_div_table clk_enet_ref_table[] = { | |
62 | { .val = 0, .div = 20, }, | |
63 | { .val = 1, .div = 10, }, | |
64 | { .val = 2, .div = 5, }, | |
65 | { .val = 3, .div = 4, }, | |
66 | { } | |
67 | }; | |
68 | ||
69 | static struct clk_div_table post_div_table[] = { | |
70 | { .val = 2, .div = 1, }, | |
71 | { .val = 1, .div = 2, }, | |
72 | { .val = 0, .div = 4, }, | |
73 | { } | |
74 | }; | |
75 | ||
76 | static struct clk_div_table video_div_table[] = { | |
77 | { .val = 0, .div = 1, }, | |
78 | { .val = 1, .div = 2, }, | |
79 | { .val = 2, .div = 1, }, | |
80 | { .val = 3, .div = 4, }, | |
81 | { } | |
82 | }; | |
83 | ||
4e5d0d61 | 84 | static struct clk *clks[IMX6SL_CLK_END]; |
45fe6810 | 85 | static struct clk_onecell_data clk_data; |
6e6cdf66 AH |
86 | static void __iomem *ccm_base; |
87 | static void __iomem *anatop_base; | |
45fe6810 | 88 | |
17626b7c AH |
89 | static const u32 clks_init_on[] __initconst = { |
90 | IMX6SL_CLK_IPG, IMX6SL_CLK_ARM, IMX6SL_CLK_MMDC_ROOT, | |
91 | }; | |
92 | ||
751f7e99 AH |
93 | /* |
94 | * ERR005311 CCM: After exit from WAIT mode, unwanted interrupt(s) taken | |
95 | * during WAIT mode entry process could cause cache memory | |
96 | * corruption. | |
97 | * | |
98 | * Software workaround: | |
99 | * To prevent this issue from occurring, software should ensure that the | |
100 | * ARM to IPG clock ratio is less than 12:5 (that is < 2.4x), before | |
101 | * entering WAIT mode. | |
102 | * | |
103 | * This function will set the ARM clk to max value within the 12:5 limit. | |
6e6cdf66 AH |
104 | * As IPG clock is fixed at 66MHz(so ARM freq must not exceed 158.4MHz), |
105 | * ARM freq are one of below setpoints: 396MHz, 792MHz and 996MHz, since | |
106 | * the clk APIs can NOT be called in idle thread(may cause kernel schedule | |
107 | * as there is sleep function in PLL wait function), so here we just slow | |
108 | * down ARM to below freq according to previous freq: | |
109 | * | |
110 | * run mode wait mode | |
111 | * 396MHz -> 132MHz; | |
112 | * 792MHz -> 158.4MHz; | |
113 | * 996MHz -> 142.3MHz; | |
751f7e99 | 114 | */ |
6e6cdf66 AH |
115 | static int imx6sl_get_arm_divider_for_wait(void) |
116 | { | |
117 | if (readl_relaxed(ccm_base + CCSR) & BM_CCSR_PLL1_SW_CLK_SEL) { | |
118 | return ARM_WAIT_DIV_396M; | |
119 | } else { | |
120 | if ((readl_relaxed(anatop_base + PLL_ARM) & | |
121 | BM_PLL_ARM_DIV_SELECT) == PLL_ARM_DIV_792M) | |
122 | return ARM_WAIT_DIV_792M; | |
123 | else | |
124 | return ARM_WAIT_DIV_996M; | |
125 | } | |
126 | } | |
127 | ||
128 | static void imx6sl_enable_pll_arm(bool enable) | |
129 | { | |
130 | static u32 saved_pll_arm; | |
131 | u32 val; | |
132 | ||
133 | if (enable) { | |
134 | saved_pll_arm = val = readl_relaxed(anatop_base + PLL_ARM); | |
135 | val |= BM_PLL_ARM_ENABLE; | |
136 | val &= ~BM_PLL_ARM_POWERDOWN; | |
137 | writel_relaxed(val, anatop_base + PLL_ARM); | |
138 | while (!(__raw_readl(anatop_base + PLL_ARM) & BM_PLL_ARM_LOCK)) | |
139 | ; | |
140 | } else { | |
141 | writel_relaxed(saved_pll_arm, anatop_base + PLL_ARM); | |
142 | } | |
143 | } | |
144 | ||
751f7e99 AH |
145 | void imx6sl_set_wait_clk(bool enter) |
146 | { | |
6e6cdf66 AH |
147 | static unsigned long saved_arm_div; |
148 | int arm_div_for_wait = imx6sl_get_arm_divider_for_wait(); | |
149 | ||
150 | /* | |
151 | * According to hardware design, arm podf change need | |
152 | * PLL1 clock enabled. | |
153 | */ | |
154 | if (arm_div_for_wait == ARM_WAIT_DIV_396M) | |
155 | imx6sl_enable_pll_arm(true); | |
751f7e99 AH |
156 | |
157 | if (enter) { | |
6e6cdf66 AH |
158 | saved_arm_div = readl_relaxed(ccm_base + CACRR); |
159 | writel_relaxed(arm_div_for_wait, ccm_base + CACRR); | |
751f7e99 | 160 | } else { |
6e6cdf66 | 161 | writel_relaxed(saved_arm_div, ccm_base + CACRR); |
751f7e99 | 162 | } |
6e6cdf66 AH |
163 | while (__raw_readl(ccm_base + CDHIPR) & BM_CDHIPR_ARM_PODF_BUSY) |
164 | ; | |
165 | ||
166 | if (arm_div_for_wait == ARM_WAIT_DIV_396M) | |
167 | imx6sl_enable_pll_arm(false); | |
751f7e99 AH |
168 | } |
169 | ||
53bb71da | 170 | static void __init imx6sl_clocks_init(struct device_node *ccm_node) |
45fe6810 SG |
171 | { |
172 | struct device_node *np; | |
173 | void __iomem *base; | |
45fe6810 | 174 | int i; |
848db4a0 | 175 | int ret; |
45fe6810 | 176 | |
45fe6810 SG |
177 | clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); |
178 | clks[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); | |
179 | clks[IMX6SL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); | |
180 | ||
181 | np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop"); | |
182 | base = of_iomap(np, 0); | |
183 | WARN_ON(!base); | |
6e6cdf66 | 184 | anatop_base = base; |
45fe6810 SG |
185 | |
186 | /* type name parent base div_mask */ | |
187 | clks[IMX6SL_CLK_PLL1_SYS] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f); | |
188 | clks[IMX6SL_CLK_PLL2_BUS] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1); | |
189 | clks[IMX6SL_CLK_PLL3_USB_OTG] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3); | |
190 | clks[IMX6SL_CLK_PLL4_AUDIO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f); | |
191 | clks[IMX6SL_CLK_PLL5_VIDEO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f); | |
192 | clks[IMX6SL_CLK_PLL6_ENET] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3); | |
193 | clks[IMX6SL_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host", "osc", base + 0x20, 0x3); | |
194 | ||
195 | /* | |
196 | * usbphy1 and usbphy2 are implemented as dummy gates using reserve | |
197 | * bit 20. They are used by phy driver to keep the refcount of | |
198 | * parent PLL correct. usbphy1_gate and usbphy2_gate only needs to be | |
199 | * turned on during boot, and software will not need to control it | |
200 | * anymore after that. | |
201 | */ | |
202 | clks[IMX6SL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20); | |
203 | clks[IMX6SL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20); | |
204 | clks[IMX6SL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6); | |
205 | clks[IMX6SL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6); | |
206 | ||
207 | /* dev name parent_name flags reg shift width div: flags, div_table lock */ | |
208 | clks[IMX6SL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); | |
238fb182 | 209 | clks[IMX6SL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); |
45fe6810 SG |
210 | clks[IMX6SL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); |
211 | clks[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); | |
212 | clks[IMX6SL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock); | |
213 | ||
214 | /* name parent_name reg idx */ | |
215 | clks[IMX6SL_CLK_PLL2_PFD0] = imx_clk_pfd("pll2_pfd0", "pll2_bus", base + 0x100, 0); | |
216 | clks[IMX6SL_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_bus", base + 0x100, 1); | |
217 | clks[IMX6SL_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_bus", base + 0x100, 2); | |
218 | clks[IMX6SL_CLK_PLL3_PFD0] = imx_clk_pfd("pll3_pfd0", "pll3_usb_otg", base + 0xf0, 0); | |
219 | clks[IMX6SL_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_usb_otg", base + 0xf0, 1); | |
220 | clks[IMX6SL_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_usb_otg", base + 0xf0, 2); | |
221 | clks[IMX6SL_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_usb_otg", base + 0xf0, 3); | |
222 | ||
223 | /* name parent_name mult div */ | |
224 | clks[IMX6SL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2", 1, 2); | |
225 | clks[IMX6SL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4); | |
226 | clks[IMX6SL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); | |
227 | clks[IMX6SL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); | |
228 | ||
53bb71da | 229 | np = ccm_node; |
45fe6810 SG |
230 | base = of_iomap(np, 0); |
231 | WARN_ON(!base); | |
6e6cdf66 | 232 | ccm_base = base; |
45fe6810 | 233 | |
9ba64fe3 SG |
234 | /* Reuse imx6q pm code */ |
235 | imx6q_pm_set_ccm_base(base); | |
236 | ||
45fe6810 SG |
237 | /* name reg shift width parent_names num_parents */ |
238 | clks[IMX6SL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); | |
239 | clks[IMX6SL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); | |
240 | clks[IMX6SL_CLK_OCRAM_ALT_SEL] = imx_clk_mux("ocram_alt_sel", base + 0x14, 7, 1, ocram_alt_sels, ARRAY_SIZE(ocram_alt_sels)); | |
241 | clks[IMX6SL_CLK_OCRAM_SEL] = imx_clk_mux("ocram_sel", base + 0x14, 6, 1, ocram_sels, ARRAY_SIZE(ocram_sels)); | |
242 | clks[IMX6SL_CLK_PRE_PERIPH2_SEL] = imx_clk_mux("pre_periph2_sel", base + 0x18, 21, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels)); | |
243 | clks[IMX6SL_CLK_PRE_PERIPH_SEL] = imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels)); | |
244 | clks[IMX6SL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); | |
245 | clks[IMX6SL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); | |
bad66c3e FE |
246 | clks[IMX6SL_CLK_CSI_SEL] = imx_clk_mux("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels)); |
247 | clks[IMX6SL_CLK_LCDIF_AXI_SEL] = imx_clk_mux("lcdif_axi_sel", base + 0x3c, 14, 2, lcdif_axi_sels, ARRAY_SIZE(lcdif_axi_sels)); | |
dfd87144 LY |
248 | clks[IMX6SL_CLK_USDHC1_SEL] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); |
249 | clks[IMX6SL_CLK_USDHC2_SEL] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); | |
250 | clks[IMX6SL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); | |
251 | clks[IMX6SL_CLK_USDHC4_SEL] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); | |
252 | clks[IMX6SL_CLK_SSI1_SEL] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); | |
253 | clks[IMX6SL_CLK_SSI2_SEL] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); | |
254 | clks[IMX6SL_CLK_SSI3_SEL] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); | |
255 | clks[IMX6SL_CLK_PERCLK_SEL] = imx_clk_fixup_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels), imx_cscmr1_fixup); | |
e37c1ad0 FF |
256 | clks[IMX6SL_CLK_PXP_AXI_SEL] = imx_clk_mux("pxp_axi_sel", base + 0x34, 6, 3, pxp_axi_sels, ARRAY_SIZE(pxp_axi_sels)); |
257 | clks[IMX6SL_CLK_EPDC_AXI_SEL] = imx_clk_mux("epdc_axi_sel", base + 0x34, 15, 3, epdc_axi_sels, ARRAY_SIZE(epdc_axi_sels)); | |
45fe6810 SG |
258 | clks[IMX6SL_CLK_GPU2D_OVG_SEL] = imx_clk_mux("gpu2d_ovg_sel", base + 0x18, 4, 2, gpu2d_ovg_sels, ARRAY_SIZE(gpu2d_ovg_sels)); |
259 | clks[IMX6SL_CLK_GPU2D_SEL] = imx_clk_mux("gpu2d_sel", base + 0x18, 8, 2, gpu2d_sels, ARRAY_SIZE(gpu2d_sels)); | |
260 | clks[IMX6SL_CLK_LCDIF_PIX_SEL] = imx_clk_mux("lcdif_pix_sel", base + 0x38, 6, 3, lcdif_pix_sels, ARRAY_SIZE(lcdif_pix_sels)); | |
261 | clks[IMX6SL_CLK_EPDC_PIX_SEL] = imx_clk_mux("epdc_pix_sel", base + 0x38, 15, 3, epdc_pix_sels, ARRAY_SIZE(epdc_pix_sels)); | |
262 | clks[IMX6SL_CLK_SPDIF0_SEL] = imx_clk_mux("spdif0_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); | |
263 | clks[IMX6SL_CLK_SPDIF1_SEL] = imx_clk_mux("spdif1_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); | |
264 | clks[IMX6SL_CLK_EXTERN_AUDIO_SEL] = imx_clk_mux("extern_audio_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); | |
265 | clks[IMX6SL_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels)); | |
266 | clks[IMX6SL_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels)); | |
267 | ||
268 | /* name reg shift width busy: reg, shift parent_names num_parents */ | |
269 | clks[IMX6SL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); | |
270 | clks[IMX6SL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); | |
271 | ||
272 | /* name parent_name reg shift width */ | |
273 | clks[IMX6SL_CLK_OCRAM_PODF] = imx_clk_divider("ocram_podf", "ocram_sel", base + 0x14, 16, 3); | |
274 | clks[IMX6SL_CLK_PERIPH_CLK2_PODF] = imx_clk_divider("periph_clk2_podf", "periph_clk2_sel", base + 0x14, 27, 3); | |
275 | clks[IMX6SL_CLK_PERIPH2_CLK2_PODF] = imx_clk_divider("periph2_clk2_podf", "periph2_clk2_sel", base + 0x14, 0, 3); | |
276 | clks[IMX6SL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); | |
277 | clks[IMX6SL_CLK_CSI_PODF] = imx_clk_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3); | |
278 | clks[IMX6SL_CLK_LCDIF_AXI_PODF] = imx_clk_divider("lcdif_axi_podf", "lcdif_axi_sel", base + 0x3c, 16, 3); | |
279 | clks[IMX6SL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3); | |
280 | clks[IMX6SL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3); | |
281 | clks[IMX6SL_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3); | |
282 | clks[IMX6SL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); | |
283 | clks[IMX6SL_CLK_SSI1_PRED] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3); | |
284 | clks[IMX6SL_CLK_SSI1_PODF] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6); | |
285 | clks[IMX6SL_CLK_SSI2_PRED] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3); | |
286 | clks[IMX6SL_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6); | |
287 | clks[IMX6SL_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3); | |
288 | clks[IMX6SL_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6); | |
dfd87144 | 289 | clks[IMX6SL_CLK_PERCLK] = imx_clk_fixup_divider("perclk", "perclk_sel", base + 0x1c, 0, 6, imx_cscmr1_fixup); |
45fe6810 SG |
290 | clks[IMX6SL_CLK_PXP_AXI_PODF] = imx_clk_divider("pxp_axi_podf", "pxp_axi_sel", base + 0x34, 3, 3); |
291 | clks[IMX6SL_CLK_EPDC_AXI_PODF] = imx_clk_divider("epdc_axi_podf", "epdc_axi_sel", base + 0x34, 12, 3); | |
292 | clks[IMX6SL_CLK_GPU2D_OVG_PODF] = imx_clk_divider("gpu2d_ovg_podf", "gpu2d_ovg_sel", base + 0x18, 26, 3); | |
293 | clks[IMX6SL_CLK_GPU2D_PODF] = imx_clk_divider("gpu2d_podf", "gpu2d_sel", base + 0x18, 29, 3); | |
294 | clks[IMX6SL_CLK_LCDIF_PIX_PRED] = imx_clk_divider("lcdif_pix_pred", "lcdif_pix_sel", base + 0x38, 3, 3); | |
295 | clks[IMX6SL_CLK_EPDC_PIX_PRED] = imx_clk_divider("epdc_pix_pred", "epdc_pix_sel", base + 0x38, 12, 3); | |
dfd87144 | 296 | clks[IMX6SL_CLK_LCDIF_PIX_PODF] = imx_clk_fixup_divider("lcdif_pix_podf", "lcdif_pix_pred", base + 0x1c, 20, 3, imx_cscmr1_fixup); |
45fe6810 SG |
297 | clks[IMX6SL_CLK_EPDC_PIX_PODF] = imx_clk_divider("epdc_pix_podf", "epdc_pix_pred", base + 0x18, 23, 3); |
298 | clks[IMX6SL_CLK_SPDIF0_PRED] = imx_clk_divider("spdif0_pred", "spdif0_sel", base + 0x30, 25, 3); | |
299 | clks[IMX6SL_CLK_SPDIF0_PODF] = imx_clk_divider("spdif0_podf", "spdif0_pred", base + 0x30, 22, 3); | |
300 | clks[IMX6SL_CLK_SPDIF1_PRED] = imx_clk_divider("spdif1_pred", "spdif1_sel", base + 0x30, 12, 3); | |
301 | clks[IMX6SL_CLK_SPDIF1_PODF] = imx_clk_divider("spdif1_podf", "spdif1_pred", base + 0x30, 9, 3); | |
302 | clks[IMX6SL_CLK_EXTERN_AUDIO_PRED] = imx_clk_divider("extern_audio_pred", "extern_audio_sel", base + 0x28, 9, 3); | |
303 | clks[IMX6SL_CLK_EXTERN_AUDIO_PODF] = imx_clk_divider("extern_audio_podf", "extern_audio_pred", base + 0x28, 25, 3); | |
304 | clks[IMX6SL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "ecspi_sel", base + 0x38, 19, 6); | |
305 | clks[IMX6SL_CLK_UART_ROOT] = imx_clk_divider("uart_root", "uart_sel", base + 0x24, 0, 6); | |
306 | ||
307 | /* name parent_name reg shift width busy: reg, shift */ | |
308 | clks[IMX6SL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); | |
309 | clks[IMX6SL_CLK_MMDC_ROOT] = imx_clk_busy_divider("mmdc", "periph2", base + 0x14, 3, 3, base + 0x48, 2); | |
310 | clks[IMX6SL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); | |
311 | ||
312 | /* name parent_name reg shift */ | |
313 | clks[IMX6SL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0); | |
314 | clks[IMX6SL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2); | |
315 | clks[IMX6SL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4); | |
316 | clks[IMX6SL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6); | |
4ca2ad55 | 317 | clks[IMX6SL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10); |
45fe6810 SG |
318 | clks[IMX6SL_CLK_EPIT1] = imx_clk_gate2("epit1", "perclk", base + 0x6c, 12); |
319 | clks[IMX6SL_CLK_EPIT2] = imx_clk_gate2("epit2", "perclk", base + 0x6c, 14); | |
320 | clks[IMX6SL_CLK_EXTERN_AUDIO] = imx_clk_gate2("extern_audio", "extern_audio_podf", base + 0x6c, 16); | |
321 | clks[IMX6SL_CLK_GPT] = imx_clk_gate2("gpt", "perclk", base + 0x6c, 20); | |
322 | clks[IMX6SL_CLK_GPT_SERIAL] = imx_clk_gate2("gpt_serial", "perclk", base + 0x6c, 22); | |
323 | clks[IMX6SL_CLK_GPU2D_OVG] = imx_clk_gate2("gpu2d_ovg", "gpu2d_ovg_podf", base + 0x6c, 26); | |
324 | clks[IMX6SL_CLK_I2C1] = imx_clk_gate2("i2c1", "perclk", base + 0x70, 6); | |
325 | clks[IMX6SL_CLK_I2C2] = imx_clk_gate2("i2c2", "perclk", base + 0x70, 8); | |
326 | clks[IMX6SL_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10); | |
327 | clks[IMX6SL_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12); | |
328 | clks[IMX6SL_CLK_CSI] = imx_clk_gate2("csi", "csi_podf", base + 0x74, 0); | |
329 | clks[IMX6SL_CLK_PXP_AXI] = imx_clk_gate2("pxp_axi", "pxp_axi_podf", base + 0x74, 2); | |
330 | clks[IMX6SL_CLK_EPDC_AXI] = imx_clk_gate2("epdc_axi", "epdc_axi_podf", base + 0x74, 4); | |
331 | clks[IMX6SL_CLK_LCDIF_AXI] = imx_clk_gate2("lcdif_axi", "lcdif_axi_podf", base + 0x74, 6); | |
332 | clks[IMX6SL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix", "lcdif_pix_podf", base + 0x74, 8); | |
333 | clks[IMX6SL_CLK_EPDC_PIX] = imx_clk_gate2("epdc_pix", "epdc_pix_podf", base + 0x74, 10); | |
334 | clks[IMX6SL_CLK_OCRAM] = imx_clk_gate2("ocram", "ocram_podf", base + 0x74, 28); | |
335 | clks[IMX6SL_CLK_PWM1] = imx_clk_gate2("pwm1", "perclk", base + 0x78, 16); | |
336 | clks[IMX6SL_CLK_PWM2] = imx_clk_gate2("pwm2", "perclk", base + 0x78, 18); | |
337 | clks[IMX6SL_CLK_PWM3] = imx_clk_gate2("pwm3", "perclk", base + 0x78, 20); | |
338 | clks[IMX6SL_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22); | |
339 | clks[IMX6SL_CLK_SDMA] = imx_clk_gate2("sdma", "ipg", base + 0x7c, 6); | |
8962a5db | 340 | clks[IMX6SL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); |
45fe6810 SG |
341 | clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif0_podf", base + 0x7c, 14); |
342 | clks[IMX6SL_CLK_SSI1] = imx_clk_gate2("ssi1", "ssi1_podf", base + 0x7c, 18); | |
343 | clks[IMX6SL_CLK_SSI2] = imx_clk_gate2("ssi2", "ssi2_podf", base + 0x7c, 20); | |
344 | clks[IMX6SL_CLK_SSI3] = imx_clk_gate2("ssi3", "ssi3_podf", base + 0x7c, 22); | |
345 | clks[IMX6SL_CLK_UART] = imx_clk_gate2("uart", "ipg", base + 0x7c, 24); | |
346 | clks[IMX6SL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_root", base + 0x7c, 26); | |
347 | clks[IMX6SL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); | |
348 | clks[IMX6SL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); | |
349 | clks[IMX6SL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); | |
350 | clks[IMX6SL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); | |
351 | clks[IMX6SL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); | |
352 | ||
229be9c1 | 353 | imx_check_clocks(clks, ARRAY_SIZE(clks)); |
45fe6810 SG |
354 | |
355 | clk_data.clks = clks; | |
356 | clk_data.clk_num = ARRAY_SIZE(clks); | |
357 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | |
358 | ||
848db4a0 AH |
359 | /* Ensure the AHB clk is at 132MHz. */ |
360 | ret = clk_set_rate(clks[IMX6SL_CLK_AHB], 132000000); | |
361 | if (ret) | |
362 | pr_warn("%s: failed to set AHB clock rate %d!\n", | |
363 | __func__, ret); | |
364 | ||
17626b7c AH |
365 | /* |
366 | * Make sure those always on clocks are enabled to maintain the correct | |
367 | * usecount and enabling/disabling of parent PLLs. | |
368 | */ | |
369 | for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) | |
370 | clk_prepare_enable(clks[clks_init_on[i]]); | |
371 | ||
45fe6810 SG |
372 | if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { |
373 | clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]); | |
374 | clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]); | |
375 | } | |
376 | ||
4390e622 NC |
377 | /* Audio-related clocks configuration */ |
378 | clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]); | |
379 | ||
0783a560 FE |
380 | /* set PLL5 video as lcdif pix parent clock */ |
381 | clk_set_parent(clks[IMX6SL_CLK_LCDIF_PIX_SEL], | |
382 | clks[IMX6SL_CLK_PLL5_VIDEO_DIV]); | |
383 | ||
384 | clk_set_parent(clks[IMX6SL_CLK_LCDIF_AXI_SEL], | |
385 | clks[IMX6SL_CLK_PLL2_PFD2]); | |
386 | ||
e7c57ecd PZ |
387 | /* Set initial power mode */ |
388 | imx6q_set_lpm(WAIT_CLOCKED); | |
45fe6810 | 389 | } |
53bb71da | 390 | CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init); |