[deliverable/linux.git] / arch / arm / mach-imx / clk-pllv3.c

/*
 * Copyright 2012 Freescale Semiconductor, Inc.
 * Copyright 2012 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/jiffies.h>
#include <linux/err.h>
#include "clk.h"

#define PLL_NUM_OFFSET		0x10
#define PLL_DENOM_OFFSET	0x20

#define BM_PLL_POWER		(0x1 << 12)
#define BM_PLL_ENABLE		(0x1 << 13)
#define BM_PLL_BYPASS		(0x1 << 16)
#define BM_PLL_LOCK		(0x1 << 31)

/**
 * struct clk_pllv3 - IMX PLL clock version 3
 * @clk_hw:	 clock source
 * @base:	 base address of PLL registers
 * @powerup_set: set POWER bit to power up the PLL
 * @div_mask:	 mask of divider bits
 *
 * IMX PLL clock version 3, found on i.MX6 series.  Divider for pllv3
 * is actually a multiplier, and always sits at bit 0.
 */
struct clk_pllv3 {
	struct clk_hw	hw;
	void __iomem	*base;
	bool		powerup_set;
	u32		div_mask;
};

#define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)

static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
{
	unsigned long timeout = jiffies + msecs_to_jiffies(10);
	u32 val = readl_relaxed(pll->base) & BM_PLL_POWER;

	/* No need to wait for lock when pll is not powered up */
	if ((pll->powerup_set && !val) || (!pll->powerup_set && val))
		return 0;

	/* Wait for PLL to lock */
	do {
		if (readl_relaxed(pll->base) & BM_PLL_LOCK)
			break;
		if (time_after(jiffies, timeout))
			break;
		usleep_range(50, 500);
	} while (1);

	return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT;
}

static int clk_pllv3_prepare(struct clk_hw *hw)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	u32 val;
	int ret;

	val = readl_relaxed(pll->base);
	if (pll->powerup_set)
		val |= BM_PLL_POWER;
	else
		val &= ~BM_PLL_POWER;
	writel_relaxed(val, pll->base);

	ret = clk_pllv3_wait_lock(pll);
	if (ret)
		return ret;

	val = readl_relaxed(pll->base);
	val &= ~BM_PLL_BYPASS;
	writel_relaxed(val, pll->base);

	return 0;
}

static void clk_pllv3_unprepare(struct clk_hw *hw)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	u32 val;

	val = readl_relaxed(pll->base);
	val |= BM_PLL_BYPASS;
	if (pll->powerup_set)
		val &= ~BM_PLL_POWER;
	else
		val |= BM_PLL_POWER;
	writel_relaxed(val, pll->base);
}

static int clk_pllv3_enable(struct clk_hw *hw)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	u32 val;

	val = readl_relaxed(pll->base);
	val |= BM_PLL_ENABLE;
	writel_relaxed(val, pll->base);

	return 0;
}

static void clk_pllv3_disable(struct clk_hw *hw)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	u32 val;

	val = readl_relaxed(pll->base);
	val &= ~BM_PLL_ENABLE;
	writel_relaxed(val, pll->base);
}

static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
					   unsigned long parent_rate)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	u32 div = readl_relaxed(pll->base)  & pll->div_mask;

	return (div == 1) ? parent_rate * 22 : parent_rate * 20;
}

static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate,
				 unsigned long *prate)
{
	unsigned long parent_rate = *prate;

	return (rate >= parent_rate * 22) ? parent_rate * 22 :
					    parent_rate * 20;
}

static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	u32 val, div;

	if (rate == parent_rate * 22)
		div = 1;
	else if (rate == parent_rate * 20)
		div = 0;
	else
		return -EINVAL;

	val = readl_relaxed(pll->base);
	val &= ~pll->div_mask;
	val |= div;
	writel_relaxed(val, pll->base);

	return clk_pllv3_wait_lock(pll);
}

static const struct clk_ops clk_pllv3_ops = {
	.prepare	= clk_pllv3_prepare,
	.unprepare	= clk_pllv3_unprepare,
	.enable		= clk_pllv3_enable,
	.disable	= clk_pllv3_disable,
	.recalc_rate	= clk_pllv3_recalc_rate,
	.round_rate	= clk_pllv3_round_rate,
	.set_rate	= clk_pllv3_set_rate,
};

static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw,
					       unsigned long parent_rate)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	u32 div = readl_relaxed(pll->base) & pll->div_mask;

	return parent_rate * div / 2;
}

static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate,
				     unsigned long *prate)
{
	unsigned long parent_rate = *prate;
	unsigned long min_rate = parent_rate * 54 / 2;
	unsigned long max_rate = parent_rate * 108 / 2;
	u32 div;

	if (rate > max_rate)
		rate = max_rate;
	else if (rate < min_rate)
		rate = min_rate;
	div = rate * 2 / parent_rate;

	return parent_rate * div / 2;
}

static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	unsigned long min_rate = parent_rate * 54 / 2;
	unsigned long max_rate = parent_rate * 108 / 2;
	u32 val, div;

	if (rate < min_rate || rate > max_rate)
		return -EINVAL;

	div = rate * 2 / parent_rate;
	val = readl_relaxed(pll->base);
	val &= ~pll->div_mask;
	val |= div;
	writel_relaxed(val, pll->base);

	return clk_pllv3_wait_lock(pll);
}

static const struct clk_ops clk_pllv3_sys_ops = {
	.prepare	= clk_pllv3_prepare,
	.unprepare	= clk_pllv3_unprepare,
	.enable		= clk_pllv3_enable,
	.disable	= clk_pllv3_disable,
	.recalc_rate	= clk_pllv3_sys_recalc_rate,
	.round_rate	= clk_pllv3_sys_round_rate,
	.set_rate	= clk_pllv3_sys_set_rate,
};

static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
					      unsigned long parent_rate)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);
	u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);
	u32 div = readl_relaxed(pll->base) & pll->div_mask;

	return (parent_rate * div) + ((parent_rate / mfd) * mfn);
}

static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
				    unsigned long *prate)
{
	unsigned long parent_rate = *prate;
	unsigned long min_rate = parent_rate * 27;
	unsigned long max_rate = parent_rate * 54;
	u32 div;
	u32 mfn, mfd = 1000000;
	s64 temp64;

	if (rate > max_rate)
		rate = max_rate;
	else if (rate < min_rate)
		rate = min_rate;

	div = rate / parent_rate;
	temp64 = (u64) (rate - div * parent_rate);
	temp64 *= mfd;
	do_div(temp64, parent_rate);
	mfn = temp64;

	return parent_rate * div + parent_rate / mfd * mfn;
}

static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	unsigned long min_rate = parent_rate * 27;
	unsigned long max_rate = parent_rate * 54;
	u32 val, div;
	u32 mfn, mfd = 1000000;
	s64 temp64;

	if (rate < min_rate || rate > max_rate)
		return -EINVAL;

	div = rate / parent_rate;
	temp64 = (u64) (rate - div * parent_rate);
	temp64 *= mfd;
	do_div(temp64, parent_rate);
	mfn = temp64;

	val = readl_relaxed(pll->base);
	val &= ~pll->div_mask;
	val |= div;
	writel_relaxed(val, pll->base);
	writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
	writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);

	return clk_pllv3_wait_lock(pll);
}

static const struct clk_ops clk_pllv3_av_ops = {
	.prepare	= clk_pllv3_prepare,
	.unprepare	= clk_pllv3_unprepare,
	.enable		= clk_pllv3_enable,
	.disable	= clk_pllv3_disable,
	.recalc_rate	= clk_pllv3_av_recalc_rate,
	.round_rate	= clk_pllv3_av_round_rate,
	.set_rate	= clk_pllv3_av_set_rate,
};

static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
						unsigned long parent_rate)
{
	return 500000000;
}

static const struct clk_ops clk_pllv3_enet_ops = {
	.prepare	= clk_pllv3_prepare,
	.unprepare	= clk_pllv3_unprepare,
	.enable		= clk_pllv3_enable,
	.disable	= clk_pllv3_disable,
	.recalc_rate	= clk_pllv3_enet_recalc_rate,
};

struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
			  const char *parent_name, void __iomem *base,
			  u32 div_mask)
{
	struct clk_pllv3 *pll;
	const struct clk_ops *ops;
	struct clk *clk;
	struct clk_init_data init;

	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
	if (!pll)
		return ERR_PTR(-ENOMEM);

	switch (type) {
	case IMX_PLLV3_SYS:
		ops = &clk_pllv3_sys_ops;
		break;
	case IMX_PLLV3_USB:
		ops = &clk_pllv3_ops;
		pll->powerup_set = true;
		break;
	case IMX_PLLV3_AV:
		ops = &clk_pllv3_av_ops;
		break;
	case IMX_PLLV3_ENET:
		ops = &clk_pllv3_enet_ops;
		break;
	default:
		ops = &clk_pllv3_ops;
	}
	pll->base = base;
	pll->div_mask = div_mask;

	init.name = name;
	init.ops = ops;
	init.flags = 0;
	init.parent_names = &parent_name;
	init.num_parents = 1;

	pll->hw.init = &init;

	clk = clk_register(NULL, &pll->hw);
	if (IS_ERR(clk))
		kfree(pll);

	return clk;
}
Commit	Line	Data
a3f6b9db SG	1	/*
	2	* Copyright 2012 Freescale Semiconductor, Inc.
	3	* Copyright 2012 Linaro Ltd.
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
	13	#include <linux/clk.h>
	14	#include <linux/clk-provider.h>
322503a1	15	#include <linux/delay.h>
a3f6b9db SG	16	#include <linux/io.h>
	17	#include <linux/slab.h>
	18	#include <linux/jiffies.h>
	19	#include <linux/err.h>
	20	#include "clk.h"
	21
	22	#define PLL_NUM_OFFSET 0x10
	23	#define PLL_DENOM_OFFSET 0x20
	24
	25	#define BM_PLL_POWER (0x1 << 12)
	26	#define BM_PLL_ENABLE (0x1 << 13)
	27	#define BM_PLL_BYPASS (0x1 << 16)
	28	#define BM_PLL_LOCK (0x1 << 31)
	29
	30	/**
	31	* struct clk_pllv3 - IMX PLL clock version 3
	32	* @clk_hw: clock source
	33	* @base: base address of PLL registers
	34	* @powerup_set: set POWER bit to power up the PLL
a3f6b9db SG	35	* @div_mask: mask of divider bits
	36	*
	37	* IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3
	38	* is actually a multiplier, and always sits at bit 0.
	39	*/
	40	struct clk_pllv3 {
	41	struct clk_hw hw;
	42	void __iomem *base;
	43	bool powerup_set;
a3f6b9db SG	44	u32 div_mask;
	45	};
	46
	47	#define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
	48
bc3b84da	49	static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
a3f6b9db	50	{
bc3b84da SG	51	unsigned long timeout = jiffies + msecs_to_jiffies(10);
bc3b84da SG	52	u32 val = readl_relaxed(pll->base) & BM_PLL_POWER;
a3f6b9db	53
bc3b84da SG	54	/* No need to wait for lock when pll is not powered up */
	55	if ((pll->powerup_set && !val) \|\| (!pll->powerup_set && val))
	56	return 0;
a3f6b9db SG	57
a3f6b9db SG	58	/* Wait for PLL to lock */
0a036388 PC	59	do {
	60	if (readl_relaxed(pll->base) & BM_PLL_LOCK)
	61	break;
a3f6b9db	62	if (time_after(jiffies, timeout))
0a036388	63	break;
322503a1	64	usleep_range(50, 500);
0a036388	65	} while (1);
a3f6b9db	66
bc3b84da SG	67	return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT;
	68	}
	69
	70	static int clk_pllv3_prepare(struct clk_hw *hw)
	71	{
	72	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	73	u32 val;
43c9b9e8	74	int ret;
bc3b84da SG	75
bc3b84da SG	76	val = readl_relaxed(pll->base);
bc3b84da SG	77	if (pll->powerup_set)
bc3b84da SG	78	val \|= BM_PLL_POWER;
0a036388	79	else
bc3b84da SG	80	val &= ~BM_PLL_POWER;
	81	writel_relaxed(val, pll->base);
	82
43c9b9e8 SG	83	ret = clk_pllv3_wait_lock(pll);
	84	if (ret)
	85	return ret;
	86
	87	val = readl_relaxed(pll->base);
	88	val &= ~BM_PLL_BYPASS;
	89	writel_relaxed(val, pll->base);
	90
	91	return 0;
a3f6b9db SG	92	}
	93
	94	static void clk_pllv3_unprepare(struct clk_hw *hw)
	95	{
	96	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	97	u32 val;
	98
	99	val = readl_relaxed(pll->base);
	100	val \|= BM_PLL_BYPASS;
	101	if (pll->powerup_set)
	102	val &= ~BM_PLL_POWER;
	103	else
	104	val \|= BM_PLL_POWER;
	105	writel_relaxed(val, pll->base);
	106	}
	107
	108	static int clk_pllv3_enable(struct clk_hw *hw)
	109	{
	110	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	111	u32 val;
	112
	113	val = readl_relaxed(pll->base);
2b254693	114	val \|= BM_PLL_ENABLE;
a3f6b9db SG	115	writel_relaxed(val, pll->base);
	116
	117	return 0;
	118	}
	119
	120	static void clk_pllv3_disable(struct clk_hw *hw)
	121	{
	122	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	123	u32 val;
	124
	125	val = readl_relaxed(pll->base);
2b254693	126	val &= ~BM_PLL_ENABLE;
a3f6b9db SG	127	writel_relaxed(val, pll->base);
	128	}
	129
	130	static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
	131	unsigned long parent_rate)
	132	{
	133	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	134	u32 div = readl_relaxed(pll->base) & pll->div_mask;
	135
	136	return (div == 1) ? parent_rate * 22 : parent_rate * 20;
	137	}
	138
	139	static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate,
	140	unsigned long *prate)
	141	{
	142	unsigned long parent_rate = *prate;
	143
	144	return (rate >= parent_rate * 22) ? parent_rate * 22 :
	145	parent_rate * 20;
	146	}
	147
	148	static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
	149	unsigned long parent_rate)
	150	{
	151	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	152	u32 val, div;
	153
	154	if (rate == parent_rate * 22)
	155	div = 1;
	156	else if (rate == parent_rate * 20)
	157	div = 0;
	158	else
	159	return -EINVAL;
	160
	161	val = readl_relaxed(pll->base);
	162	val &= ~pll->div_mask;
	163	val \|= div;
	164	writel_relaxed(val, pll->base);
	165
bc3b84da	166	return clk_pllv3_wait_lock(pll);
a3f6b9db SG	167	}
	168
	169	static const struct clk_ops clk_pllv3_ops = {
	170	.prepare = clk_pllv3_prepare,
	171	.unprepare = clk_pllv3_unprepare,
	172	.enable = clk_pllv3_enable,
	173	.disable = clk_pllv3_disable,
	174	.recalc_rate = clk_pllv3_recalc_rate,
	175	.round_rate = clk_pllv3_round_rate,
	176	.set_rate = clk_pllv3_set_rate,
	177	};
	178
	179	static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw,
	180	unsigned long parent_rate)
	181	{
	182	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	183	u32 div = readl_relaxed(pll->base) & pll->div_mask;
	184
	185	return parent_rate * div / 2;
	186	}
	187
	188	static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate,
	189	unsigned long *prate)
	190	{
	191	unsigned long parent_rate = *prate;
	192	unsigned long min_rate = parent_rate * 54 / 2;
	193	unsigned long max_rate = parent_rate * 108 / 2;
	194	u32 div;
	195
	196	if (rate > max_rate)
	197	rate = max_rate;
	198	else if (rate < min_rate)
	199	rate = min_rate;
	200	div = rate * 2 / parent_rate;
	201
	202	return parent_rate * div / 2;
	203	}
	204
	205	static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
	206	unsigned long parent_rate)
	207	{
	208	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	209	unsigned long min_rate = parent_rate * 54 / 2;
	210	unsigned long max_rate = parent_rate * 108 / 2;
	211	u32 val, div;
	212
	213	if (rate < min_rate \|\| rate > max_rate)
	214	return -EINVAL;
	215
	216	div = rate * 2 / parent_rate;
	217	val = readl_relaxed(pll->base);
	218	val &= ~pll->div_mask;
	219	val \|= div;
	220	writel_relaxed(val, pll->base);
	221
bc3b84da	222	return clk_pllv3_wait_lock(pll);
a3f6b9db SG	223	}
	224
	225	static const struct clk_ops clk_pllv3_sys_ops = {
	226	.prepare = clk_pllv3_prepare,
	227	.unprepare = clk_pllv3_unprepare,
	228	.enable = clk_pllv3_enable,
	229	.disable = clk_pllv3_disable,
	230	.recalc_rate = clk_pllv3_sys_recalc_rate,
	231	.round_rate = clk_pllv3_sys_round_rate,
	232	.set_rate = clk_pllv3_sys_set_rate,
	233	};
	234
	235	static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
	236	unsigned long parent_rate)
	237	{
	238	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	239	u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);
	240	u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);
	241	u32 div = readl_relaxed(pll->base) & pll->div_mask;
	242
	243	return (parent_rate * div) + ((parent_rate / mfd) * mfn);
	244	}
	245
	246	static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
	247	unsigned long *prate)
	248	{
	249	unsigned long parent_rate = *prate;
	250	unsigned long min_rate = parent_rate * 27;
	251	unsigned long max_rate = parent_rate * 54;
	252	u32 div;
	253	u32 mfn, mfd = 1000000;
	254	s64 temp64;
	255
	256	if (rate > max_rate)
	257	rate = max_rate;
	258	else if (rate < min_rate)
	259	rate = min_rate;
	260
	261	div = rate / parent_rate;
	262	temp64 = (u64) (rate - div * parent_rate);
	263	temp64 *= mfd;
	264	do_div(temp64, parent_rate);
	265	mfn = temp64;
	266
	267	return parent_rate * div + parent_rate / mfd * mfn;
	268	}
	269
	270	static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
	271	unsigned long parent_rate)
	272	{
	273	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	274	unsigned long min_rate = parent_rate * 27;
	275	unsigned long max_rate = parent_rate * 54;
	276	u32 val, div;
	277	u32 mfn, mfd = 1000000;
	278	s64 temp64;
	279
	280	if (rate < min_rate \|\| rate > max_rate)
	281	return -EINVAL;
	282
	283	div = rate / parent_rate;
	284	temp64 = (u64) (rate - div * parent_rate);
	285	temp64 *= mfd;
	286	do_div(temp64, parent_rate);
287	mfn = temp64;
288
289	val = readl_relaxed(pll->base);
290	val &= ~pll->div_mask;
291	val \|= div;
292	writel_relaxed(val, pll->base);
293	writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
294	writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);
295
bc3b84da	296	return clk_pllv3_wait_lock(pll);
a3f6b9db SG	297	}
	298
	299	static const struct clk_ops clk_pllv3_av_ops = {
	300	.prepare = clk_pllv3_prepare,
	301	.unprepare = clk_pllv3_unprepare,
	302	.enable = clk_pllv3_enable,
	303	.disable = clk_pllv3_disable,
	304	.recalc_rate = clk_pllv3_av_recalc_rate,
	305	.round_rate = clk_pllv3_av_round_rate,
	306	.set_rate = clk_pllv3_av_set_rate,
	307	};
	308
	309	static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
	310	unsigned long parent_rate)
	311	{
7a04092c	312	return 500000000;
a3f6b9db SG	313	}
	314
	315	static const struct clk_ops clk_pllv3_enet_ops = {
	316	.prepare = clk_pllv3_prepare,
	317	.unprepare = clk_pllv3_unprepare,
	318	.enable = clk_pllv3_enable,
	319	.disable = clk_pllv3_disable,
	320	.recalc_rate = clk_pllv3_enet_recalc_rate,
a3f6b9db SG	321	};
a3f6b9db SG	322
a3f6b9db SG	323	struct clk imx_clk_pllv3(enum imx_pllv3_type type, const char name,
a3f6b9db SG	324	const char parent_name, void __iomem base,
2b254693	325	u32 div_mask)
a3f6b9db SG	326	{
	327	struct clk_pllv3 *pll;
	328	const struct clk_ops *ops;
	329	struct clk *clk;
	330	struct clk_init_data init;
	331
	332	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
	333	if (!pll)
	334	return ERR_PTR(-ENOMEM);
	335
	336	switch (type) {
	337	case IMX_PLLV3_SYS:
	338	ops = &clk_pllv3_sys_ops;
	339	break;
	340	case IMX_PLLV3_USB:
	341	ops = &clk_pllv3_ops;
	342	pll->powerup_set = true;
	343	break;
	344	case IMX_PLLV3_AV:
	345	ops = &clk_pllv3_av_ops;
	346	break;
	347	case IMX_PLLV3_ENET:
	348	ops = &clk_pllv3_enet_ops;
	349	break;
a3f6b9db SG	350	default:
	351	ops = &clk_pllv3_ops;
	352	}
	353	pll->base = base;
a3f6b9db SG	354	pll->div_mask = div_mask;
	355
	356	init.name = name;
	357	init.ops = ops;
	358	init.flags = 0;
	359	init.parent_names = &parent_name;
	360	init.num_parents = 1;
	361
	362	pll->hw.init = &init;
	363
	364	clk = clk_register(NULL, &pll->hw);
	365	if (IS_ERR(clk))
	366	kfree(pll);
	367
	368	return clk;
	369	}