[deliverable/linux.git] / arch / arm / mach-imx / clk-pllv3.c

/*
 * Copyright 2012 Freescale Semiconductor, Inc.
 * Copyright 2012 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/jiffies.h>
#include <linux/err.h>
#include "clk.h"

#define PLL_NUM_OFFSET		0x10
#define PLL_DENOM_OFFSET	0x20

#define BM_PLL_POWER		(0x1 << 12)
#define BM_PLL_ENABLE		(0x1 << 13)
#define BM_PLL_BYPASS		(0x1 << 16)
#define BM_PLL_LOCK		(0x1 << 31)

/**
 * struct clk_pllv3 - IMX PLL clock version 3
 * @clk_hw:	 clock source
 * @base:	 base address of PLL registers
 * @powerup_set: set POWER bit to power up the PLL
 * @div_mask:	 mask of divider bits
 *
 * IMX PLL clock version 3, found on i.MX6 series.  Divider for pllv3
 * is actually a multiplier, and always sits at bit 0.
 */
struct clk_pllv3 {
	struct clk_hw	hw;
	void __iomem	*base;
	bool		powerup_set;
	u32		div_mask;
};

#define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)

static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
{
	unsigned long timeout = jiffies + msecs_to_jiffies(10);
	u32 val = readl_relaxed(pll->base) & BM_PLL_POWER;

	/* No need to wait for lock when pll is not powered up */
	if ((pll->powerup_set && !val) || (!pll->powerup_set && val))
		return 0;

	/* Wait for PLL to lock */
	do {
		if (readl_relaxed(pll->base) & BM_PLL_LOCK)
			break;
		if (time_after(jiffies, timeout))
			break;
		usleep_range(50, 500);
	} while (1);

	return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT;
}

static int clk_pllv3_prepare(struct clk_hw *hw)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	u32 val;

	val = readl_relaxed(pll->base);
	val &= ~BM_PLL_BYPASS;
	if (pll->powerup_set)
		val |= BM_PLL_POWER;
	else
		val &= ~BM_PLL_POWER;
	writel_relaxed(val, pll->base);

	return clk_pllv3_wait_lock(pll);
}

static void clk_pllv3_unprepare(struct clk_hw *hw)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	u32 val;

	val = readl_relaxed(pll->base);
	val |= BM_PLL_BYPASS;
	if (pll->powerup_set)
		val &= ~BM_PLL_POWER;
	else
		val |= BM_PLL_POWER;
	writel_relaxed(val, pll->base);
}

static int clk_pllv3_enable(struct clk_hw *hw)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	u32 val;

	val = readl_relaxed(pll->base);
	val |= BM_PLL_ENABLE;
	writel_relaxed(val, pll->base);

	return 0;
}

static void clk_pllv3_disable(struct clk_hw *hw)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	u32 val;

	val = readl_relaxed(pll->base);
	val &= ~BM_PLL_ENABLE;
	writel_relaxed(val, pll->base);
}

static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
					   unsigned long parent_rate)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	u32 div = readl_relaxed(pll->base)  & pll->div_mask;

	return (div == 1) ? parent_rate * 22 : parent_rate * 20;
}

static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate,
				 unsigned long *prate)
{
	unsigned long parent_rate = *prate;

	return (rate >= parent_rate * 22) ? parent_rate * 22 :
					    parent_rate * 20;
}

static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	u32 val, div;

	if (rate == parent_rate * 22)
		div = 1;
	else if (rate == parent_rate * 20)
		div = 0;
	else
		return -EINVAL;

	val = readl_relaxed(pll->base);
	val &= ~pll->div_mask;
	val |= div;
	writel_relaxed(val, pll->base);

	return clk_pllv3_wait_lock(pll);
}

static const struct clk_ops clk_pllv3_ops = {
	.prepare	= clk_pllv3_prepare,
	.unprepare	= clk_pllv3_unprepare,
	.enable		= clk_pllv3_enable,
	.disable	= clk_pllv3_disable,
	.recalc_rate	= clk_pllv3_recalc_rate,
	.round_rate	= clk_pllv3_round_rate,
	.set_rate	= clk_pllv3_set_rate,
};

static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw,
					       unsigned long parent_rate)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	u32 div = readl_relaxed(pll->base) & pll->div_mask;

	return parent_rate * div / 2;
}

static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate,
				     unsigned long *prate)
{
	unsigned long parent_rate = *prate;
	unsigned long min_rate = parent_rate * 54 / 2;
	unsigned long max_rate = parent_rate * 108 / 2;
	u32 div;

	if (rate > max_rate)
		rate = max_rate;
	else if (rate < min_rate)
		rate = min_rate;
	div = rate * 2 / parent_rate;

	return parent_rate * div / 2;
}

static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	unsigned long min_rate = parent_rate * 54 / 2;
	unsigned long max_rate = parent_rate * 108 / 2;
	u32 val, div;

	if (rate < min_rate || rate > max_rate)
		return -EINVAL;

	div = rate * 2 / parent_rate;
	val = readl_relaxed(pll->base);
	val &= ~pll->div_mask;
	val |= div;
	writel_relaxed(val, pll->base);

	return clk_pllv3_wait_lock(pll);
}

static const struct clk_ops clk_pllv3_sys_ops = {
	.prepare	= clk_pllv3_prepare,
	.unprepare	= clk_pllv3_unprepare,
	.enable		= clk_pllv3_enable,
	.disable	= clk_pllv3_disable,
	.recalc_rate	= clk_pllv3_sys_recalc_rate,
	.round_rate	= clk_pllv3_sys_round_rate,
	.set_rate	= clk_pllv3_sys_set_rate,
};

static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
					      unsigned long parent_rate)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);
	u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);
	u32 div = readl_relaxed(pll->base) & pll->div_mask;

	return (parent_rate * div) + ((parent_rate / mfd) * mfn);
}

static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
				    unsigned long *prate)
{
	unsigned long parent_rate = *prate;
	unsigned long min_rate = parent_rate * 27;
	unsigned long max_rate = parent_rate * 54;
	u32 div;
	u32 mfn, mfd = 1000000;
	s64 temp64;

	if (rate > max_rate)
		rate = max_rate;
	else if (rate < min_rate)
		rate = min_rate;

	div = rate / parent_rate;
	temp64 = (u64) (rate - div * parent_rate);
	temp64 *= mfd;
	do_div(temp64, parent_rate);
	mfn = temp64;

	return parent_rate * div + parent_rate / mfd * mfn;
}

static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
{
	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	unsigned long min_rate = parent_rate * 27;
	unsigned long max_rate = parent_rate * 54;
	u32 val, div;
	u32 mfn, mfd = 1000000;
	s64 temp64;

	if (rate < min_rate || rate > max_rate)
		return -EINVAL;

	div = rate / parent_rate;
	temp64 = (u64) (rate - div * parent_rate);
	temp64 *= mfd;
	do_div(temp64, parent_rate);
	mfn = temp64;

	val = readl_relaxed(pll->base);
	val &= ~pll->div_mask;
	val |= div;
	writel_relaxed(val, pll->base);
	writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
	writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);

	return clk_pllv3_wait_lock(pll);
}

static const struct clk_ops clk_pllv3_av_ops = {
	.prepare	= clk_pllv3_prepare,
	.unprepare	= clk_pllv3_unprepare,
	.enable		= clk_pllv3_enable,
	.disable	= clk_pllv3_disable,
	.recalc_rate	= clk_pllv3_av_recalc_rate,
	.round_rate	= clk_pllv3_av_round_rate,
	.set_rate	= clk_pllv3_av_set_rate,
};

static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
						unsigned long parent_rate)
{
	return 500000000;
}

static const struct clk_ops clk_pllv3_enet_ops = {
	.prepare	= clk_pllv3_prepare,
	.unprepare	= clk_pllv3_unprepare,
	.enable		= clk_pllv3_enable,
	.disable	= clk_pllv3_disable,
	.recalc_rate	= clk_pllv3_enet_recalc_rate,
};

struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
			  const char *parent_name, void __iomem *base,
			  u32 div_mask)
{
	struct clk_pllv3 *pll;
	const struct clk_ops *ops;
	struct clk *clk;
	struct clk_init_data init;

	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
	if (!pll)
		return ERR_PTR(-ENOMEM);

	switch (type) {
	case IMX_PLLV3_SYS:
		ops = &clk_pllv3_sys_ops;
		break;
	case IMX_PLLV3_USB:
		ops = &clk_pllv3_ops;
		pll->powerup_set = true;
		break;
	case IMX_PLLV3_AV:
		ops = &clk_pllv3_av_ops;
		break;
	case IMX_PLLV3_ENET:
		ops = &clk_pllv3_enet_ops;
		break;
	default:
		ops = &clk_pllv3_ops;
	}
	pll->base = base;
	pll->div_mask = div_mask;

	init.name = name;
	init.ops = ops;
	init.flags = 0;
	init.parent_names = &parent_name;
	init.num_parents = 1;

	pll->hw.init = &init;

	clk = clk_register(NULL, &pll->hw);
	if (IS_ERR(clk))
		kfree(pll);

	return clk;
}
Commit	Line	Data
a3f6b9db SG	1	/*
	2	* Copyright 2012 Freescale Semiconductor, Inc.
	3	* Copyright 2012 Linaro Ltd.
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
	13	#include <linux/clk.h>
	14	#include <linux/clk-provider.h>
322503a1	15	#include <linux/delay.h>
a3f6b9db SG	16	#include <linux/io.h>
	17	#include <linux/slab.h>
	18	#include <linux/jiffies.h>
	19	#include <linux/err.h>
	20	#include "clk.h"
	21
	22	#define PLL_NUM_OFFSET 0x10
	23	#define PLL_DENOM_OFFSET 0x20
	24
	25	#define BM_PLL_POWER (0x1 << 12)
	26	#define BM_PLL_ENABLE (0x1 << 13)
	27	#define BM_PLL_BYPASS (0x1 << 16)
	28	#define BM_PLL_LOCK (0x1 << 31)
	29
	30	/**
	31	* struct clk_pllv3 - IMX PLL clock version 3
	32	* @clk_hw: clock source
	33	* @base: base address of PLL registers
	34	* @powerup_set: set POWER bit to power up the PLL
a3f6b9db SG	35	* @div_mask: mask of divider bits
	36	*
	37	* IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3
	38	* is actually a multiplier, and always sits at bit 0.
	39	*/
	40	struct clk_pllv3 {
	41	struct clk_hw hw;
	42	void __iomem *base;
	43	bool powerup_set;
a3f6b9db SG	44	u32 div_mask;
	45	};
	46
	47	#define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
	48
bc3b84da	49	static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
a3f6b9db	50	{
bc3b84da SG	51	unsigned long timeout = jiffies + msecs_to_jiffies(10);
bc3b84da SG	52	u32 val = readl_relaxed(pll->base) & BM_PLL_POWER;
a3f6b9db	53
bc3b84da SG	54	/* No need to wait for lock when pll is not powered up */
	55	if ((pll->powerup_set && !val) \|\| (!pll->powerup_set && val))
	56	return 0;
a3f6b9db SG	57
a3f6b9db SG	58	/* Wait for PLL to lock */
0a036388 PC	59	do {
	60	if (readl_relaxed(pll->base) & BM_PLL_LOCK)
	61	break;
a3f6b9db	62	if (time_after(jiffies, timeout))
0a036388	63	break;
322503a1	64	usleep_range(50, 500);
0a036388	65	} while (1);
a3f6b9db	66
bc3b84da SG	67	return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT;
	68	}
	69
	70	static int clk_pllv3_prepare(struct clk_hw *hw)
	71	{
	72	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	73	u32 val;
	74
	75	val = readl_relaxed(pll->base);
	76	val &= ~BM_PLL_BYPASS;
	77	if (pll->powerup_set)
	78	val \|= BM_PLL_POWER;
0a036388	79	else
bc3b84da SG	80	val &= ~BM_PLL_POWER;
	81	writel_relaxed(val, pll->base);
	82
	83	return clk_pllv3_wait_lock(pll);
a3f6b9db SG	84	}
	85
	86	static void clk_pllv3_unprepare(struct clk_hw *hw)
	87	{
	88	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	89	u32 val;
	90
	91	val = readl_relaxed(pll->base);
	92	val \|= BM_PLL_BYPASS;
	93	if (pll->powerup_set)
	94	val &= ~BM_PLL_POWER;
	95	else
	96	val \|= BM_PLL_POWER;
	97	writel_relaxed(val, pll->base);
	98	}
	99
	100	static int clk_pllv3_enable(struct clk_hw *hw)
	101	{
	102	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	103	u32 val;
	104
	105	val = readl_relaxed(pll->base);
2b254693	106	val \|= BM_PLL_ENABLE;
a3f6b9db SG	107	writel_relaxed(val, pll->base);
	108
	109	return 0;
	110	}
	111
	112	static void clk_pllv3_disable(struct clk_hw *hw)
	113	{
	114	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	115	u32 val;
	116
	117	val = readl_relaxed(pll->base);
2b254693	118	val &= ~BM_PLL_ENABLE;
a3f6b9db SG	119	writel_relaxed(val, pll->base);
	120	}
	121
	122	static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
	123	unsigned long parent_rate)
	124	{
	125	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	126	u32 div = readl_relaxed(pll->base) & pll->div_mask;
	127
	128	return (div == 1) ? parent_rate * 22 : parent_rate * 20;
	129	}
	130
	131	static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate,
	132	unsigned long *prate)
	133	{
	134	unsigned long parent_rate = *prate;
	135
	136	return (rate >= parent_rate * 22) ? parent_rate * 22 :
	137	parent_rate * 20;
	138	}
	139
	140	static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
	141	unsigned long parent_rate)
	142	{
	143	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	144	u32 val, div;
	145
	146	if (rate == parent_rate * 22)
	147	div = 1;
	148	else if (rate == parent_rate * 20)
	149	div = 0;
	150	else
	151	return -EINVAL;
	152
	153	val = readl_relaxed(pll->base);
	154	val &= ~pll->div_mask;
	155	val \|= div;
	156	writel_relaxed(val, pll->base);
	157
bc3b84da	158	return clk_pllv3_wait_lock(pll);
a3f6b9db SG	159	}
	160
	161	static const struct clk_ops clk_pllv3_ops = {
	162	.prepare = clk_pllv3_prepare,
	163	.unprepare = clk_pllv3_unprepare,
	164	.enable = clk_pllv3_enable,
	165	.disable = clk_pllv3_disable,
	166	.recalc_rate = clk_pllv3_recalc_rate,
	167	.round_rate = clk_pllv3_round_rate,
	168	.set_rate = clk_pllv3_set_rate,
	169	};
	170
	171	static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw,
	172	unsigned long parent_rate)
	173	{
	174	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	175	u32 div = readl_relaxed(pll->base) & pll->div_mask;
	176
	177	return parent_rate * div / 2;
	178	}
	179
	180	static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate,
	181	unsigned long *prate)
	182	{
	183	unsigned long parent_rate = *prate;
	184	unsigned long min_rate = parent_rate * 54 / 2;
	185	unsigned long max_rate = parent_rate * 108 / 2;
	186	u32 div;
	187
	188	if (rate > max_rate)
	189	rate = max_rate;
	190	else if (rate < min_rate)
	191	rate = min_rate;
	192	div = rate * 2 / parent_rate;
	193
	194	return parent_rate * div / 2;
	195	}
	196
	197	static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
	198	unsigned long parent_rate)
	199	{
	200	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	201	unsigned long min_rate = parent_rate * 54 / 2;
	202	unsigned long max_rate = parent_rate * 108 / 2;
	203	u32 val, div;
	204
	205	if (rate < min_rate \|\| rate > max_rate)
	206	return -EINVAL;
	207
	208	div = rate * 2 / parent_rate;
	209	val = readl_relaxed(pll->base);
	210	val &= ~pll->div_mask;
	211	val \|= div;
	212	writel_relaxed(val, pll->base);
	213
bc3b84da	214	return clk_pllv3_wait_lock(pll);
a3f6b9db SG	215	}
	216
	217	static const struct clk_ops clk_pllv3_sys_ops = {
	218	.prepare = clk_pllv3_prepare,
	219	.unprepare = clk_pllv3_unprepare,
	220	.enable = clk_pllv3_enable,
	221	.disable = clk_pllv3_disable,
	222	.recalc_rate = clk_pllv3_sys_recalc_rate,
	223	.round_rate = clk_pllv3_sys_round_rate,
	224	.set_rate = clk_pllv3_sys_set_rate,
	225	};
	226
	227	static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
	228	unsigned long parent_rate)
	229	{
	230	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	231	u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);
	232	u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);
	233	u32 div = readl_relaxed(pll->base) & pll->div_mask;
	234
	235	return (parent_rate * div) + ((parent_rate / mfd) * mfn);
	236	}
	237
	238	static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
	239	unsigned long *prate)
	240	{
	241	unsigned long parent_rate = *prate;
	242	unsigned long min_rate = parent_rate * 27;
	243	unsigned long max_rate = parent_rate * 54;
	244	u32 div;
	245	u32 mfn, mfd = 1000000;
	246	s64 temp64;
	247
	248	if (rate > max_rate)
	249	rate = max_rate;
	250	else if (rate < min_rate)
	251	rate = min_rate;
	252
	253	div = rate / parent_rate;
	254	temp64 = (u64) (rate - div * parent_rate);
	255	temp64 *= mfd;
	256	do_div(temp64, parent_rate);
	257	mfn = temp64;
	258
	259	return parent_rate * div + parent_rate / mfd * mfn;
	260	}
	261
	262	static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
	263	unsigned long parent_rate)
	264	{
	265	struct clk_pllv3 *pll = to_clk_pllv3(hw);
	266	unsigned long min_rate = parent_rate * 27;
	267	unsigned long max_rate = parent_rate * 54;
	268	u32 val, div;
	269	u32 mfn, mfd = 1000000;
	270	s64 temp64;
	271
	272	if (rate < min_rate \|\| rate > max_rate)
	273	return -EINVAL;
	274
	275	div = rate / parent_rate;
	276	temp64 = (u64) (rate - div * parent_rate);
	277	temp64 *= mfd;
	278	do_div(temp64, parent_rate);
279	mfn = temp64;
280
281	val = readl_relaxed(pll->base);
282	val &= ~pll->div_mask;
283	val \|= div;
284	writel_relaxed(val, pll->base);
285	writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
286	writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);
287
bc3b84da	288	return clk_pllv3_wait_lock(pll);
a3f6b9db SG	289	}
	290
	291	static const struct clk_ops clk_pllv3_av_ops = {
	292	.prepare = clk_pllv3_prepare,
	293	.unprepare = clk_pllv3_unprepare,
	294	.enable = clk_pllv3_enable,
	295	.disable = clk_pllv3_disable,
	296	.recalc_rate = clk_pllv3_av_recalc_rate,
	297	.round_rate = clk_pllv3_av_round_rate,
	298	.set_rate = clk_pllv3_av_set_rate,
	299	};
	300
	301	static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
	302	unsigned long parent_rate)
	303	{
7a04092c	304	return 500000000;
a3f6b9db SG	305	}
	306
	307	static const struct clk_ops clk_pllv3_enet_ops = {
	308	.prepare = clk_pllv3_prepare,
	309	.unprepare = clk_pllv3_unprepare,
	310	.enable = clk_pllv3_enable,
	311	.disable = clk_pllv3_disable,
	312	.recalc_rate = clk_pllv3_enet_recalc_rate,
a3f6b9db SG	313	};
a3f6b9db SG	314
a3f6b9db SG	315	struct clk imx_clk_pllv3(enum imx_pllv3_type type, const char name,
a3f6b9db SG	316	const char parent_name, void __iomem base,
2b254693	317	u32 div_mask)
a3f6b9db SG	318	{
	319	struct clk_pllv3 *pll;
	320	const struct clk_ops *ops;
	321	struct clk *clk;
	322	struct clk_init_data init;
	323
	324	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
	325	if (!pll)
	326	return ERR_PTR(-ENOMEM);
	327
	328	switch (type) {
	329	case IMX_PLLV3_SYS:
	330	ops = &clk_pllv3_sys_ops;
	331	break;
	332	case IMX_PLLV3_USB:
	333	ops = &clk_pllv3_ops;
	334	pll->powerup_set = true;
	335	break;
	336	case IMX_PLLV3_AV:
	337	ops = &clk_pllv3_av_ops;
	338	break;
	339	case IMX_PLLV3_ENET:
	340	ops = &clk_pllv3_enet_ops;
	341	break;
a3f6b9db SG	342	default:
	343	ops = &clk_pllv3_ops;
	344	}
	345	pll->base = base;
a3f6b9db SG	346	pll->div_mask = div_mask;
	347
	348	init.name = name;
	349	init.ops = ops;
	350	init.flags = 0;
	351	init.parent_names = &parent_name;
	352	init.num_parents = 1;
	353
	354	pll->hw.init = &init;
	355
	356	clk = clk_register(NULL, &pll->hw);
	357	if (IS_ERR(clk))
	358	kfree(pll);
	359
	360	return clk;
	361	}