Commit | Line | Data |
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6c7b0685 SH |
1 | #ifndef __MACH_IMX_CLK_H |
2 | #define __MACH_IMX_CLK_H | |
3 | ||
4 | #include <linux/spinlock.h> | |
5 | #include <linux/clk-provider.h> | |
3a84d17b SH |
6 | |
7 | extern spinlock_t imx_ccm_lock; | |
6c7b0685 | 8 | |
dfd87144 LY |
9 | extern void imx_cscmr1_fixup(u32 *val); |
10 | ||
2af9e6db | 11 | struct clk *imx_clk_pllv1(const char *name, const char *parent, |
6c7b0685 SH |
12 | void __iomem *base); |
13 | ||
a547b816 SH |
14 | struct clk *imx_clk_pllv2(const char *name, const char *parent, |
15 | void __iomem *base); | |
16 | ||
a3f6b9db SG |
17 | enum imx_pllv3_type { |
18 | IMX_PLLV3_GENERIC, | |
19 | IMX_PLLV3_SYS, | |
20 | IMX_PLLV3_USB, | |
21 | IMX_PLLV3_AV, | |
22 | IMX_PLLV3_ENET, | |
a3f6b9db SG |
23 | }; |
24 | ||
25 | struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, | |
2b254693 | 26 | const char *parent_name, void __iomem *base, u32 div_mask); |
a3f6b9db | 27 | |
b75c0151 SH |
28 | struct clk *clk_register_gate2(struct device *dev, const char *name, |
29 | const char *parent_name, unsigned long flags, | |
30 | void __iomem *reg, u8 bit_idx, | |
31 | u8 clk_gate_flags, spinlock_t *lock); | |
32 | ||
75f83d06 MF |
33 | struct clk * imx_obtain_fixed_clock( |
34 | const char *name, unsigned long rate); | |
35 | ||
b75c0151 SH |
36 | static inline struct clk *imx_clk_gate2(const char *name, const char *parent, |
37 | void __iomem *reg, u8 shift) | |
38 | { | |
39 | return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, | |
40 | shift, 0, &imx_ccm_lock); | |
41 | } | |
42 | ||
a10bd67f SG |
43 | struct clk *imx_clk_pfd(const char *name, const char *parent_name, |
44 | void __iomem *reg, u8 idx); | |
45 | ||
32af7a83 SG |
46 | struct clk *imx_clk_busy_divider(const char *name, const char *parent_name, |
47 | void __iomem *reg, u8 shift, u8 width, | |
48 | void __iomem *busy_reg, u8 busy_shift); | |
49 | ||
50 | struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, | |
51 | u8 width, void __iomem *busy_reg, u8 busy_shift, | |
52 | const char **parent_names, int num_parents); | |
53 | ||
cbe7fc8a LY |
54 | struct clk *imx_clk_fixup_divider(const char *name, const char *parent, |
55 | void __iomem *reg, u8 shift, u8 width, | |
56 | void (*fixup)(u32 *val)); | |
57 | ||
a49e6c4b LY |
58 | struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg, |
59 | u8 shift, u8 width, const char **parents, | |
60 | int num_parents, void (*fixup)(u32 *val)); | |
61 | ||
6c7b0685 SH |
62 | static inline struct clk *imx_clk_fixed(const char *name, int rate) |
63 | { | |
64 | return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate); | |
65 | } | |
66 | ||
67 | static inline struct clk *imx_clk_divider(const char *name, const char *parent, | |
68 | void __iomem *reg, u8 shift, u8 width) | |
69 | { | |
70 | return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT, | |
71 | reg, shift, width, 0, &imx_ccm_lock); | |
72 | } | |
73 | ||
3ce92170 PZ |
74 | static inline struct clk *imx_clk_divider_flags(const char *name, |
75 | const char *parent, void __iomem *reg, u8 shift, u8 width, | |
76 | unsigned long flags) | |
77 | { | |
78 | return clk_register_divider(NULL, name, parent, flags, | |
79 | reg, shift, width, 0, &imx_ccm_lock); | |
80 | } | |
81 | ||
6c7b0685 SH |
82 | static inline struct clk *imx_clk_gate(const char *name, const char *parent, |
83 | void __iomem *reg, u8 shift) | |
84 | { | |
85 | return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, | |
86 | shift, 0, &imx_ccm_lock); | |
87 | } | |
88 | ||
89 | static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, | |
90 | u8 shift, u8 width, const char **parents, int num_parents) | |
91 | { | |
819c1de3 JH |
92 | return clk_register_mux(NULL, name, parents, num_parents, |
93 | CLK_SET_RATE_NO_REPARENT, reg, shift, | |
6c7b0685 SH |
94 | width, 0, &imx_ccm_lock); |
95 | } | |
96 | ||
3ce92170 PZ |
97 | static inline struct clk *imx_clk_mux_flags(const char *name, |
98 | void __iomem *reg, u8 shift, u8 width, const char **parents, | |
99 | int num_parents, unsigned long flags) | |
100 | { | |
101 | return clk_register_mux(NULL, name, parents, num_parents, | |
819c1de3 | 102 | flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0, |
3ce92170 PZ |
103 | &imx_ccm_lock); |
104 | } | |
105 | ||
6c7b0685 SH |
106 | static inline struct clk *imx_clk_fixed_factor(const char *name, |
107 | const char *parent, unsigned int mult, unsigned int div) | |
108 | { | |
109 | return clk_register_fixed_factor(NULL, name, parent, | |
110 | CLK_SET_RATE_PARENT, mult, div); | |
111 | } | |
112 | ||
113 | #endif |