ARM: i.MX6: call ksz9021 phy fixup for all i.MX6 boards
[deliverable/linux.git] / arch / arm / mach-imx / clk.h
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1#ifndef __MACH_IMX_CLK_H
2#define __MACH_IMX_CLK_H
3
4#include <linux/spinlock.h>
5#include <linux/clk-provider.h>
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6
7extern spinlock_t imx_ccm_lock;
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2af9e6db 9struct clk *imx_clk_pllv1(const char *name, const char *parent,
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10 void __iomem *base);
11
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12struct clk *imx_clk_pllv2(const char *name, const char *parent,
13 void __iomem *base);
14
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15enum imx_pllv3_type {
16 IMX_PLLV3_GENERIC,
17 IMX_PLLV3_SYS,
18 IMX_PLLV3_USB,
19 IMX_PLLV3_AV,
20 IMX_PLLV3_ENET,
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21};
22
23struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
2b254693 24 const char *parent_name, void __iomem *base, u32 div_mask);
a3f6b9db 25
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26struct clk *clk_register_gate2(struct device *dev, const char *name,
27 const char *parent_name, unsigned long flags,
28 void __iomem *reg, u8 bit_idx,
29 u8 clk_gate_flags, spinlock_t *lock);
30
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31struct clk * imx_obtain_fixed_clock(
32 const char *name, unsigned long rate);
33
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34static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
35 void __iomem *reg, u8 shift)
36{
37 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
38 shift, 0, &imx_ccm_lock);
39}
40
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41struct clk *imx_clk_pfd(const char *name, const char *parent_name,
42 void __iomem *reg, u8 idx);
43
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44struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
45 void __iomem *reg, u8 shift, u8 width,
46 void __iomem *busy_reg, u8 busy_shift);
47
48struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
49 u8 width, void __iomem *busy_reg, u8 busy_shift,
50 const char **parent_names, int num_parents);
51
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52static inline struct clk *imx_clk_fixed(const char *name, int rate)
53{
54 return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
55}
56
57static inline struct clk *imx_clk_divider(const char *name, const char *parent,
58 void __iomem *reg, u8 shift, u8 width)
59{
60 return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
61 reg, shift, width, 0, &imx_ccm_lock);
62}
63
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64static inline struct clk *imx_clk_divider_flags(const char *name,
65 const char *parent, void __iomem *reg, u8 shift, u8 width,
66 unsigned long flags)
67{
68 return clk_register_divider(NULL, name, parent, flags,
69 reg, shift, width, 0, &imx_ccm_lock);
70}
71
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72static inline struct clk *imx_clk_gate(const char *name, const char *parent,
73 void __iomem *reg, u8 shift)
74{
75 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
76 shift, 0, &imx_ccm_lock);
77}
78
79static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
80 u8 shift, u8 width, const char **parents, int num_parents)
81{
82 return clk_register_mux(NULL, name, parents, num_parents, 0, reg, shift,
83 width, 0, &imx_ccm_lock);
84}
85
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86static inline struct clk *imx_clk_mux_flags(const char *name,
87 void __iomem *reg, u8 shift, u8 width, const char **parents,
88 int num_parents, unsigned long flags)
89{
90 return clk_register_mux(NULL, name, parents, num_parents,
91 flags, reg, shift, width, 0,
92 &imx_ccm_lock);
93}
94
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95static inline struct clk *imx_clk_fixed_factor(const char *name,
96 const char *parent, unsigned int mult, unsigned int div)
97{
98 return clk_register_fixed_factor(NULL, name, parent,
99 CLK_SET_RATE_PARENT, mult, div);
100}
101
102#endif
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