Commit | Line | Data |
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6c7b0685 SH |
1 | #ifndef __MACH_IMX_CLK_H |
2 | #define __MACH_IMX_CLK_H | |
3 | ||
4 | #include <linux/spinlock.h> | |
5 | #include <linux/clk-provider.h> | |
3a84d17b SH |
6 | |
7 | extern spinlock_t imx_ccm_lock; | |
6c7b0685 | 8 | |
dfd87144 LY |
9 | extern void imx_cscmr1_fixup(u32 *val); |
10 | ||
2af9e6db | 11 | struct clk *imx_clk_pllv1(const char *name, const char *parent, |
6c7b0685 SH |
12 | void __iomem *base); |
13 | ||
a547b816 SH |
14 | struct clk *imx_clk_pllv2(const char *name, const char *parent, |
15 | void __iomem *base); | |
16 | ||
a3f6b9db SG |
17 | enum imx_pllv3_type { |
18 | IMX_PLLV3_GENERIC, | |
19 | IMX_PLLV3_SYS, | |
20 | IMX_PLLV3_USB, | |
21 | IMX_PLLV3_AV, | |
22 | IMX_PLLV3_ENET, | |
a3f6b9db SG |
23 | }; |
24 | ||
25 | struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, | |
2b254693 | 26 | const char *parent_name, void __iomem *base, u32 div_mask); |
a3f6b9db | 27 | |
b75c0151 SH |
28 | struct clk *clk_register_gate2(struct device *dev, const char *name, |
29 | const char *parent_name, unsigned long flags, | |
30 | void __iomem *reg, u8 bit_idx, | |
f9f28cdf SG |
31 | u8 clk_gate_flags, spinlock_t *lock, |
32 | unsigned int *share_count); | |
b75c0151 | 33 | |
75f83d06 MF |
34 | struct clk * imx_obtain_fixed_clock( |
35 | const char *name, unsigned long rate); | |
36 | ||
b75c0151 SH |
37 | static inline struct clk *imx_clk_gate2(const char *name, const char *parent, |
38 | void __iomem *reg, u8 shift) | |
39 | { | |
40 | return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, | |
f9f28cdf SG |
41 | shift, 0, &imx_ccm_lock, NULL); |
42 | } | |
43 | ||
44 | static inline struct clk *imx_clk_gate2_shared(const char *name, | |
45 | const char *parent, void __iomem *reg, u8 shift, | |
46 | unsigned int *share_count) | |
47 | { | |
48 | return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, | |
49 | shift, 0, &imx_ccm_lock, share_count); | |
b75c0151 SH |
50 | } |
51 | ||
a10bd67f SG |
52 | struct clk *imx_clk_pfd(const char *name, const char *parent_name, |
53 | void __iomem *reg, u8 idx); | |
54 | ||
32af7a83 SG |
55 | struct clk *imx_clk_busy_divider(const char *name, const char *parent_name, |
56 | void __iomem *reg, u8 shift, u8 width, | |
57 | void __iomem *busy_reg, u8 busy_shift); | |
58 | ||
59 | struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, | |
60 | u8 width, void __iomem *busy_reg, u8 busy_shift, | |
61 | const char **parent_names, int num_parents); | |
62 | ||
cbe7fc8a LY |
63 | struct clk *imx_clk_fixup_divider(const char *name, const char *parent, |
64 | void __iomem *reg, u8 shift, u8 width, | |
65 | void (*fixup)(u32 *val)); | |
66 | ||
a49e6c4b LY |
67 | struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg, |
68 | u8 shift, u8 width, const char **parents, | |
69 | int num_parents, void (*fixup)(u32 *val)); | |
70 | ||
6c7b0685 SH |
71 | static inline struct clk *imx_clk_fixed(const char *name, int rate) |
72 | { | |
73 | return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate); | |
74 | } | |
75 | ||
76 | static inline struct clk *imx_clk_divider(const char *name, const char *parent, | |
77 | void __iomem *reg, u8 shift, u8 width) | |
78 | { | |
79 | return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT, | |
80 | reg, shift, width, 0, &imx_ccm_lock); | |
81 | } | |
82 | ||
3ce92170 PZ |
83 | static inline struct clk *imx_clk_divider_flags(const char *name, |
84 | const char *parent, void __iomem *reg, u8 shift, u8 width, | |
85 | unsigned long flags) | |
86 | { | |
87 | return clk_register_divider(NULL, name, parent, flags, | |
88 | reg, shift, width, 0, &imx_ccm_lock); | |
89 | } | |
90 | ||
6c7b0685 SH |
91 | static inline struct clk *imx_clk_gate(const char *name, const char *parent, |
92 | void __iomem *reg, u8 shift) | |
93 | { | |
94 | return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, | |
95 | shift, 0, &imx_ccm_lock); | |
96 | } | |
97 | ||
98 | static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, | |
99 | u8 shift, u8 width, const char **parents, int num_parents) | |
100 | { | |
819c1de3 JH |
101 | return clk_register_mux(NULL, name, parents, num_parents, |
102 | CLK_SET_RATE_NO_REPARENT, reg, shift, | |
6c7b0685 SH |
103 | width, 0, &imx_ccm_lock); |
104 | } | |
105 | ||
3ce92170 PZ |
106 | static inline struct clk *imx_clk_mux_flags(const char *name, |
107 | void __iomem *reg, u8 shift, u8 width, const char **parents, | |
108 | int num_parents, unsigned long flags) | |
109 | { | |
110 | return clk_register_mux(NULL, name, parents, num_parents, | |
819c1de3 | 111 | flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0, |
3ce92170 PZ |
112 | &imx_ccm_lock); |
113 | } | |
114 | ||
6c7b0685 SH |
115 | static inline struct clk *imx_clk_fixed_factor(const char *name, |
116 | const char *parent, unsigned int mult, unsigned int div) | |
117 | { | |
118 | return clk_register_fixed_factor(NULL, name, parent, | |
119 | CLK_SET_RATE_PARENT, mult, div); | |
120 | } | |
121 | ||
122 | #endif |