ARM: imx: add clk-pllv1 type support
[deliverable/linux.git] / arch / arm / mach-imx / clk.h
CommitLineData
6c7b0685
SH
1#ifndef __MACH_IMX_CLK_H
2#define __MACH_IMX_CLK_H
3
4#include <linux/spinlock.h>
5#include <linux/clk-provider.h>
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SH
6
7extern spinlock_t imx_ccm_lock;
6c7b0685 8
229be9c1
AS
9void imx_check_clocks(struct clk *clks[], unsigned int count);
10
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LY
11extern void imx_cscmr1_fixup(u32 *val);
12
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SG
13enum imx_pllv1_type {
14 IMX_PLLV1_IMX1,
15 IMX_PLLV1_IMX21,
16 IMX_PLLV1_IMX25,
17 IMX_PLLV1_IMX27,
18 IMX_PLLV1_IMX31,
19 IMX_PLLV1_IMX35,
20};
21
22struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name,
23 const char *parent, void __iomem *base);
6c7b0685 24
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SH
25struct clk *imx_clk_pllv2(const char *name, const char *parent,
26 void __iomem *base);
27
a3f6b9db
SG
28enum imx_pllv3_type {
29 IMX_PLLV3_GENERIC,
30 IMX_PLLV3_SYS,
31 IMX_PLLV3_USB,
60ad8467 32 IMX_PLLV3_USB_VF610,
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SG
33 IMX_PLLV3_AV,
34 IMX_PLLV3_ENET,
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SG
35};
36
37struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
2b254693 38 const char *parent_name, void __iomem *base, u32 div_mask);
a3f6b9db 39
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SH
40struct clk *clk_register_gate2(struct device *dev, const char *name,
41 const char *parent_name, unsigned long flags,
42 void __iomem *reg, u8 bit_idx,
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SG
43 u8 clk_gate_flags, spinlock_t *lock,
44 unsigned int *share_count);
b75c0151 45
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MF
46struct clk * imx_obtain_fixed_clock(
47 const char *name, unsigned long rate);
48
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SG
49struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
50 void __iomem *reg, u8 shift, u32 exclusive_mask);
51
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SH
52static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
53 void __iomem *reg, u8 shift)
54{
55 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
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SG
56 shift, 0, &imx_ccm_lock, NULL);
57}
58
59static inline struct clk *imx_clk_gate2_shared(const char *name,
60 const char *parent, void __iomem *reg, u8 shift,
61 unsigned int *share_count)
62{
63 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
64 shift, 0, &imx_ccm_lock, share_count);
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SH
65}
66
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SG
67struct clk *imx_clk_pfd(const char *name, const char *parent_name,
68 void __iomem *reg, u8 idx);
69
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SG
70struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
71 void __iomem *reg, u8 shift, u8 width,
72 void __iomem *busy_reg, u8 busy_shift);
73
74struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
75 u8 width, void __iomem *busy_reg, u8 busy_shift,
76 const char **parent_names, int num_parents);
77
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78struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
79 void __iomem *reg, u8 shift, u8 width,
80 void (*fixup)(u32 *val));
81
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LY
82struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
83 u8 shift, u8 width, const char **parents,
84 int num_parents, void (*fixup)(u32 *val));
85
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SH
86static inline struct clk *imx_clk_fixed(const char *name, int rate)
87{
88 return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
89}
90
91static inline struct clk *imx_clk_divider(const char *name, const char *parent,
92 void __iomem *reg, u8 shift, u8 width)
93{
94 return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
95 reg, shift, width, 0, &imx_ccm_lock);
96}
97
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98static inline struct clk *imx_clk_divider_flags(const char *name,
99 const char *parent, void __iomem *reg, u8 shift, u8 width,
100 unsigned long flags)
101{
102 return clk_register_divider(NULL, name, parent, flags,
103 reg, shift, width, 0, &imx_ccm_lock);
104}
105
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SH
106static inline struct clk *imx_clk_gate(const char *name, const char *parent,
107 void __iomem *reg, u8 shift)
108{
109 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
110 shift, 0, &imx_ccm_lock);
111}
112
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AS
113static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent,
114 void __iomem *reg, u8 shift)
115{
116 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
117 shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock);
118}
119
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SH
120static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
121 u8 shift, u8 width, const char **parents, int num_parents)
122{
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JH
123 return clk_register_mux(NULL, name, parents, num_parents,
124 CLK_SET_RATE_NO_REPARENT, reg, shift,
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125 width, 0, &imx_ccm_lock);
126}
127
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128static inline struct clk *imx_clk_mux_flags(const char *name,
129 void __iomem *reg, u8 shift, u8 width, const char **parents,
130 int num_parents, unsigned long flags)
131{
132 return clk_register_mux(NULL, name, parents, num_parents,
819c1de3 133 flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0,
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134 &imx_ccm_lock);
135}
136
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SH
137static inline struct clk *imx_clk_fixed_factor(const char *name,
138 const char *parent, unsigned int mult, unsigned int div)
139{
140 return clk_register_fixed_factor(NULL, name, parent,
141 CLK_SET_RATE_PARENT, mult, div);
142}
143
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LS
144struct clk *imx_clk_cpu(const char *name, const char *parent_name,
145 struct clk *div, struct clk *mux, struct clk *pll,
146 struct clk *step);
147
6c7b0685 148#endif
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