Commit | Line | Data |
---|---|---|
52c543f9 | 1 | /* |
df595746 | 2 | * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved. |
52c543f9 QJ |
3 | */ |
4 | ||
5 | /* | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #ifndef __ASM_ARCH_MXC_COMMON_H__ | |
12 | #define __ASM_ARCH_MXC_COMMON_H__ | |
13 | ||
7b6d864b RH |
14 | #include <linux/reboot.h> |
15 | ||
d48866fe | 16 | struct irq_data; |
282b13d0 | 17 | struct platform_device; |
009e63f8 | 18 | struct pt_regs; |
30c730f8 | 19 | struct clk; |
876292d6 | 20 | struct device_node; |
a1f1c7ef | 21 | enum mxc_cpu_pwr_mode; |
e57e4ab5 | 22 | struct of_device_id; |
282b13d0 | 23 | |
803648db SG |
24 | void mx1_map_io(void); |
25 | void mx21_map_io(void); | |
803648db SG |
26 | void mx27_map_io(void); |
27 | void mx31_map_io(void); | |
28 | void mx35_map_io(void); | |
803648db SG |
29 | void imx1_init_early(void); |
30 | void imx21_init_early(void); | |
803648db SG |
31 | void imx27_init_early(void); |
32 | void imx31_init_early(void); | |
33 | void imx35_init_early(void); | |
803648db | 34 | void mxc_init_irq(void __iomem *); |
fffa0512 | 35 | void tzic_init_irq(void); |
803648db SG |
36 | void mx1_init_irq(void); |
37 | void mx21_init_irq(void); | |
803648db SG |
38 | void mx27_init_irq(void); |
39 | void mx31_init_irq(void); | |
40 | void mx35_init_irq(void); | |
803648db SG |
41 | void imx1_soc_init(void); |
42 | void imx21_soc_init(void); | |
803648db SG |
43 | void imx27_soc_init(void); |
44 | void imx31_soc_init(void); | |
45 | void imx35_soc_init(void); | |
803648db | 46 | void epit_timer_init(void __iomem *base, int irq); |
803648db SG |
47 | int mx1_clocks_init(unsigned long fref); |
48 | int mx21_clocks_init(unsigned long lref, unsigned long fref); | |
803648db SG |
49 | int mx27_clocks_init(unsigned long fref); |
50 | int mx31_clocks_init(unsigned long fref); | |
51 | int mx35_clocks_init(void); | |
803648db SG |
52 | int mx31_clocks_init_dt(void); |
53 | struct platform_device *mxc_register_gpio(char *name, int id, | |
b78d8e59 | 54 | resource_size_t iobase, resource_size_t iosize, int irq, int irq_high); |
803648db SG |
55 | void mxc_set_cpu_type(unsigned int type); |
56 | void mxc_restart(enum reboot_mode, const char *); | |
57 | void mxc_arch_reset_init(void __iomem *); | |
803648db | 58 | void imx_set_aips(void __iomem *); |
e57e4ab5 | 59 | void imx_aips_allow_unprivileged_access(const char *compat); |
803648db | 60 | int mxc_device_init(void); |
bfefdff8 | 61 | void imx_set_soc_revision(unsigned int rev); |
f1c6f314 | 62 | void imx_init_revision_from_anatop(void); |
a2887546 | 63 | struct device *imx_soc_device_init(void); |
05136f08 | 64 | void imx6_enable_rbc(bool enable); |
14517564 | 65 | void imx_gpc_check_dt(void); |
05136f08 AH |
66 | void imx_gpc_set_arm_power_in_lpm(bool power_off); |
67 | void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw); | |
68 | void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw); | |
8c4300c2 | 69 | void imx25_pm_init(void); |
73d2b4cd | 70 | |
41e7daf2 SG |
71 | enum mxc_cpu_pwr_mode { |
72 | WAIT_CLOCKED, /* wfi only */ | |
73 | WAIT_UNCLOCKED, /* WAIT */ | |
74 | WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */ | |
75 | STOP_POWER_ON, /* just STOP */ | |
76 | STOP_POWER_OFF, /* STOP + SRPG */ | |
77 | }; | |
78 | ||
3ac804e3 FE |
79 | enum mx3_cpu_pwr_mode { |
80 | MX3_RUN, | |
81 | MX3_WAIT, | |
82 | MX3_DOZE, | |
83 | MX3_SLEEP, | |
84 | }; | |
85 | ||
803648db | 86 | void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode); |
b6de943b | 87 | |
803648db SG |
88 | void imx_enable_cpu(int cpu, bool enable); |
89 | void imx_set_cpu_jump(int cpu, void *jump_addr); | |
90 | u32 imx_get_cpu_arg(int cpu); | |
91 | void imx_set_cpu_arg(int cpu, u32 arg); | |
69c31b7a | 92 | #ifdef CONFIG_SMP |
803648db SG |
93 | void v7_secondary_startup(void); |
94 | void imx_scu_map_io(void); | |
95 | void imx_smp_prepare(void); | |
13eed989 SG |
96 | #else |
97 | static inline void imx_scu_map_io(void) {} | |
a1f1c7ef | 98 | static inline void imx_smp_prepare(void) {} |
69c31b7a | 99 | #endif |
803648db | 100 | void imx_src_init(void); |
80c0ecdc | 101 | void imx_gpc_pre_suspend(bool arm_power_off); |
803648db SG |
102 | void imx_gpc_post_resume(void); |
103 | void imx_gpc_mask_all(void); | |
104 | void imx_gpc_restore_all(void); | |
65bb688a MZ |
105 | void imx_gpc_hwirq_mask(unsigned int hwirq); |
106 | void imx_gpc_hwirq_unmask(unsigned int hwirq); | |
803648db SG |
107 | void imx_anatop_init(void); |
108 | void imx_anatop_pre_suspend(void); | |
109 | void imx_anatop_post_resume(void); | |
8fb76a07 | 110 | int imx6_set_lpm(enum mxc_cpu_pwr_mode mode); |
dfea953a | 111 | void imx6q_set_int_mem_clk_lpm(bool enable); |
751f7e99 | 112 | void imx6sl_set_wait_clk(bool enter); |
ec336b28 | 113 | int imx_mmdc_get_ddr_type(void); |
803648db SG |
114 | |
115 | void imx_cpu_die(unsigned int cpu); | |
116 | int imx_cpu_kill(unsigned int cpu); | |
e4f2d979 | 117 | |
c356bdb4 SG |
118 | #ifdef CONFIG_SUSPEND |
119 | void v7_cpu_resume(void); | |
1579c7b9 MF |
120 | void imx53_suspend(void __iomem *ocram_vbase); |
121 | extern const u32 imx53_suspend_sz; | |
df595746 | 122 | void imx6_suspend(void __iomem *ocram_vbase); |
c356bdb4 SG |
123 | #else |
124 | static inline void v7_cpu_resume(void) {} | |
1579c7b9 MF |
125 | static inline void imx53_suspend(void __iomem *ocram_vbase) {} |
126 | static const u32 imx53_suspend_sz; | |
c356bdb4 SG |
127 | static inline void imx6_suspend(void __iomem *ocram_vbase) {} |
128 | #endif | |
129 | ||
35e2916f | 130 | void imx6_pm_ccm_init(const char *ccm_compat); |
803648db | 131 | void imx6q_pm_init(void); |
df595746 AH |
132 | void imx6dl_pm_init(void); |
133 | void imx6sl_pm_init(void); | |
ff843d62 | 134 | void imx6sx_pm_init(void); |
ee4a5f83 | 135 | void imx6ul_pm_init(void); |
df595746 | 136 | |
28a9f3b0 | 137 | #ifdef CONFIG_PM |
36b66c3f SG |
138 | void imx51_pm_init(void); |
139 | void imx53_pm_init(void); | |
46ec1b26 | 140 | #else |
36b66c3f SG |
141 | static inline void imx51_pm_init(void) {} |
142 | static inline void imx53_pm_init(void) {} | |
46ec1b26 EM |
143 | #endif |
144 | ||
8321b758 | 145 | #ifdef CONFIG_NEON |
803648db | 146 | int mx51_neon_fixup(void); |
8321b758 SG |
147 | #else |
148 | static inline int mx51_neon_fixup(void) { return 0; } | |
149 | #endif | |
150 | ||
e6a07569 | 151 | #ifdef CONFIG_CACHE_L2X0 |
803648db | 152 | void imx_init_l2cache(void); |
e6a07569 SG |
153 | #else |
154 | static inline void imx_init_l2cache(void) {} | |
155 | #endif | |
156 | ||
75305275 MY |
157 | extern const struct smp_operations imx_smp_ops; |
158 | extern const struct smp_operations ls1021a_smp_ops; | |
e4f2d979 | 159 | |
52c543f9 | 160 | #endif |