Merge tag 'pci-v3.15-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaa...
[deliverable/linux.git] / arch / arm / mach-imx / common.h
CommitLineData
52c543f9 1/*
e95dddb3 2 * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
52c543f9
QJ
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_COMMON_H__
12#define __ASM_ARCH_MXC_COMMON_H__
13
7b6d864b
RH
14#include <linux/reboot.h>
15
d48866fe 16struct irq_data;
282b13d0 17struct platform_device;
009e63f8 18struct pt_regs;
30c730f8 19struct clk;
a1f1c7ef 20enum mxc_cpu_pwr_mode;
282b13d0 21
803648db
SG
22void mx1_map_io(void);
23void mx21_map_io(void);
24void mx25_map_io(void);
25void mx27_map_io(void);
26void mx31_map_io(void);
27void mx35_map_io(void);
28void mx51_map_io(void);
29void mx53_map_io(void);
30void imx1_init_early(void);
31void imx21_init_early(void);
32void imx25_init_early(void);
33void imx27_init_early(void);
34void imx31_init_early(void);
35void imx35_init_early(void);
36void imx51_init_early(void);
37void imx53_init_early(void);
38void mxc_init_irq(void __iomem *);
39void tzic_init_irq(void __iomem *);
40void mx1_init_irq(void);
41void mx21_init_irq(void);
42void mx25_init_irq(void);
43void mx27_init_irq(void);
44void mx31_init_irq(void);
45void mx35_init_irq(void);
46void mx51_init_irq(void);
47void mx53_init_irq(void);
48void imx1_soc_init(void);
49void imx21_soc_init(void);
50void imx25_soc_init(void);
51void imx27_soc_init(void);
52void imx31_soc_init(void);
53void imx35_soc_init(void);
54void imx51_soc_init(void);
55void imx51_init_late(void);
56void imx53_init_late(void);
57void epit_timer_init(void __iomem *base, int irq);
58void mxc_timer_init(void __iomem *, int);
59int mx1_clocks_init(unsigned long fref);
60int mx21_clocks_init(unsigned long lref, unsigned long fref);
61int mx25_clocks_init(void);
62int mx27_clocks_init(unsigned long fref);
63int mx31_clocks_init(unsigned long fref);
64int mx35_clocks_init(void);
65int mx51_clocks_init(unsigned long ckil, unsigned long osc,
a329b48c 66 unsigned long ckih1, unsigned long ckih2);
803648db
SG
67int mx25_clocks_init_dt(void);
68int mx27_clocks_init_dt(void);
69int mx31_clocks_init_dt(void);
70struct platform_device *mxc_register_gpio(char *name, int id,
b78d8e59 71 resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
803648db
SG
72void mxc_set_cpu_type(unsigned int type);
73void mxc_restart(enum reboot_mode, const char *);
74void mxc_arch_reset_init(void __iomem *);
75void mxc_arch_reset_init_dt(void);
76int mx53_revision(void);
77void imx_set_aips(void __iomem *);
78int mxc_device_init(void);
bfefdff8
SG
79void imx_set_soc_revision(unsigned int rev);
80unsigned int imx_get_soc_revision(void);
f1c6f314 81void imx_init_revision_from_anatop(void);
a2887546 82struct device *imx_soc_device_init(void);
73d2b4cd 83
41e7daf2
SG
84enum mxc_cpu_pwr_mode {
85 WAIT_CLOCKED, /* wfi only */
86 WAIT_UNCLOCKED, /* WAIT */
87 WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */
88 STOP_POWER_ON, /* just STOP */
89 STOP_POWER_OFF, /* STOP + SRPG */
90};
91
3ac804e3
FE
92enum mx3_cpu_pwr_mode {
93 MX3_RUN,
94 MX3_WAIT,
95 MX3_DOZE,
96 MX3_SLEEP,
97};
98
803648db
SG
99void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
100void imx_print_silicon_rev(const char *cpu, int srev);
b6de943b
SH
101
102void avic_handle_irq(struct pt_regs *);
58a92600 103void tzic_handle_irq(struct pt_regs *);
b6de943b
SH
104
105#define imx1_handle_irq avic_handle_irq
106#define imx21_handle_irq avic_handle_irq
107#define imx25_handle_irq avic_handle_irq
108#define imx27_handle_irq avic_handle_irq
109#define imx31_handle_irq avic_handle_irq
110#define imx35_handle_irq avic_handle_irq
374daac4 111#define imx50_handle_irq tzic_handle_irq
58a92600
SH
112#define imx51_handle_irq tzic_handle_irq
113#define imx53_handle_irq tzic_handle_irq
b6de943b 114
803648db
SG
115void imx_enable_cpu(int cpu, bool enable);
116void imx_set_cpu_jump(int cpu, void *jump_addr);
117u32 imx_get_cpu_arg(int cpu);
118void imx_set_cpu_arg(int cpu, u32 arg);
119void v7_cpu_resume(void);
69c31b7a 120#ifdef CONFIG_SMP
803648db
SG
121void v7_secondary_startup(void);
122void imx_scu_map_io(void);
123void imx_smp_prepare(void);
124void imx_scu_standby_enable(void);
13eed989
SG
125#else
126static inline void imx_scu_map_io(void) {}
a1f1c7ef 127static inline void imx_smp_prepare(void) {}
e5f9dec8 128static inline void imx_scu_standby_enable(void) {}
69c31b7a 129#endif
803648db 130void imx_src_init(void);
803648db
SG
131void imx_gpc_init(void);
132void imx_gpc_pre_suspend(void);
133void imx_gpc_post_resume(void);
134void imx_gpc_mask_all(void);
135void imx_gpc_restore_all(void);
d48866fe
SG
136void imx_gpc_irq_mask(struct irq_data *d);
137void imx_gpc_irq_unmask(struct irq_data *d);
803648db
SG
138void imx_anatop_init(void);
139void imx_anatop_pre_suspend(void);
140void imx_anatop_post_resume(void);
141int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
142void imx6q_set_chicken_bit(void);
143
144void imx_cpu_die(unsigned int cpu);
145int imx_cpu_kill(unsigned int cpu);
e4f2d979 146
803648db 147void imx6q_pm_init(void);
9e8147bb 148void imx6q_pm_set_ccm_base(void __iomem *base);
28a9f3b0 149#ifdef CONFIG_PM
803648db 150void imx5_pm_init(void);
46ec1b26 151#else
547dd1e0 152static inline void imx5_pm_init(void) {}
46ec1b26
EM
153#endif
154
8321b758 155#ifdef CONFIG_NEON
803648db 156int mx51_neon_fixup(void);
8321b758
SG
157#else
158static inline int mx51_neon_fixup(void) { return 0; }
159#endif
160
e6a07569 161#ifdef CONFIG_CACHE_L2X0
803648db 162void imx_init_l2cache(void);
e6a07569
SG
163#else
164static inline void imx_init_l2cache(void) {}
165#endif
166
e4f2d979
MZ
167extern struct smp_operations imx_smp_ops;
168
52c543f9 169#endif
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