ARM: imx6: let pm code map CCM block on its own
[deliverable/linux.git] / arch / arm / mach-imx / common.h
CommitLineData
52c543f9 1/*
df595746 2 * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
52c543f9
QJ
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_COMMON_H__
12#define __ASM_ARCH_MXC_COMMON_H__
13
7b6d864b
RH
14#include <linux/reboot.h>
15
d48866fe 16struct irq_data;
282b13d0 17struct platform_device;
009e63f8 18struct pt_regs;
30c730f8 19struct clk;
876292d6 20struct device_node;
a1f1c7ef 21enum mxc_cpu_pwr_mode;
e57e4ab5 22struct of_device_id;
282b13d0 23
803648db
SG
24void mx1_map_io(void);
25void mx21_map_io(void);
803648db
SG
26void mx27_map_io(void);
27void mx31_map_io(void);
28void mx35_map_io(void);
803648db
SG
29void imx1_init_early(void);
30void imx21_init_early(void);
803648db
SG
31void imx27_init_early(void);
32void imx31_init_early(void);
33void imx35_init_early(void);
803648db 34void mxc_init_irq(void __iomem *);
fffa0512 35void tzic_init_irq(void);
803648db
SG
36void mx1_init_irq(void);
37void mx21_init_irq(void);
803648db
SG
38void mx27_init_irq(void);
39void mx31_init_irq(void);
40void mx35_init_irq(void);
803648db
SG
41void imx1_soc_init(void);
42void imx21_soc_init(void);
803648db
SG
43void imx27_soc_init(void);
44void imx31_soc_init(void);
45void imx35_soc_init(void);
803648db 46void epit_timer_init(void __iomem *base, int irq);
6c529c49 47void mxc_timer_init(unsigned long, int);
803648db
SG
48int mx1_clocks_init(unsigned long fref);
49int mx21_clocks_init(unsigned long lref, unsigned long fref);
803648db
SG
50int mx27_clocks_init(unsigned long fref);
51int mx31_clocks_init(unsigned long fref);
52int mx35_clocks_init(void);
803648db
SG
53int mx31_clocks_init_dt(void);
54struct platform_device *mxc_register_gpio(char *name, int id,
b78d8e59 55 resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
803648db
SG
56void mxc_set_cpu_type(unsigned int type);
57void mxc_restart(enum reboot_mode, const char *);
58void mxc_arch_reset_init(void __iomem *);
803648db 59void imx_set_aips(void __iomem *);
e57e4ab5 60void imx_aips_allow_unprivileged_access(const char *compat);
803648db 61int mxc_device_init(void);
bfefdff8 62void imx_set_soc_revision(unsigned int rev);
f1c6f314 63void imx_init_revision_from_anatop(void);
a2887546 64struct device *imx_soc_device_init(void);
05136f08 65void imx6_enable_rbc(bool enable);
14517564 66void imx_gpc_check_dt(void);
05136f08
AH
67void imx_gpc_set_arm_power_in_lpm(bool power_off);
68void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw);
69void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw);
73d2b4cd 70
41e7daf2
SG
71enum mxc_cpu_pwr_mode {
72 WAIT_CLOCKED, /* wfi only */
73 WAIT_UNCLOCKED, /* WAIT */
74 WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */
75 STOP_POWER_ON, /* just STOP */
76 STOP_POWER_OFF, /* STOP + SRPG */
77};
78
3ac804e3
FE
79enum mx3_cpu_pwr_mode {
80 MX3_RUN,
81 MX3_WAIT,
82 MX3_DOZE,
83 MX3_SLEEP,
84};
85
803648db 86void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
b6de943b 87
803648db
SG
88void imx_enable_cpu(int cpu, bool enable);
89void imx_set_cpu_jump(int cpu, void *jump_addr);
90u32 imx_get_cpu_arg(int cpu);
91void imx_set_cpu_arg(int cpu, u32 arg);
69c31b7a 92#ifdef CONFIG_SMP
803648db
SG
93void v7_secondary_startup(void);
94void imx_scu_map_io(void);
95void imx_smp_prepare(void);
13eed989
SG
96#else
97static inline void imx_scu_map_io(void) {}
a1f1c7ef 98static inline void imx_smp_prepare(void) {}
69c31b7a 99#endif
803648db 100void imx_src_init(void);
80c0ecdc 101void imx_gpc_pre_suspend(bool arm_power_off);
803648db
SG
102void imx_gpc_post_resume(void);
103void imx_gpc_mask_all(void);
104void imx_gpc_restore_all(void);
65bb688a
MZ
105void imx_gpc_hwirq_mask(unsigned int hwirq);
106void imx_gpc_hwirq_unmask(unsigned int hwirq);
803648db
SG
107void imx_anatop_init(void);
108void imx_anatop_pre_suspend(void);
109void imx_anatop_post_resume(void);
8fb76a07 110int imx6_set_lpm(enum mxc_cpu_pwr_mode mode);
dfea953a 111void imx6q_set_int_mem_clk_lpm(bool enable);
751f7e99 112void imx6sl_set_wait_clk(bool enter);
ec336b28 113int imx_mmdc_get_ddr_type(void);
803648db
SG
114
115void imx_cpu_die(unsigned int cpu);
116int imx_cpu_kill(unsigned int cpu);
e4f2d979 117
c356bdb4
SG
118#ifdef CONFIG_SUSPEND
119void v7_cpu_resume(void);
df595746 120void imx6_suspend(void __iomem *ocram_vbase);
c356bdb4
SG
121#else
122static inline void v7_cpu_resume(void) {}
123static inline void imx6_suspend(void __iomem *ocram_vbase) {}
124#endif
125
803648db 126void imx6q_pm_init(void);
df595746
AH
127void imx6dl_pm_init(void);
128void imx6sl_pm_init(void);
ff843d62 129void imx6sx_pm_init(void);
df595746 130
28a9f3b0 131#ifdef CONFIG_PM
36b66c3f
SG
132void imx51_pm_init(void);
133void imx53_pm_init(void);
46ec1b26 134#else
36b66c3f
SG
135static inline void imx51_pm_init(void) {}
136static inline void imx53_pm_init(void) {}
46ec1b26
EM
137#endif
138
8321b758 139#ifdef CONFIG_NEON
803648db 140int mx51_neon_fixup(void);
8321b758
SG
141#else
142static inline int mx51_neon_fixup(void) { return 0; }
143#endif
144
e6a07569 145#ifdef CONFIG_CACHE_L2X0
803648db 146void imx_init_l2cache(void);
e6a07569
SG
147#else
148static inline void imx_init_l2cache(void) {}
149#endif
150
e4f2d979 151extern struct smp_operations imx_smp_ops;
4e3fea4a 152extern struct smp_operations ls1021a_smp_ops;
e4f2d979 153
52c543f9 154#endif
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