[deliverable/linux.git] / arch / arm / mach-imx / cpu-imx5.c

/*
 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 *
 * This file contains the CPU initialization code.
 */

#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>

#include "hardware.h"
#include "common.h"

static int mx5_cpu_rev = -1;

#define IIM_SREV 0x24

static u32 imx5_read_srev_reg(const char *compat)
{
	void __iomem *iim_base;
	struct device_node *np;
	u32 srev;

	np = of_find_compatible_node(NULL, NULL, compat);
	iim_base = of_iomap(np, 0);
	WARN_ON(!iim_base);

	srev = readl(iim_base + IIM_SREV) & 0xff;

	iounmap(iim_base);

	return srev;
}

static int get_mx51_srev(void)
{
	u32 rev = imx5_read_srev_reg("fsl,imx51-iim");

	switch (rev) {
	case 0x0:
		return IMX_CHIP_REVISION_2_0;
	case 0x10:
		return IMX_CHIP_REVISION_3_0;
	default:
		return IMX_CHIP_REVISION_UNKNOWN;
	}
}

/*
 * Returns:
 *	the silicon revision of the cpu
 *	-EINVAL - not a mx51
 */
int mx51_revision(void)
{
	if (!cpu_is_mx51())
		return -EINVAL;

	if (mx5_cpu_rev == -1)
		mx5_cpu_rev = get_mx51_srev();

	return mx5_cpu_rev;
}
EXPORT_SYMBOL(mx51_revision);

#ifdef CONFIG_NEON

/*
 * All versions of the silicon before Rev. 3 have broken NEON implementations.
 * Dependent on link order - so the assumption is that vfp_init is called
 * before us.
 */
int __init mx51_neon_fixup(void)
{
	if (mx51_revision() < IMX_CHIP_REVISION_3_0 &&
			(elf_hwcap & HWCAP_NEON)) {
		elf_hwcap &= ~HWCAP_NEON;
		pr_info("Turning off NEON support, detected broken NEON implementation\n");
	}
	return 0;
}

#endif

static int get_mx53_srev(void)
{
	u32 rev = imx5_read_srev_reg("fsl,imx53-iim");

	switch (rev) {
	case 0x0:
		return IMX_CHIP_REVISION_1_0;
	case 0x2:
		return IMX_CHIP_REVISION_2_0;
	case 0x3:
		return IMX_CHIP_REVISION_2_1;
	default:
		return IMX_CHIP_REVISION_UNKNOWN;
	}
}

/*
 * Returns:
 *	the silicon revision of the cpu
 *	-EINVAL - not a mx53
 */
int mx53_revision(void)
{
	if (!cpu_is_mx53())
		return -EINVAL;

	if (mx5_cpu_rev == -1)
		mx5_cpu_rev = get_mx53_srev();

	return mx5_cpu_rev;
}
EXPORT_SYMBOL(mx53_revision);
Commit	Line	Data
a329b48c	1	/*
b66ff7a2	2	* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
a329b48c AK	3	*
	4	* The code contained herein is licensed under the GNU General Public
	5	* License. You may obtain a copy of the GNU General Public License
	6	* Version 2 or later at the following locations:
	7	*
	8	* http://www.opensource.org/licenses/gpl-license.html
	9	* http://www.gnu.org/copyleft/gpl.html
	10	*
	11	* This file contains the CPU initialization code.
	12	*/
	13
	14	#include <linux/types.h>
	15	#include <linux/kernel.h>
	16	#include <linux/init.h>
5443856c	17	#include <linux/module.h>
ca06679d	18	#include <linux/io.h>
ee18a715 SG	19	#include <linux/of.h>
ee18a715 SG	20	#include <linux/of_address.h>
a329b48c	21
50f2de61	22	#include "hardware.h"
22567796	23	#include "common.h"
50f2de61	24
c52c9835	25	static int mx5_cpu_rev = -1;
5443856c	26
9ab4650f	27	#define IIM_SREV 0x24
5443856c	28
ee18a715 SG	29	static u32 imx5_read_srev_reg(const char *compat)
	30	{
	31	void __iomem *iim_base;
	32	struct device_node *np;
	33	u32 srev;
	34
	35	np = of_find_compatible_node(NULL, NULL, compat);
	36	iim_base = of_iomap(np, 0);
	37	WARN_ON(!iim_base);
	38
	39	srev = readl(iim_base + IIM_SREV) & 0xff;
	40
	41	iounmap(iim_base);
	42
	43	return srev;
	44	}
	45
9ab4650f	46	static int get_mx51_srev(void)
5443856c	47	{
ee18a715	48	u32 rev = imx5_read_srev_reg("fsl,imx51-iim");
5443856c	49
c52c9835 JL	50	switch (rev) {
c52c9835 JL	51	case 0x0:
9ab4650f	52	return IMX_CHIP_REVISION_2_0;
c52c9835	53	case 0x10:
9ab4650f	54	return IMX_CHIP_REVISION_3_0;
c52c9835 JL	55	default:
	56	return IMX_CHIP_REVISION_UNKNOWN;
	57	}
5443856c SH	58	}
	59
	60	/*
	61	* Returns:
	62	* the silicon revision of the cpu
	63	* -EINVAL - not a mx51
	64	*/
	65	int mx51_revision(void)
	66	{
	67	if (!cpu_is_mx51())
	68	return -EINVAL;
	69
c52c9835 JL	70	if (mx5_cpu_rev == -1)
c52c9835 JL	71	mx5_cpu_rev = get_mx51_srev();
5443856c	72
c52c9835	73	return mx5_cpu_rev;
5443856c SH	74	}
	75	EXPORT_SYMBOL(mx51_revision);
	76
33d7c5c1 AK	77	#ifdef CONFIG_NEON
	78
	79	/*
	80	* All versions of the silicon before Rev. 3 have broken NEON implementations.
	81	* Dependent on link order - so the assumption is that vfp_init is called
	82	* before us.
	83	*/
8321b758	84	int __init mx51_neon_fixup(void)
33d7c5c1	85	{
ca06679d FE	86	if (mx51_revision() < IMX_CHIP_REVISION_3_0 &&
ca06679d FE	87	(elf_hwcap & HWCAP_NEON)) {
33d7c5c1 AK	88	elf_hwcap &= ~HWCAP_NEON;
	89	pr_info("Turning off NEON support, detected broken NEON implementation\n");
	90	}
	91	return 0;
	92	}
	93
33d7c5c1 AK	94	#endif
33d7c5c1 AK	95
9ab4650f DN	96	static int get_mx53_srev(void)
9ab4650f DN	97	{
ee18a715	98	u32 rev = imx5_read_srev_reg("fsl,imx53-iim");
9ab4650f	99
503e1639 RZ	100	switch (rev) {
503e1639 RZ	101	case 0x0:
9ab4650f	102	return IMX_CHIP_REVISION_1_0;
503e1639	103	case 0x2:
9ab4650f	104	return IMX_CHIP_REVISION_2_0;
503e1639 RZ	105	case 0x3:
	106	return IMX_CHIP_REVISION_2_1;
	107	default:
	108	return IMX_CHIP_REVISION_UNKNOWN;
	109	}
9ab4650f DN	110	}
9ab4650f DN	111
b66ff7a2 DN	112	/*
	113	* Returns:
	114	* the silicon revision of the cpu
	115	* -EINVAL - not a mx53
	116	*/
	117	int mx53_revision(void)
	118	{
	119	if (!cpu_is_mx53())
	120	return -EINVAL;
	121
c52c9835 JL	122	if (mx5_cpu_rev == -1)
c52c9835 JL	123	mx5_cpu_rev = get_mx53_srev();
b66ff7a2	124
c52c9835	125	return mx5_cpu_rev;
b66ff7a2 DN	126	}
b66ff7a2 DN	127	EXPORT_SYMBOL(mx53_revision);