[deliverable/linux.git] / arch / arm / mach-imx / cpu.c


#include <linux/module.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/slab.h>
#include <linux/sys_soc.h>

#include "hardware.h"
#include "common.h"

unsigned int __mxc_cpu_type;
EXPORT_SYMBOL(__mxc_cpu_type);

static unsigned int imx_soc_revision;

void mxc_set_cpu_type(unsigned int type)
{
	__mxc_cpu_type = type;
}

void imx_set_soc_revision(unsigned int rev)
{
	imx_soc_revision = rev;
}

unsigned int imx_get_soc_revision(void)
{
	return imx_soc_revision;
}

void imx_print_silicon_rev(const char *cpu, int srev)
{
	if (srev == IMX_CHIP_REVISION_UNKNOWN)
		pr_info("CPU identified as %s, unknown revision\n", cpu);
	else
		pr_info("CPU identified as %s, silicon rev %d.%d\n",
				cpu, (srev >> 4) & 0xf, srev & 0xf);
}

void __init imx_set_aips(void __iomem *base)
{
	unsigned int reg;
/*
 * Set all MPROTx to be non-bufferable, trusted for R/W,
 * not forced to user-mode.
 */
	__raw_writel(0x77777777, base + 0x0);
	__raw_writel(0x77777777, base + 0x4);

/*
 * Set all OPACRx to be non-bufferable, to not require
 * supervisor privilege level for access, allow for
 * write access and untrusted master access.
 */
	__raw_writel(0x0, base + 0x40);
	__raw_writel(0x0, base + 0x44);
	__raw_writel(0x0, base + 0x48);
	__raw_writel(0x0, base + 0x4C);
	reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
	__raw_writel(reg, base + 0x50);
}

struct device * __init imx_soc_device_init(void)
{
	struct soc_device_attribute *soc_dev_attr;
	struct soc_device *soc_dev;
	struct device_node *root;
	const char *soc_id;
	int ret;

	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
	if (!soc_dev_attr)
		return NULL;

	soc_dev_attr->family = "Freescale i.MX";

	root = of_find_node_by_path("/");
	ret = of_property_read_string(root, "model", &soc_dev_attr->machine);
	of_node_put(root);
	if (ret)
		goto free_soc;

	switch (__mxc_cpu_type) {
	case MXC_CPU_MX1:
		soc_id = "i.MX1";
		break;
	case MXC_CPU_MX21:
		soc_id = "i.MX21";
		break;
	case MXC_CPU_MX25:
		soc_id = "i.MX25";
		break;
	case MXC_CPU_MX27:
		soc_id = "i.MX27";
		break;
	case MXC_CPU_MX31:
		soc_id = "i.MX31";
		break;
	case MXC_CPU_MX35:
		soc_id = "i.MX35";
		break;
	case MXC_CPU_MX51:
		soc_id = "i.MX51";
		break;
	case MXC_CPU_MX53:
		soc_id = "i.MX53";
		break;
	case MXC_CPU_IMX6SL:
		soc_id = "i.MX6SL";
		break;
	case MXC_CPU_IMX6DL:
		soc_id = "i.MX6DL";
		break;
	case MXC_CPU_IMX6Q:
		soc_id = "i.MX6Q";
		break;
	default:
		soc_id = "Unknown";
	}
	soc_dev_attr->soc_id = soc_id;

	soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d",
					   (imx_soc_revision >> 4) & 0xf,
					   imx_soc_revision & 0xf);
	if (!soc_dev_attr->revision)
		goto free_soc;

	soc_dev = soc_device_register(soc_dev_attr);
	if (IS_ERR(soc_dev))
		goto free_rev;

	return soc_device_to_device(soc_dev);

free_rev:
	kfree(soc_dev_attr->revision);
free_soc:
	kfree(soc_dev_attr);
	return NULL;
}
Commit	Line	Data
198016e1 SH	1
198016e1 SH	2	#include <linux/module.h>
bb07d751	3	#include <linux/io.h>
a2887546 SG	4	#include <linux/of.h>
	5	#include <linux/slab.h>
	6	#include <linux/sys_soc.h>
50f2de61 SG	7
50f2de61 SG	8	#include "hardware.h"
e7feaaa7	9	#include "common.h"
198016e1 SH	10
	11	unsigned int __mxc_cpu_type;
	12	EXPORT_SYMBOL(__mxc_cpu_type);
	13
bfefdff8 SG	14	static unsigned int imx_soc_revision;
bfefdff8 SG	15
198016e1 SH	16	void mxc_set_cpu_type(unsigned int type)
	17	{
	18	__mxc_cpu_type = type;
	19	}
	20
bfefdff8 SG	21	void imx_set_soc_revision(unsigned int rev)
	22	{
	23	imx_soc_revision = rev;
	24	}
	25
	26	unsigned int imx_get_soc_revision(void)
	27	{
	28	return imx_soc_revision;
	29	}
	30
059e58f6 FE	31	void imx_print_silicon_rev(const char *cpu, int srev)
	32	{
	33	if (srev == IMX_CHIP_REVISION_UNKNOWN)
	34	pr_info("CPU identified as %s, unknown revision\n", cpu);
	35	else
	36	pr_info("CPU identified as %s, silicon rev %d.%d\n",
	37	cpu, (srev >> 4) & 0xf, srev & 0xf);
	38	}
bb07d751 FE	39
	40	void __init imx_set_aips(void __iomem *base)
	41	{
	42	unsigned int reg;
	43	/*
	44	* Set all MPROTx to be non-bufferable, trusted for R/W,
	45	* not forced to user-mode.
	46	*/
	47	__raw_writel(0x77777777, base + 0x0);
	48	__raw_writel(0x77777777, base + 0x4);
	49
	50	/*
	51	* Set all OPACRx to be non-bufferable, to not require
	52	* supervisor privilege level for access, allow for
	53	* write access and untrusted master access.
	54	*/
	55	__raw_writel(0x0, base + 0x40);
	56	__raw_writel(0x0, base + 0x44);
	57	__raw_writel(0x0, base + 0x48);
	58	__raw_writel(0x0, base + 0x4C);
	59	reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
	60	__raw_writel(reg, base + 0x50);
	61	}
a2887546 SG	62
	63	struct device * __init imx_soc_device_init(void)
	64	{
	65	struct soc_device_attribute *soc_dev_attr;
	66	struct soc_device *soc_dev;
	67	struct device_node *root;
	68	const char *soc_id;
	69	int ret;
	70
	71	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
	72	if (!soc_dev_attr)
	73	return NULL;
	74
	75	soc_dev_attr->family = "Freescale i.MX";
	76
	77	root = of_find_node_by_path("/");
	78	ret = of_property_read_string(root, "model", &soc_dev_attr->machine);
	79	of_node_put(root);
	80	if (ret)
	81	goto free_soc;
	82
	83	switch (__mxc_cpu_type) {
	84	case MXC_CPU_MX1:
	85	soc_id = "i.MX1";
	86	break;
	87	case MXC_CPU_MX21:
	88	soc_id = "i.MX21";
	89	break;
	90	case MXC_CPU_MX25:
	91	soc_id = "i.MX25";
	92	break;
	93	case MXC_CPU_MX27:
	94	soc_id = "i.MX27";
	95	break;
	96	case MXC_CPU_MX31:
	97	soc_id = "i.MX31";
	98	break;
	99	case MXC_CPU_MX35:
	100	soc_id = "i.MX35";
	101	break;
	102	case MXC_CPU_MX51:
	103	soc_id = "i.MX51";
	104	break;
	105	case MXC_CPU_MX53:
	106	soc_id = "i.MX53";
	107	break;
	108	case MXC_CPU_IMX6SL:
	109	soc_id = "i.MX6SL";
	110	break;
	111	case MXC_CPU_IMX6DL:
	112	soc_id = "i.MX6DL";
	113	break;
	114	case MXC_CPU_IMX6Q:
	115	soc_id = "i.MX6Q";
	116	break;
	117	default:
	118	soc_id = "Unknown";
	119	}
	120	soc_dev_attr->soc_id = soc_id;
	121
	122	soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d",
	123	(imx_soc_revision >> 4) & 0xf,
	124	imx_soc_revision & 0xf);
	125	if (!soc_dev_attr->revision)
126	goto free_soc;
127
128	soc_dev = soc_device_register(soc_dev_attr);
129	if (IS_ERR(soc_dev))
130	goto free_rev;
131
132	return soc_device_to_device(soc_dev);
133
134	free_rev:
135	kfree(soc_dev_attr->revision);
136	free_soc:
137	kfree(soc_dev_attr);
138	return NULL;
139	}