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fc80a5e3 JB |
1 | /* |
2 | * Author: MontaVista Software, Inc. | |
3 | * <source@mvista.com> | |
4 | * | |
5 | * Based on the OMAP devices.c | |
6 | * | |
7 | * 2005 (c) MontaVista Software, Inc. This file is licensed under the | |
8 | * terms of the GNU General Public License version 2. This program is | |
9 | * licensed "as is" without any warranty of any kind, whether express | |
10 | * or implied. | |
11 | * | |
12 | * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
13 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | |
07469495 UKK |
14 | * Copyright 2008 Sascha Hauer, kernel@pengutronix.de |
15 | * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | |
16 | * Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt> | |
fc80a5e3 JB |
17 | * |
18 | * This program is free software; you can redistribute it and/or | |
19 | * modify it under the terms of the GNU General Public License | |
20 | * as published by the Free Software Foundation; either version 2 | |
21 | * of the License, or (at your option) any later version. | |
22 | * This program is distributed in the hope that it will be useful, | |
23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
25 | * GNU General Public License for more details. | |
26 | * | |
27 | * You should have received a copy of the GNU General Public License | |
28 | * along with this program; if not, write to the Free Software | |
29 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
30 | * MA 02110-1301, USA. | |
31 | */ | |
32 | #include <linux/module.h> | |
33 | #include <linux/kernel.h> | |
34 | #include <linux/init.h> | |
35 | #include <linux/platform_device.h> | |
36 | #include <linux/gpio.h> | |
3eb352c7 | 37 | #include <linux/dma-mapping.h> |
e9ec2a17 | 38 | #include <linux/serial.h> |
fc80a5e3 | 39 | |
80b02c17 | 40 | #include <mach/irqs.h> |
a09e64fb | 41 | #include <mach/hardware.h> |
058b7a6f | 42 | #include <mach/common.h> |
1a02be0e | 43 | #include <mach/mmc.h> |
058b7a6f HS |
44 | |
45 | #include "devices.h" | |
fc80a5e3 | 46 | |
07469495 UKK |
47 | #if defined(CONFIG_ARCH_MX1) |
48 | static struct resource imx1_camera_resources[] = { | |
49 | { | |
50 | .start = 0x00224000, | |
51 | .end = 0x00224010, | |
52 | .flags = IORESOURCE_MEM, | |
53 | }, { | |
54 | .start = MX1_CSI_INT, | |
55 | .end = MX1_CSI_INT, | |
56 | .flags = IORESOURCE_IRQ, | |
57 | }, | |
58 | }; | |
59 | ||
60 | static u64 imx1_camera_dmamask = DMA_BIT_MASK(32); | |
61 | ||
62 | struct platform_device imx1_camera_device = { | |
63 | .name = "mx1-camera", | |
64 | .id = 0, /* This is used to put cameras on this interface */ | |
65 | .dev = { | |
66 | .dma_mask = &imx1_camera_dmamask, | |
67 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
68 | }, | |
69 | .resource = imx1_camera_resources, | |
70 | .num_resources = ARRAY_SIZE(imx1_camera_resources), | |
71 | }; | |
72 | ||
73 | static struct resource imx_i2c_resources[] = { | |
74 | { | |
75 | .start = 0x00217000, | |
76 | .end = 0x00217010, | |
77 | .flags = IORESOURCE_MEM, | |
78 | }, { | |
79 | .start = MX1_I2C_INT, | |
80 | .end = MX1_I2C_INT, | |
81 | .flags = IORESOURCE_IRQ, | |
82 | }, | |
83 | }; | |
84 | ||
85 | struct platform_device imx_i2c_device0 = { | |
86 | .name = "imx-i2c", | |
87 | .id = 0, | |
88 | .resource = imx_i2c_resources, | |
89 | .num_resources = ARRAY_SIZE(imx_i2c_resources), | |
90 | }; | |
91 | ||
92 | #define DEFINE_IMX1_UART_DEVICE(n, baseaddr, irqrx, irqtx, irqrts) \ | |
93 | static struct resource imx1_uart_resources ## n[] = { \ | |
94 | { \ | |
95 | .start = baseaddr, \ | |
96 | .end = baseaddr + 0xd0, \ | |
97 | .flags = IORESOURCE_MEM, \ | |
98 | }, { \ | |
99 | .start = irqrx, \ | |
100 | .end = irqrx, \ | |
101 | .flags = IORESOURCE_IRQ, \ | |
102 | }, { \ | |
103 | .start = irqtx, \ | |
104 | .end = irqtx, \ | |
105 | .flags = IORESOURCE_IRQ, \ | |
106 | }, { \ | |
107 | .start = irqrts, \ | |
108 | .end = irqrts, \ | |
109 | .flags = IORESOURCE_IRQ, \ | |
110 | }, \ | |
111 | }; \ | |
112 | \ | |
113 | struct platform_device imx1_uart_device ## n = { \ | |
114 | .name = "imx-uart", \ | |
115 | .id = n, \ | |
116 | .num_resources = ARRAY_SIZE(imx1_uart_resources ## n), \ | |
117 | .resource = imx1_uart_resources ## n, \ | |
118 | } | |
119 | ||
120 | DEFINE_IMX1_UART_DEVICE(0, MX1_UART1_BASE_ADDR, MX1_UART1_MINT_RX, MX1_UART1_MINT_TX, MX1_UART1_MINT_RTS); | |
121 | DEFINE_IMX1_UART_DEVICE(1, MX1_UART2_BASE_ADDR, MX1_UART2_MINT_RX, MX1_UART2_MINT_TX, MX1_UART2_MINT_RTS); | |
122 | ||
123 | static struct resource imx_rtc_resources[] = { | |
124 | { | |
125 | .start = 0x00204000, | |
126 | .end = 0x00204024, | |
127 | .flags = IORESOURCE_MEM, | |
128 | }, { | |
129 | .start = MX1_RTC_INT, | |
130 | .end = MX1_RTC_INT, | |
131 | .flags = IORESOURCE_IRQ, | |
132 | }, { | |
133 | .start = MX1_RTC_SAMINT, | |
134 | .end = MX1_RTC_SAMINT, | |
135 | .flags = IORESOURCE_IRQ, | |
136 | }, | |
137 | }; | |
138 | ||
139 | struct platform_device imx_rtc_device = { | |
140 | .name = "rtc-imx", | |
141 | .id = 0, | |
142 | .resource = imx_rtc_resources, | |
143 | .num_resources = ARRAY_SIZE(imx_rtc_resources), | |
144 | }; | |
145 | ||
146 | static struct resource imx_wdt_resources[] = { | |
147 | { | |
148 | .start = 0x00201000, | |
149 | .end = 0x00201008, | |
150 | .flags = IORESOURCE_MEM, | |
151 | }, { | |
152 | .start = MX1_WDT_INT, | |
153 | .end = MX1_WDT_INT, | |
154 | .flags = IORESOURCE_IRQ, | |
155 | }, | |
156 | }; | |
157 | ||
158 | struct platform_device imx_wdt_device = { | |
159 | .name = "imx-wdt", | |
160 | .id = 0, | |
161 | .resource = imx_wdt_resources, | |
162 | .num_resources = ARRAY_SIZE(imx_wdt_resources), | |
163 | }; | |
164 | ||
165 | static struct resource imx_usb_resources[] = { | |
166 | { | |
167 | .start = 0x00212000, | |
168 | .end = 0x00212148, | |
169 | .flags = IORESOURCE_MEM, | |
170 | }, { | |
171 | .start = MX1_USBD_INT0, | |
172 | .end = MX1_USBD_INT0, | |
173 | .flags = IORESOURCE_IRQ, | |
174 | }, { | |
175 | .start = MX1_USBD_INT1, | |
176 | .end = MX1_USBD_INT1, | |
177 | .flags = IORESOURCE_IRQ, | |
178 | }, { | |
179 | .start = MX1_USBD_INT2, | |
180 | .end = MX1_USBD_INT2, | |
181 | .flags = IORESOURCE_IRQ, | |
182 | }, { | |
183 | .start = MX1_USBD_INT3, | |
184 | .end = MX1_USBD_INT3, | |
185 | .flags = IORESOURCE_IRQ, | |
186 | }, { | |
187 | .start = MX1_USBD_INT4, | |
188 | .end = MX1_USBD_INT4, | |
189 | .flags = IORESOURCE_IRQ, | |
190 | }, { | |
191 | .start = MX1_USBD_INT5, | |
192 | .end = MX1_USBD_INT5, | |
193 | .flags = IORESOURCE_IRQ, | |
194 | }, { | |
195 | .start = MX1_USBD_INT6, | |
196 | .end = MX1_USBD_INT6, | |
197 | .flags = IORESOURCE_IRQ, | |
198 | }, | |
199 | }; | |
200 | ||
201 | struct platform_device imx_usb_device = { | |
202 | .name = "imx_udc", | |
203 | .id = 0, | |
204 | .num_resources = ARRAY_SIZE(imx_usb_resources), | |
205 | .resource = imx_usb_resources, | |
206 | }; | |
207 | ||
208 | /* GPIO port description */ | |
209 | static struct mxc_gpio_port imx_gpio_ports[] = { | |
210 | { | |
211 | .chip.label = "gpio-0", | |
212 | .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR), | |
213 | .irq = MX1_GPIO_INT_PORTA, | |
214 | .virtual_irq_start = MXC_GPIO_IRQ_START, | |
215 | }, { | |
216 | .chip.label = "gpio-1", | |
217 | .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x100), | |
218 | .irq = MX1_GPIO_INT_PORTB, | |
219 | .virtual_irq_start = MXC_GPIO_IRQ_START + 32, | |
220 | }, { | |
221 | .chip.label = "gpio-2", | |
222 | .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x200), | |
223 | .irq = MX1_GPIO_INT_PORTC, | |
224 | .virtual_irq_start = MXC_GPIO_IRQ_START + 64, | |
225 | }, { | |
226 | .chip.label = "gpio-3", | |
227 | .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x300), | |
228 | .irq = MX1_GPIO_INT_PORTD, | |
229 | .virtual_irq_start = MXC_GPIO_IRQ_START + 96, | |
230 | } | |
231 | }; | |
232 | ||
233 | int __init imx1_register_gpios(void) | |
234 | { | |
235 | return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); | |
236 | } | |
237 | #endif | |
238 | ||
239 | #if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27) | |
f420db84 SH |
240 | /* |
241 | * SPI master controller | |
242 | * | |
243 | * - i.MX1: 2 channel (slighly different register setting) | |
244 | * - i.MX21: 2 channel | |
245 | * - i.MX27: 3 channel | |
246 | */ | |
68c94b40 UKK |
247 | #define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq) \ |
248 | static struct resource mxc_spi_resources ## n[] = { \ | |
249 | { \ | |
250 | .start = baseaddr, \ | |
251 | .end = baseaddr + SZ_4K - 1, \ | |
252 | .flags = IORESOURCE_MEM, \ | |
253 | }, { \ | |
254 | .start = irq, \ | |
255 | .end = irq, \ | |
256 | .flags = IORESOURCE_IRQ, \ | |
257 | }, \ | |
258 | }; \ | |
259 | \ | |
260 | struct platform_device mxc_spi_device ## n = { \ | |
261 | .name = "spi_imx", \ | |
262 | .id = n, \ | |
263 | .num_resources = ARRAY_SIZE(mxc_spi_resources ## n), \ | |
264 | .resource = mxc_spi_resources ## n, \ | |
265 | } | |
f420db84 | 266 | |
68c94b40 UKK |
267 | DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1); |
268 | DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2); | |
f420db84 SH |
269 | |
270 | #ifdef CONFIG_MACH_MX27 | |
68c94b40 | 271 | DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3); |
f420db84 SH |
272 | #endif |
273 | ||
fc80a5e3 JB |
274 | /* |
275 | * General Purpose Timer | |
bf50bcc2 SH |
276 | * - i.MX21: 3 timers |
277 | * - i.MX27: 6 timers | |
fc80a5e3 | 278 | */ |
2b84a364 UKK |
279 | #define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \ |
280 | static struct resource timer ## n ##_resources[] = { \ | |
281 | { \ | |
282 | .start = baseaddr, \ | |
283 | .end = baseaddr + SZ_4K - 1, \ | |
284 | .flags = IORESOURCE_MEM, \ | |
285 | }, { \ | |
286 | .start = irq, \ | |
287 | .end = irq, \ | |
288 | .flags = IORESOURCE_IRQ, \ | |
289 | } \ | |
290 | }; \ | |
291 | \ | |
292 | struct platform_device mxc_gpt ## n = { \ | |
293 | .name = "imx_gpt", \ | |
294 | .id = n, \ | |
295 | .num_resources = ARRAY_SIZE(timer ## n ## _resources), \ | |
296 | .resource = timer ## n ## _resources, \ | |
fc80a5e3 | 297 | } |
fc80a5e3 | 298 | |
2b84a364 UKK |
299 | /* We use gpt1 as system timer, so do not add a device for this one */ |
300 | DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2); | |
301 | DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3); | |
fc80a5e3 JB |
302 | |
303 | #ifdef CONFIG_MACH_MX27 | |
2b84a364 UKK |
304 | DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4); |
305 | DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5); | |
306 | DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6); | |
fc80a5e3 JB |
307 | #endif |
308 | ||
6d38c1cf | 309 | /* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */ |
fc80a5e3 JB |
310 | static struct resource mxc_wdt_resources[] = { |
311 | { | |
58152a16 UKK |
312 | .start = MX2x_WDOG_BASE_ADDR, |
313 | .end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1, | |
314 | .flags = IORESOURCE_MEM, | |
fc80a5e3 JB |
315 | }, |
316 | }; | |
317 | ||
318 | struct platform_device mxc_wdt = { | |
6d38c1cf | 319 | .name = "imx2-wdt", |
fc80a5e3 JB |
320 | .id = 0, |
321 | .num_resources = ARRAY_SIZE(mxc_wdt_resources), | |
322 | .resource = mxc_wdt_resources, | |
323 | }; | |
324 | ||
3d89baa7 SH |
325 | static struct resource mxc_w1_master_resources[] = { |
326 | { | |
58152a16 UKK |
327 | .start = MX2x_OWIRE_BASE_ADDR, |
328 | .end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1, | |
3d89baa7 SH |
329 | .flags = IORESOURCE_MEM, |
330 | }, | |
331 | }; | |
332 | ||
333 | struct platform_device mxc_w1_master_device = { | |
334 | .name = "mxc_w1", | |
335 | .id = 0, | |
336 | .num_resources = ARRAY_SIZE(mxc_w1_master_resources), | |
337 | .resource = mxc_w1_master_resources, | |
338 | }; | |
339 | ||
f0d3ab49 UKK |
340 | #define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq) \ |
341 | static struct resource pfx ## _nand_resources[] = { \ | |
342 | { \ | |
343 | .start = baseaddr, \ | |
344 | .end = baseaddr + SZ_4K - 1, \ | |
345 | .flags = IORESOURCE_MEM, \ | |
346 | }, { \ | |
347 | .start = irq, \ | |
348 | .end = irq, \ | |
349 | .flags = IORESOURCE_IRQ, \ | |
350 | }, \ | |
351 | }; \ | |
352 | \ | |
353 | struct platform_device pfx ## _nand_device = { \ | |
354 | .name = "mxc_nand", \ | |
355 | .id = 0, \ | |
356 | .num_resources = ARRAY_SIZE(pfx ## _nand_resources), \ | |
357 | .resource = pfx ## _nand_resources, \ | |
358 | } | |
02870978 | 359 | |
f0d3ab49 UKK |
360 | #ifdef CONFIG_MACH_MX21 |
361 | DEFINE_MXC_NAND_DEVICE(imx21, MX21_NFC_BASE_ADDR, MX21_INT_NANDFC); | |
362 | #endif | |
363 | ||
364 | #ifdef CONFIG_MACH_MX27 | |
365 | DEFINE_MXC_NAND_DEVICE(imx27, MX27_NFC_BASE_ADDR, MX27_INT_NANDFC); | |
366 | #endif | |
02870978 | 367 | |
e4813551 HS |
368 | /* |
369 | * lcdc: | |
370 | * - i.MX1: the basic controller | |
371 | * - i.MX21: to be checked | |
372 | * - i.MX27: like i.MX1, with slightly variations | |
373 | */ | |
374 | static struct resource mxc_fb[] = { | |
375 | { | |
58152a16 UKK |
376 | .start = MX2x_LCDC_BASE_ADDR, |
377 | .end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1, | |
e4813551 | 378 | .flags = IORESOURCE_MEM, |
bf50bcc2 | 379 | }, { |
58152a16 UKK |
380 | .start = MX2x_INT_LCDC, |
381 | .end = MX2x_INT_LCDC, | |
e4813551 HS |
382 | .flags = IORESOURCE_IRQ, |
383 | } | |
384 | }; | |
385 | ||
386 | /* mxc lcd driver */ | |
387 | struct platform_device mxc_fb_device = { | |
388 | .name = "imx-fb", | |
389 | .id = 0, | |
390 | .num_resources = ARRAY_SIZE(mxc_fb), | |
391 | .resource = mxc_fb, | |
392 | .dev = { | |
3eb352c7 | 393 | .coherent_dma_mask = DMA_BIT_MASK(32), |
e4813551 HS |
394 | }, |
395 | }; | |
396 | ||
879fea1b SH |
397 | #ifdef CONFIG_MACH_MX27 |
398 | static struct resource mxc_fec_resources[] = { | |
399 | { | |
58152a16 UKK |
400 | .start = MX27_FEC_BASE_ADDR, |
401 | .end = MX27_FEC_BASE_ADDR + SZ_4K - 1, | |
402 | .flags = IORESOURCE_MEM, | |
879fea1b | 403 | }, { |
58152a16 UKK |
404 | .start = MX27_INT_FEC, |
405 | .end = MX27_INT_FEC, | |
406 | .flags = IORESOURCE_IRQ, | |
879fea1b SH |
407 | }, |
408 | }; | |
409 | ||
410 | struct platform_device mxc_fec_device = { | |
411 | .name = "fec", | |
412 | .id = 0, | |
413 | .num_resources = ARRAY_SIZE(mxc_fec_resources), | |
414 | .resource = mxc_fec_resources, | |
415 | }; | |
e4813551 HS |
416 | #endif |
417 | ||
9309b2ba UKK |
418 | #define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq) \ |
419 | static struct resource mxc_i2c_resources ## n[] = { \ | |
420 | { \ | |
421 | .start = baseaddr, \ | |
422 | .end = baseaddr + SZ_4K - 1, \ | |
423 | .flags = IORESOURCE_MEM, \ | |
424 | }, { \ | |
425 | .start = irq, \ | |
426 | .end = irq, \ | |
427 | .flags = IORESOURCE_IRQ, \ | |
428 | } \ | |
429 | }; \ | |
430 | \ | |
431 | struct platform_device mxc_i2c_device ## n = { \ | |
432 | .name = "imx-i2c", \ | |
433 | .id = n, \ | |
434 | .num_resources = ARRAY_SIZE(mxc_i2c_resources ## n), \ | |
435 | .resource = mxc_i2c_resources ## n, \ | |
c5d4dbff | 436 | } |
c5d4dbff | 437 | |
9309b2ba | 438 | DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C); |
c5d4dbff SH |
439 | |
440 | #ifdef CONFIG_MACH_MX27 | |
9309b2ba | 441 | DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2); |
c5d4dbff SH |
442 | #endif |
443 | ||
824b16e6 | 444 | static struct resource mxc_pwm_resources[] = { |
bf50bcc2 | 445 | { |
58152a16 UKK |
446 | .start = MX2x_PWM_BASE_ADDR, |
447 | .end = MX2x_PWM_BASE_ADDR + SZ_4K - 1, | |
448 | .flags = IORESOURCE_MEM, | |
bf50bcc2 | 449 | }, { |
58152a16 UKK |
450 | .start = MX2x_INT_PWM, |
451 | .end = MX2x_INT_PWM, | |
452 | .flags = IORESOURCE_IRQ, | |
824b16e6 SH |
453 | } |
454 | }; | |
455 | ||
456 | struct platform_device mxc_pwm_device = { | |
457 | .name = "mxc_pwm", | |
458 | .id = 0, | |
459 | .num_resources = ARRAY_SIZE(mxc_pwm_resources), | |
bf50bcc2 | 460 | .resource = mxc_pwm_resources, |
824b16e6 SH |
461 | }; |
462 | ||
ccd0e42c UKK |
463 | #define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \ |
464 | static struct resource mxc_sdhc_resources ## n[] = { \ | |
465 | { \ | |
466 | .start = baseaddr, \ | |
467 | .end = baseaddr + SZ_4K - 1, \ | |
468 | .flags = IORESOURCE_MEM, \ | |
469 | }, { \ | |
470 | .start = irq, \ | |
471 | .end = irq, \ | |
472 | .flags = IORESOURCE_IRQ, \ | |
473 | }, { \ | |
474 | .start = dmareq, \ | |
475 | .end = dmareq, \ | |
476 | .flags = IORESOURCE_DMA, \ | |
477 | }, \ | |
478 | }; \ | |
479 | \ | |
988addf8 | 480 | static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32); \ |
ccd0e42c UKK |
481 | \ |
482 | struct platform_device mxc_sdhc_device ## n = { \ | |
483 | .name = "mxc-mmc", \ | |
484 | .id = n, \ | |
485 | .dev = { \ | |
486 | .dma_mask = &mxc_sdhc ## n ## _dmamask, \ | |
988addf8 | 487 | .coherent_dma_mask = DMA_BIT_MASK(32), \ |
ccd0e42c UKK |
488 | }, \ |
489 | .num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \ | |
490 | .resource = mxc_sdhc_resources ## n, \ | |
491 | } | |
1a02be0e | 492 | |
ccd0e42c UKK |
493 | DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1); |
494 | DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2); | |
1a02be0e | 495 | |
f6d2fa7d | 496 | #ifdef CONFIG_MACH_MX27 |
627fb3b9 M |
497 | static struct resource otg_resources[] = { |
498 | { | |
58152a16 UKK |
499 | .start = MX27_USBOTG_BASE_ADDR, |
500 | .end = MX27_USBOTG_BASE_ADDR + 0x1ff, | |
501 | .flags = IORESOURCE_MEM, | |
627fb3b9 | 502 | }, { |
58152a16 UKK |
503 | .start = MX27_INT_USB3, |
504 | .end = MX27_INT_USB3, | |
505 | .flags = IORESOURCE_IRQ, | |
627fb3b9 M |
506 | }, |
507 | }; | |
508 | ||
3eb352c7 | 509 | static u64 otg_dmamask = DMA_BIT_MASK(32); |
627fb3b9 M |
510 | |
511 | /* OTG gadget device */ | |
512 | struct platform_device mxc_otg_udc_device = { | |
513 | .name = "fsl-usb2-udc", | |
514 | .id = -1, | |
515 | .dev = { | |
516 | .dma_mask = &otg_dmamask, | |
3eb352c7 | 517 | .coherent_dma_mask = DMA_BIT_MASK(32), |
627fb3b9 M |
518 | }, |
519 | .resource = otg_resources, | |
520 | .num_resources = ARRAY_SIZE(otg_resources), | |
521 | }; | |
522 | ||
523 | /* OTG host */ | |
524 | struct platform_device mxc_otg_host = { | |
525 | .name = "mxc-ehci", | |
526 | .id = 0, | |
527 | .dev = { | |
3eb352c7 | 528 | .coherent_dma_mask = DMA_BIT_MASK(32), |
627fb3b9 M |
529 | .dma_mask = &otg_dmamask, |
530 | }, | |
531 | .resource = otg_resources, | |
532 | .num_resources = ARRAY_SIZE(otg_resources), | |
533 | }; | |
534 | ||
535 | /* USB host 1 */ | |
536 | ||
3eb352c7 | 537 | static u64 usbh1_dmamask = DMA_BIT_MASK(32); |
627fb3b9 M |
538 | |
539 | static struct resource mxc_usbh1_resources[] = { | |
540 | { | |
58152a16 UKK |
541 | .start = MX27_USBOTG_BASE_ADDR + 0x200, |
542 | .end = MX27_USBOTG_BASE_ADDR + 0x3ff, | |
627fb3b9 M |
543 | .flags = IORESOURCE_MEM, |
544 | }, { | |
58152a16 UKK |
545 | .start = MX27_INT_USB1, |
546 | .end = MX27_INT_USB1, | |
627fb3b9 M |
547 | .flags = IORESOURCE_IRQ, |
548 | }, | |
549 | }; | |
550 | ||
551 | struct platform_device mxc_usbh1 = { | |
552 | .name = "mxc-ehci", | |
553 | .id = 1, | |
554 | .dev = { | |
3eb352c7 | 555 | .coherent_dma_mask = DMA_BIT_MASK(32), |
627fb3b9 M |
556 | .dma_mask = &usbh1_dmamask, |
557 | }, | |
558 | .resource = mxc_usbh1_resources, | |
559 | .num_resources = ARRAY_SIZE(mxc_usbh1_resources), | |
560 | }; | |
561 | ||
562 | /* USB host 2 */ | |
3eb352c7 | 563 | static u64 usbh2_dmamask = DMA_BIT_MASK(32); |
627fb3b9 M |
564 | |
565 | static struct resource mxc_usbh2_resources[] = { | |
566 | { | |
58152a16 UKK |
567 | .start = MX27_USBOTG_BASE_ADDR + 0x400, |
568 | .end = MX27_USBOTG_BASE_ADDR + 0x5ff, | |
627fb3b9 M |
569 | .flags = IORESOURCE_MEM, |
570 | }, { | |
58152a16 UKK |
571 | .start = MX27_INT_USB2, |
572 | .end = MX27_INT_USB2, | |
627fb3b9 M |
573 | .flags = IORESOURCE_IRQ, |
574 | }, | |
575 | }; | |
576 | ||
577 | struct platform_device mxc_usbh2 = { | |
578 | .name = "mxc-ehci", | |
579 | .id = 2, | |
580 | .dev = { | |
3eb352c7 | 581 | .coherent_dma_mask = DMA_BIT_MASK(32), |
627fb3b9 M |
582 | .dma_mask = &usbh2_dmamask, |
583 | }, | |
584 | .resource = mxc_usbh2_resources, | |
585 | .num_resources = ARRAY_SIZE(mxc_usbh2_resources), | |
586 | }; | |
f6d2fa7d | 587 | #endif |
627fb3b9 | 588 | |
69ddb488 UKK |
589 | #define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \ |
590 | { \ | |
591 | .name = _name, \ | |
592 | .start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \ | |
593 | .end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \ | |
594 | .flags = IORESOURCE_DMA, \ | |
595 | } | |
23291df4 | 596 | |
69ddb488 UKK |
597 | #define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \ |
598 | static struct resource imx_ssi_resources ## n[] = { \ | |
599 | { \ | |
600 | .start = MX2x_SSI ## ssin ## _BASE_ADDR, \ | |
601 | .end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \ | |
602 | .flags = IORESOURCE_MEM, \ | |
603 | }, { \ | |
604 | .start = MX2x_INT_SSI1, \ | |
605 | .end = MX2x_INT_SSI1, \ | |
606 | .flags = IORESOURCE_IRQ, \ | |
607 | }, \ | |
608 | DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \ | |
609 | DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \ | |
610 | DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \ | |
611 | DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \ | |
612 | }; \ | |
613 | \ | |
614 | struct platform_device imx_ssi_device ## n = { \ | |
615 | .name = "imx-ssi", \ | |
616 | .id = n, \ | |
617 | .num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \ | |
618 | .resource = imx_ssi_resources ## n, \ | |
619 | } | |
23291df4 | 620 | |
69ddb488 UKK |
621 | DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1); |
622 | DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1); | |
23291df4 | 623 | |
551823e7 | 624 | #define DEFINE_IMX2x_UART_DEVICE(n, baseaddr, irq) \ |
e9ec2a17 UKK |
625 | static struct resource imx2x_uart_resources ## n[] = { \ |
626 | { \ | |
627 | .start = baseaddr, \ | |
628 | .end = baseaddr + 0xb5, \ | |
629 | .flags = IORESOURCE_MEM, \ | |
630 | }, { \ | |
631 | .start = irq, \ | |
632 | .end = irq, \ | |
633 | .flags = IORESOURCE_IRQ, \ | |
634 | }, \ | |
635 | }; \ | |
636 | \ | |
551823e7 | 637 | struct platform_device imx2x_uart_device ## n = { \ |
e9ec2a17 UKK |
638 | .name = "imx-uart", \ |
639 | .id = n, \ | |
640 | .num_resources = ARRAY_SIZE(imx2x_uart_resources ## n), \ | |
641 | .resource = imx2x_uart_resources ## n, \ | |
642 | } | |
643 | ||
551823e7 UKK |
644 | DEFINE_IMX2x_UART_DEVICE(0, MX2x_UART1_BASE_ADDR, MX2x_INT_UART1); |
645 | DEFINE_IMX2x_UART_DEVICE(1, MX2x_UART2_BASE_ADDR, MX2x_INT_UART2); | |
646 | DEFINE_IMX2x_UART_DEVICE(2, MX2x_UART3_BASE_ADDR, MX2x_INT_UART3); | |
647 | DEFINE_IMX2x_UART_DEVICE(3, MX2x_UART4_BASE_ADDR, MX2x_INT_UART4); | |
e9ec2a17 UKK |
648 | |
649 | #ifdef CONFIG_MACH_MX27 | |
551823e7 UKK |
650 | DEFINE_IMX2x_UART_DEVICE(4, MX27_UART5_BASE_ADDR, MX27_INT_UART5); |
651 | DEFINE_IMX2x_UART_DEVICE(5, MX27_UART6_BASE_ADDR, MX27_INT_UART6); | |
e9ec2a17 UKK |
652 | #endif |
653 | ||
fc80a5e3 | 654 | /* GPIO port description */ |
897359d5 UKK |
655 | #define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \ |
656 | { \ | |
657 | .chip.label = "gpio-" #n, \ | |
658 | .irq = _irq, \ | |
659 | .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \ | |
660 | n * 0x100), \ | |
661 | .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \ | |
662 | } | |
663 | ||
664 | #define DEFINE_MXC_GPIO_PORT(SOC, n) \ | |
665 | { \ | |
666 | .chip.label = "gpio-" #n, \ | |
667 | .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \ | |
668 | n * 0x100), \ | |
669 | .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \ | |
fc80a5e3 | 670 | } |
897359d5 UKK |
671 | |
672 | #define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \ | |
673 | static struct mxc_gpio_port pfx ## _gpio_ports[] = { \ | |
674 | DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \ | |
675 | DEFINE_MXC_GPIO_PORT(SOC, 1), \ | |
676 | DEFINE_MXC_GPIO_PORT(SOC, 2), \ | |
677 | DEFINE_MXC_GPIO_PORT(SOC, 3), \ | |
678 | DEFINE_MXC_GPIO_PORT(SOC, 4), \ | |
679 | DEFINE_MXC_GPIO_PORT(SOC, 5), \ | |
680 | } | |
681 | ||
682 | #ifdef CONFIG_MACH_MX21 | |
683 | DEFINE_MXC_GPIO_PORTS(MX21, imx21); | |
9a763bfb UKK |
684 | |
685 | int __init imx21_register_gpios(void) | |
686 | { | |
687 | return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports)); | |
688 | } | |
897359d5 UKK |
689 | #endif |
690 | ||
691 | #ifdef CONFIG_MACH_MX27 | |
692 | DEFINE_MXC_GPIO_PORTS(MX27, imx27); | |
fc80a5e3 | 693 | |
9a763bfb | 694 | int __init imx27_register_gpios(void) |
fc80a5e3 | 695 | { |
9a763bfb | 696 | return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports)); |
fc80a5e3 | 697 | } |
9a763bfb | 698 | #endif |
4e0fa90d MF |
699 | |
700 | #ifdef CONFIG_MACH_MX21 | |
701 | static struct resource mx21_usbhc_resources[] = { | |
702 | { | |
e1695307 WS |
703 | .start = MX21_USBOTG_BASE_ADDR, |
704 | .end = MX21_USBOTG_BASE_ADDR + SZ_8K - 1, | |
4e0fa90d MF |
705 | .flags = IORESOURCE_MEM, |
706 | }, | |
707 | { | |
988addf8 RK |
708 | .start = MX21_INT_USBHOST, |
709 | .end = MX21_INT_USBHOST, | |
4e0fa90d MF |
710 | .flags = IORESOURCE_IRQ, |
711 | }, | |
712 | }; | |
713 | ||
714 | struct platform_device mx21_usbhc_device = { | |
715 | .name = "imx21-hcd", | |
716 | .id = 0, | |
717 | .dev = { | |
718 | .dma_mask = &mx21_usbhc_device.dev.coherent_dma_mask, | |
719 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
720 | }, | |
721 | .num_resources = ARRAY_SIZE(mx21_usbhc_resources), | |
722 | .resource = mx21_usbhc_resources, | |
723 | }; | |
724 | #endif | |
07469495 | 725 | #endif |