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1 | /* |
2 | * Author: MontaVista Software, Inc. | |
3 | * <source@mvista.com> | |
4 | * | |
5 | * Based on the OMAP devices.c | |
6 | * | |
7 | * 2005 (c) MontaVista Software, Inc. This file is licensed under the | |
8 | * terms of the GNU General Public License version 2. This program is | |
9 | * licensed "as is" without any warranty of any kind, whether express | |
10 | * or implied. | |
11 | * | |
12 | * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
13 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | |
07469495 UKK |
14 | * Copyright 2008 Sascha Hauer, kernel@pengutronix.de |
15 | * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | |
16 | * Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt> | |
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17 | * |
18 | * This program is free software; you can redistribute it and/or | |
19 | * modify it under the terms of the GNU General Public License | |
20 | * as published by the Free Software Foundation; either version 2 | |
21 | * of the License, or (at your option) any later version. | |
22 | * This program is distributed in the hope that it will be useful, | |
23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
25 | * GNU General Public License for more details. | |
26 | * | |
27 | * You should have received a copy of the GNU General Public License | |
28 | * along with this program; if not, write to the Free Software | |
29 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
30 | * MA 02110-1301, USA. | |
31 | */ | |
32 | #include <linux/module.h> | |
33 | #include <linux/kernel.h> | |
34 | #include <linux/init.h> | |
35 | #include <linux/platform_device.h> | |
36 | #include <linux/gpio.h> | |
3eb352c7 | 37 | #include <linux/dma-mapping.h> |
e9ec2a17 | 38 | #include <linux/serial.h> |
fc80a5e3 | 39 | |
80b02c17 | 40 | #include <mach/irqs.h> |
a09e64fb | 41 | #include <mach/hardware.h> |
058b7a6f | 42 | #include <mach/common.h> |
1a02be0e | 43 | #include <mach/mmc.h> |
058b7a6f | 44 | |
07469495 | 45 | #if defined(CONFIG_ARCH_MX1) |
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46 | /* GPIO port description */ |
47 | static struct mxc_gpio_port imx_gpio_ports[] = { | |
48 | { | |
49 | .chip.label = "gpio-0", | |
cf3a6aba | 50 | .base = MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR), |
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51 | .irq = MX1_GPIO_INT_PORTA, |
52 | .virtual_irq_start = MXC_GPIO_IRQ_START, | |
53 | }, { | |
54 | .chip.label = "gpio-1", | |
cf3a6aba | 55 | .base = MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x100), |
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56 | .irq = MX1_GPIO_INT_PORTB, |
57 | .virtual_irq_start = MXC_GPIO_IRQ_START + 32, | |
58 | }, { | |
59 | .chip.label = "gpio-2", | |
cf3a6aba | 60 | .base = MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x200), |
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61 | .irq = MX1_GPIO_INT_PORTC, |
62 | .virtual_irq_start = MXC_GPIO_IRQ_START + 64, | |
63 | }, { | |
64 | .chip.label = "gpio-3", | |
cf3a6aba | 65 | .base = MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x300), |
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66 | .irq = MX1_GPIO_INT_PORTD, |
67 | .virtual_irq_start = MXC_GPIO_IRQ_START + 96, | |
68 | } | |
69 | }; | |
70 | ||
71 | int __init imx1_register_gpios(void) | |
72 | { | |
73 | return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); | |
74 | } | |
75 | #endif | |
76 | ||
9d3d945a | 77 | #if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27) |
fc80a5e3 | 78 | /* GPIO port description */ |
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79 | #define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \ |
80 | { \ | |
81 | .chip.label = "gpio-" #n, \ | |
82 | .irq = _irq, \ | |
83 | .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \ | |
84 | n * 0x100), \ | |
85 | .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \ | |
86 | } | |
87 | ||
88 | #define DEFINE_MXC_GPIO_PORT(SOC, n) \ | |
89 | { \ | |
90 | .chip.label = "gpio-" #n, \ | |
91 | .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \ | |
92 | n * 0x100), \ | |
93 | .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \ | |
fc80a5e3 | 94 | } |
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95 | |
96 | #define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \ | |
97 | static struct mxc_gpio_port pfx ## _gpio_ports[] = { \ | |
98 | DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \ | |
99 | DEFINE_MXC_GPIO_PORT(SOC, 1), \ | |
100 | DEFINE_MXC_GPIO_PORT(SOC, 2), \ | |
101 | DEFINE_MXC_GPIO_PORT(SOC, 3), \ | |
102 | DEFINE_MXC_GPIO_PORT(SOC, 4), \ | |
103 | DEFINE_MXC_GPIO_PORT(SOC, 5), \ | |
104 | } | |
105 | ||
106 | #ifdef CONFIG_MACH_MX21 | |
107 | DEFINE_MXC_GPIO_PORTS(MX21, imx21); | |
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108 | |
109 | int __init imx21_register_gpios(void) | |
110 | { | |
111 | return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports)); | |
112 | } | |
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113 | #endif |
114 | ||
115 | #ifdef CONFIG_MACH_MX27 | |
116 | DEFINE_MXC_GPIO_PORTS(MX27, imx27); | |
fc80a5e3 | 117 | |
9a763bfb | 118 | int __init imx27_register_gpios(void) |
fc80a5e3 | 119 | { |
9a763bfb | 120 | return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports)); |
fc80a5e3 | 121 | } |
9a763bfb | 122 | #endif |
4e0fa90d | 123 | |
07469495 | 124 | #endif |