[deliverable/linux.git] / arch / arm / mach-imx / devices.c

/*
 * Author: MontaVista Software, Inc.
 *       <source@mvista.com>
 *
 * Based on the OMAP devices.c
 *
 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
 * terms of the GNU General Public License version 2. This program is
 * licensed "as is" without any warranty of any kind, whether express
 * or implied.
 *
 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/dma-mapping.h>
#include <linux/serial.h>

#include <mach/irqs.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/mmc.h>
#include <mach/imx-uart.h>

#include "devices.h"

/*
 * SPI master controller
 *
 * - i.MX1: 2 channel (slighly different register setting)
 * - i.MX21: 2 channel
 * - i.MX27: 3 channel
 */
#define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq)					\
	static struct resource mxc_spi_resources ## n[] = {			\
		{								\
			.start = baseaddr,					\
			.end = baseaddr + SZ_4K - 1,				\
			.flags = IORESOURCE_MEM,				\
		}, {								\
			.start = irq,						\
			.end = irq,						\
			.flags = IORESOURCE_IRQ,				\
		},								\
	};									\
										\
	struct platform_device mxc_spi_device ## n = {				\
		.name = "spi_imx",						\
		.id = n,							\
		.num_resources = ARRAY_SIZE(mxc_spi_resources ## n),		\
		.resource = mxc_spi_resources ## n,				\
	}

DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1);
DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2);

#ifdef CONFIG_MACH_MX27
DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3);
#endif

/*
 * General Purpose Timer
 * - i.MX21: 3 timers
 * - i.MX27: 6 timers
 */
#define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq)				\
	static struct resource timer ## n ##_resources[] = {		\
		{							\
			.start = baseaddr,				\
			.end = baseaddr + SZ_4K - 1,			\
			.flags = IORESOURCE_MEM,			\
		}, {							\
			.start = irq,					\
			.end = irq,					\
			.flags = IORESOURCE_IRQ,			\
		}							\
	};								\
									\
	struct platform_device mxc_gpt ## n = {				\
		.name = "imx_gpt",					\
		.id = n,						\
		.num_resources = ARRAY_SIZE(timer ## n ## _resources),	\
		.resource = timer ## n ## _resources,			\
	}

/* We use gpt1 as system timer, so do not add a device for this one */
DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2);
DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3);

#ifdef CONFIG_MACH_MX27
DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4);
DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
#endif

/* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */
static struct resource mxc_wdt_resources[] = {
	{
		.start = MX2x_WDOG_BASE_ADDR,
		.end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
};

struct platform_device mxc_wdt = {
	.name = "imx2-wdt",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_wdt_resources),
	.resource = mxc_wdt_resources,
};

static struct resource mxc_w1_master_resources[] = {
	{
		.start = MX2x_OWIRE_BASE_ADDR,
		.end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
};

struct platform_device mxc_w1_master_device = {
	.name = "mxc_w1",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
	.resource = mxc_w1_master_resources,
};

#define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq)			\
	static struct resource pfx ## _nand_resources[] = {		\
		{							\
			.start = baseaddr,				\
			.end = baseaddr + SZ_4K - 1,			\
			.flags = IORESOURCE_MEM,			\
		}, {							\
			.start = irq,					\
			.end = irq,					\
			.flags = IORESOURCE_IRQ,			\
		},							\
	};								\
									\
	struct platform_device pfx ## _nand_device = {			\
		.name = "mxc_nand",					\
		.id = 0,						\
		.num_resources = ARRAY_SIZE(pfx ## _nand_resources),	\
		.resource = pfx ## _nand_resources,			\
	}

#ifdef CONFIG_MACH_MX21
DEFINE_MXC_NAND_DEVICE(imx21, MX21_NFC_BASE_ADDR, MX21_INT_NANDFC);
#endif

#ifdef CONFIG_MACH_MX27
DEFINE_MXC_NAND_DEVICE(imx27, MX27_NFC_BASE_ADDR, MX27_INT_NANDFC);
#endif

/*
 * lcdc:
 * - i.MX1: the basic controller
 * - i.MX21: to be checked
 * - i.MX27: like i.MX1, with slightly variations
 */
static struct resource mxc_fb[] = {
	{
		.start = MX2x_LCDC_BASE_ADDR,
		.end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MX2x_INT_LCDC,
		.end = MX2x_INT_LCDC,
		.flags = IORESOURCE_IRQ,
	}
};

/* mxc lcd driver */
struct platform_device mxc_fb_device = {
	.name = "imx-fb",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_fb),
	.resource = mxc_fb,
	.dev = {
		.coherent_dma_mask = DMA_BIT_MASK(32),
	},
};

#ifdef CONFIG_MACH_MX27
static struct resource mxc_fec_resources[] = {
	{
		.start = MX27_FEC_BASE_ADDR,
		.end = MX27_FEC_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MX27_INT_FEC,
		.end = MX27_INT_FEC,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_fec_device = {
	.name = "fec",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_fec_resources),
	.resource = mxc_fec_resources,
};
#endif

#define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq)				\
	static struct resource mxc_i2c_resources ## n[] = {		\
		{							\
			.start = baseaddr,				\
			.end = baseaddr + SZ_4K - 1,			\
			.flags = IORESOURCE_MEM,			\
		}, {							\
			.start = irq,					\
			.end = irq,					\
			.flags = IORESOURCE_IRQ,			\
		}							\
	};								\
									\
	struct platform_device mxc_i2c_device ## n = {			\
		.name = "imx-i2c",					\
		.id = n,						\
		.num_resources = ARRAY_SIZE(mxc_i2c_resources ## n),	\
		.resource = mxc_i2c_resources ## n,			\
	}

DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C);

#ifdef CONFIG_MACH_MX27
DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2);
#endif

static struct resource mxc_pwm_resources[] = {
	{
		.start = MX2x_PWM_BASE_ADDR,
		.end = MX2x_PWM_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MX2x_INT_PWM,
		.end = MX2x_INT_PWM,
		.flags = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_pwm_device = {
	.name = "mxc_pwm",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_pwm_resources),
	.resource = mxc_pwm_resources,
};

#define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq)			\
	static struct resource mxc_sdhc_resources ## n[] = {		\
		{							\
			.start = baseaddr,				\
			.end = baseaddr + SZ_4K - 1,			\
			.flags = IORESOURCE_MEM,			\
		}, {							\
			.start = irq,					\
			.end = irq,					\
			.flags = IORESOURCE_IRQ,			\
		}, {							\
			.start = dmareq,				\
			.end = dmareq,					\
			.flags = IORESOURCE_DMA,			\
		},							\
	};								\
									\
	static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32);	\
									\
	struct platform_device mxc_sdhc_device ## n = {			\
		.name = "mxc-mmc",					\
		.id = n,						\
		.dev = {						\
			.dma_mask = &mxc_sdhc ## n ## _dmamask,		\
			.coherent_dma_mask = DMA_BIT_MASK(32),		\
		},							\
		.num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n),	\
		.resource = mxc_sdhc_resources ## n,		\
	}

DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1);
DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2);

#ifdef CONFIG_MACH_MX27
static struct resource otg_resources[] = {
	{
		.start = MX27_USBOTG_BASE_ADDR,
		.end = MX27_USBOTG_BASE_ADDR + 0x1ff,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MX27_INT_USB3,
		.end = MX27_INT_USB3,
		.flags = IORESOURCE_IRQ,
	},
};

static u64 otg_dmamask = DMA_BIT_MASK(32);

/* OTG gadget device */
struct platform_device mxc_otg_udc_device = {
	.name		= "fsl-usb2-udc",
	.id		= -1,
	.dev		= {
		.dma_mask		= &otg_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
	.resource	= otg_resources,
	.num_resources	= ARRAY_SIZE(otg_resources),
};

/* OTG host */
struct platform_device mxc_otg_host = {
	.name = "mxc-ehci",
	.id = 0,
	.dev = {
		.coherent_dma_mask = DMA_BIT_MASK(32),
		.dma_mask = &otg_dmamask,
	},
	.resource = otg_resources,
	.num_resources = ARRAY_SIZE(otg_resources),
};

/* USB host 1 */

static u64 usbh1_dmamask = DMA_BIT_MASK(32);

static struct resource mxc_usbh1_resources[] = {
	{
		.start = MX27_USBOTG_BASE_ADDR + 0x200,
		.end = MX27_USBOTG_BASE_ADDR + 0x3ff,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MX27_INT_USB1,
		.end = MX27_INT_USB1,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_usbh1 = {
	.name = "mxc-ehci",
	.id = 1,
	.dev = {
		.coherent_dma_mask = DMA_BIT_MASK(32),
		.dma_mask = &usbh1_dmamask,
	},
	.resource = mxc_usbh1_resources,
	.num_resources = ARRAY_SIZE(mxc_usbh1_resources),
};

/* USB host 2 */
static u64 usbh2_dmamask = DMA_BIT_MASK(32);

static struct resource mxc_usbh2_resources[] = {
	{
		.start = MX27_USBOTG_BASE_ADDR + 0x400,
		.end = MX27_USBOTG_BASE_ADDR + 0x5ff,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MX27_INT_USB2,
		.end = MX27_INT_USB2,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_usbh2 = {
	.name = "mxc-ehci",
	.id = 2,
	.dev = {
		.coherent_dma_mask = DMA_BIT_MASK(32),
		.dma_mask = &usbh2_dmamask,
	},
	.resource = mxc_usbh2_resources,
	.num_resources = ARRAY_SIZE(mxc_usbh2_resources),
};
#endif

#define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix)			\
	{								\
		.name = _name,						\
		.start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix,	\
		.end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix,		\
		.flags = IORESOURCE_DMA,				\
	}

#define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq)			\
	static struct resource imx_ssi_resources ## n[] = {		\
		{							\
			.start = MX2x_SSI ## ssin ## _BASE_ADDR,	\
			.end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f,	\
			.flags = IORESOURCE_MEM,			\
		}, {							\
			.start = MX2x_INT_SSI1,				\
			.end = MX2x_INT_SSI1,				\
			.flags = IORESOURCE_IRQ,			\
		},							\
		DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0),		\
		DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0),		\
		DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1),		\
		DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1),		\
	};								\
									\
	struct platform_device imx_ssi_device ## n = {			\
		.name = "imx-ssi",					\
		.id = n,						\
		.num_resources = ARRAY_SIZE(imx_ssi_resources ## n),	\
		.resource = imx_ssi_resources ## n,			\
	}

DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);

#define DEFINE_IMX_UART_DEVICE(n, baseaddr, irq)			\
	static struct resource imx2x_uart_resources ## n[] = {		\
		{							\
			.start = baseaddr,				\
			.end = baseaddr + 0xb5,				\
			.flags = IORESOURCE_MEM,			\
		}, {							\
			.start = irq,					\
			.end = irq,					\
			.flags = IORESOURCE_IRQ,			\
		},							\
	};								\
									\
	struct platform_device mxc_uart_device ## n = {			\
		.name = "imx-uart",					\
		.id = n,						\
		.num_resources = ARRAY_SIZE(imx2x_uart_resources ## n),	\
		.resource = imx2x_uart_resources ## n,			\
	}

DEFINE_IMX_UART_DEVICE(0, MX2x_UART1_BASE_ADDR, MX2x_INT_UART1);
DEFINE_IMX_UART_DEVICE(1, MX2x_UART2_BASE_ADDR, MX2x_INT_UART2);
DEFINE_IMX_UART_DEVICE(2, MX2x_UART3_BASE_ADDR, MX2x_INT_UART3);
DEFINE_IMX_UART_DEVICE(3, MX2x_UART4_BASE_ADDR, MX2x_INT_UART4);

#ifdef CONFIG_MACH_MX27
DEFINE_IMX_UART_DEVICE(4, MX27_UART5_BASE_ADDR, MX27_INT_UART5);
DEFINE_IMX_UART_DEVICE(5, MX27_UART6_BASE_ADDR, MX27_INT_UART6);
#endif

/* GPIO port description */
#define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq)				\
	{								\
		.chip.label = "gpio-" #n,				\
		.irq = _irq,						\
		.base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR +	\
				n * 0x100),				\
		.virtual_irq_start = MXC_GPIO_IRQ_START + n * 32,	\
	}

#define DEFINE_MXC_GPIO_PORT(SOC, n)					\
	{								\
		.chip.label = "gpio-" #n,				\
		.base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR +	\
				n * 0x100),				\
		.virtual_irq_start = MXC_GPIO_IRQ_START + n * 32,	\
	}

#define DEFINE_MXC_GPIO_PORTS(SOC, pfx)					\
	static struct mxc_gpio_port pfx ## _gpio_ports[] = {		\
		DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO),	\
		DEFINE_MXC_GPIO_PORT(SOC, 1),				\
		DEFINE_MXC_GPIO_PORT(SOC, 2),				\
		DEFINE_MXC_GPIO_PORT(SOC, 3),				\
		DEFINE_MXC_GPIO_PORT(SOC, 4),				\
		DEFINE_MXC_GPIO_PORT(SOC, 5),				\
	}

#ifdef CONFIG_MACH_MX21
DEFINE_MXC_GPIO_PORTS(MX21, imx21);

int __init imx21_register_gpios(void)
{
	return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
}
#endif

#ifdef CONFIG_MACH_MX27
DEFINE_MXC_GPIO_PORTS(MX27, imx27);

int __init imx27_register_gpios(void)
{
	return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
}
#endif

#ifdef CONFIG_MACH_MX21
static struct resource mx21_usbhc_resources[] = {
	{
		.start	= MX21_USBOTG_BASE_ADDR,
		.end	= MX21_USBOTG_BASE_ADDR + SZ_8K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start		= MX21_INT_USBHOST,
		.end		= MX21_INT_USBHOST,
		.flags		= IORESOURCE_IRQ,
	},
};

struct platform_device mx21_usbhc_device = {
	.name		= "imx21-hcd",
	.id		= 0,
	.dev		= {
		.dma_mask = &mx21_usbhc_device.dev.coherent_dma_mask,
		.coherent_dma_mask = DMA_BIT_MASK(32),
	},
	.num_resources	= ARRAY_SIZE(mx21_usbhc_resources),
	.resource	= mx21_usbhc_resources,
};
#endif
Commit	Line	Data
fc80a5e3 JB	1	/*
	2	* Author: MontaVista Software, Inc.
	3	* <source@mvista.com>
	4	*
	5	* Based on the OMAP devices.c
	6	*
	7	* 2005 (c) MontaVista Software, Inc. This file is licensed under the
	8	* terms of the GNU General Public License version 2. This program is
	9	* licensed "as is" without any warranty of any kind, whether express
	10	* or implied.
	11	*
	12	* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	13	* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License
	17	* as published by the Free Software Foundation; either version 2
	18	* of the License, or (at your option) any later version.
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	27	* MA 02110-1301, USA.
	28	*/
	29	#include <linux/module.h>
	30	#include <linux/kernel.h>
	31	#include <linux/init.h>
	32	#include <linux/platform_device.h>
	33	#include <linux/gpio.h>
3eb352c7	34	#include <linux/dma-mapping.h>
e9ec2a17	35	#include <linux/serial.h>
fc80a5e3	36
80b02c17	37	#include <mach/irqs.h>
a09e64fb	38	#include <mach/hardware.h>
058b7a6f	39	#include <mach/common.h>
1a02be0e	40	#include <mach/mmc.h>
e9ec2a17	41	#include <mach/imx-uart.h>
058b7a6f HS	42
058b7a6f HS	43	#include "devices.h"
fc80a5e3	44
f420db84 SH	45	/*
	46	* SPI master controller
	47	*
	48	* - i.MX1: 2 channel (slighly different register setting)
	49	* - i.MX21: 2 channel
	50	* - i.MX27: 3 channel
	51	*/
68c94b40 UKK	52	#define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq) \
	53	static struct resource mxc_spi_resources ## n[] = { \
	54	{ \
	55	.start = baseaddr, \
	56	.end = baseaddr + SZ_4K - 1, \
	57	.flags = IORESOURCE_MEM, \
	58	}, { \
	59	.start = irq, \
	60	.end = irq, \
	61	.flags = IORESOURCE_IRQ, \
	62	}, \
	63	}; \
	64	\
	65	struct platform_device mxc_spi_device ## n = { \
	66	.name = "spi_imx", \
	67	.id = n, \
	68	.num_resources = ARRAY_SIZE(mxc_spi_resources ## n), \
	69	.resource = mxc_spi_resources ## n, \
	70	}
f420db84	71
68c94b40 UKK	72	DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1);
68c94b40 UKK	73	DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2);
f420db84 SH	74
f420db84 SH	75	#ifdef CONFIG_MACH_MX27
68c94b40	76	DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3);
f420db84 SH	77	#endif
f420db84 SH	78
fc80a5e3 JB	79	/*
fc80a5e3 JB	80	* General Purpose Timer
bf50bcc2 SH	81	* - i.MX21: 3 timers
bf50bcc2 SH	82	* - i.MX27: 6 timers
fc80a5e3	83	*/
2b84a364 UKK	84	#define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \
	85	static struct resource timer ## n ##_resources[] = { \
	86	{ \
	87	.start = baseaddr, \
	88	.end = baseaddr + SZ_4K - 1, \
	89	.flags = IORESOURCE_MEM, \
	90	}, { \
	91	.start = irq, \
	92	.end = irq, \
	93	.flags = IORESOURCE_IRQ, \
	94	} \
	95	}; \
	96	\
	97	struct platform_device mxc_gpt ## n = { \
	98	.name = "imx_gpt", \
	99	.id = n, \
	100	.num_resources = ARRAY_SIZE(timer ## n ## _resources), \
	101	.resource = timer ## n ## _resources, \
fc80a5e3	102	}
fc80a5e3	103
2b84a364 UKK	104	/* We use gpt1 as system timer, so do not add a device for this one */
	105	DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2);
	106	DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3);
fc80a5e3 JB	107
fc80a5e3 JB	108	#ifdef CONFIG_MACH_MX27
2b84a364 UKK	109	DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4);
	110	DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
	111	DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
fc80a5e3 JB	112	#endif
fc80a5e3 JB	113
6d38c1cf	114	/* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */
fc80a5e3 JB	115	static struct resource mxc_wdt_resources[] = {
fc80a5e3 JB	116	{
58152a16 UKK	117	.start = MX2x_WDOG_BASE_ADDR,
	118	.end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1,
	119	.flags = IORESOURCE_MEM,
fc80a5e3 JB	120	},
	121	};
	122
	123	struct platform_device mxc_wdt = {
6d38c1cf	124	.name = "imx2-wdt",
fc80a5e3 JB	125	.id = 0,
	126	.num_resources = ARRAY_SIZE(mxc_wdt_resources),
	127	.resource = mxc_wdt_resources,
	128	};
	129
3d89baa7 SH	130	static struct resource mxc_w1_master_resources[] = {
3d89baa7 SH	131	{
58152a16 UKK	132	.start = MX2x_OWIRE_BASE_ADDR,
58152a16 UKK	133	.end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1,
3d89baa7 SH	134	.flags = IORESOURCE_MEM,
	135	},
	136	};
	137
	138	struct platform_device mxc_w1_master_device = {
	139	.name = "mxc_w1",
	140	.id = 0,
	141	.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
	142	.resource = mxc_w1_master_resources,
	143	};
	144
f0d3ab49 UKK	145	#define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq) \
	146	static struct resource pfx ## _nand_resources[] = { \
	147	{ \
	148	.start = baseaddr, \
	149	.end = baseaddr + SZ_4K - 1, \
	150	.flags = IORESOURCE_MEM, \
	151	}, { \
	152	.start = irq, \
	153	.end = irq, \
	154	.flags = IORESOURCE_IRQ, \
	155	}, \
	156	}; \
	157	\
	158	struct platform_device pfx ## _nand_device = { \
	159	.name = "mxc_nand", \
	160	.id = 0, \
	161	.num_resources = ARRAY_SIZE(pfx ## _nand_resources), \
	162	.resource = pfx ## _nand_resources, \
	163	}
02870978	164
f0d3ab49 UKK	165	#ifdef CONFIG_MACH_MX21
	166	DEFINE_MXC_NAND_DEVICE(imx21, MX21_NFC_BASE_ADDR, MX21_INT_NANDFC);
	167	#endif
	168
	169	#ifdef CONFIG_MACH_MX27
	170	DEFINE_MXC_NAND_DEVICE(imx27, MX27_NFC_BASE_ADDR, MX27_INT_NANDFC);
	171	#endif
02870978	172
e4813551 HS	173	/*
	174	* lcdc:
	175	* - i.MX1: the basic controller
	176	* - i.MX21: to be checked
	177	* - i.MX27: like i.MX1, with slightly variations
	178	*/
	179	static struct resource mxc_fb[] = {
	180	{
58152a16 UKK	181	.start = MX2x_LCDC_BASE_ADDR,
58152a16 UKK	182	.end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1,
e4813551	183	.flags = IORESOURCE_MEM,
bf50bcc2	184	}, {
58152a16 UKK	185	.start = MX2x_INT_LCDC,
58152a16 UKK	186	.end = MX2x_INT_LCDC,
e4813551 HS	187	.flags = IORESOURCE_IRQ,
	188	}
	189	};
	190
	191	/* mxc lcd driver */
	192	struct platform_device mxc_fb_device = {
	193	.name = "imx-fb",
	194	.id = 0,
	195	.num_resources = ARRAY_SIZE(mxc_fb),
	196	.resource = mxc_fb,
	197	.dev = {
3eb352c7	198	.coherent_dma_mask = DMA_BIT_MASK(32),
e4813551 HS	199	},
	200	};
	201
879fea1b SH	202	#ifdef CONFIG_MACH_MX27
	203	static struct resource mxc_fec_resources[] = {
	204	{
58152a16 UKK	205	.start = MX27_FEC_BASE_ADDR,
	206	.end = MX27_FEC_BASE_ADDR + SZ_4K - 1,
	207	.flags = IORESOURCE_MEM,
879fea1b	208	}, {
58152a16 UKK	209	.start = MX27_INT_FEC,
	210	.end = MX27_INT_FEC,
	211	.flags = IORESOURCE_IRQ,
879fea1b SH	212	},
	213	};
	214
	215	struct platform_device mxc_fec_device = {
	216	.name = "fec",
	217	.id = 0,
	218	.num_resources = ARRAY_SIZE(mxc_fec_resources),
	219	.resource = mxc_fec_resources,
	220	};
e4813551 HS	221	#endif
e4813551 HS	222
9309b2ba UKK	223	#define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq) \
	224	static struct resource mxc_i2c_resources ## n[] = { \
	225	{ \
	226	.start = baseaddr, \
	227	.end = baseaddr + SZ_4K - 1, \
	228	.flags = IORESOURCE_MEM, \
	229	}, { \
	230	.start = irq, \
	231	.end = irq, \
	232	.flags = IORESOURCE_IRQ, \
	233	} \
	234	}; \
	235	\
	236	struct platform_device mxc_i2c_device ## n = { \
	237	.name = "imx-i2c", \
	238	.id = n, \
	239	.num_resources = ARRAY_SIZE(mxc_i2c_resources ## n), \
	240	.resource = mxc_i2c_resources ## n, \
c5d4dbff	241	}
c5d4dbff	242
9309b2ba	243	DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C);
c5d4dbff SH	244
c5d4dbff SH	245	#ifdef CONFIG_MACH_MX27
9309b2ba	246	DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2);
c5d4dbff SH	247	#endif
c5d4dbff SH	248
824b16e6	249	static struct resource mxc_pwm_resources[] = {
bf50bcc2	250	{
58152a16 UKK	251	.start = MX2x_PWM_BASE_ADDR,
	252	.end = MX2x_PWM_BASE_ADDR + SZ_4K - 1,
	253	.flags = IORESOURCE_MEM,
bf50bcc2	254	}, {
58152a16 UKK	255	.start = MX2x_INT_PWM,
	256	.end = MX2x_INT_PWM,
	257	.flags = IORESOURCE_IRQ,
824b16e6 SH	258	}
	259	};
	260
	261	struct platform_device mxc_pwm_device = {
	262	.name = "mxc_pwm",
	263	.id = 0,
	264	.num_resources = ARRAY_SIZE(mxc_pwm_resources),
bf50bcc2	265	.resource = mxc_pwm_resources,
824b16e6 SH	266	};
824b16e6 SH	267
ccd0e42c UKK	268	#define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \
	269	static struct resource mxc_sdhc_resources ## n[] = { \
	270	{ \
	271	.start = baseaddr, \
	272	.end = baseaddr + SZ_4K - 1, \
	273	.flags = IORESOURCE_MEM, \
	274	}, { \
	275	.start = irq, \
	276	.end = irq, \
	277	.flags = IORESOURCE_IRQ, \
	278	}, { \
	279	.start = dmareq, \
	280	.end = dmareq, \
	281	.flags = IORESOURCE_DMA, \
	282	}, \
	283	}; \
	284	\
988addf8	285	static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32); \
ccd0e42c UKK	286	\
	287	struct platform_device mxc_sdhc_device ## n = { \
	288	.name = "mxc-mmc", \
	289	.id = n, \
	290	.dev = { \
	291	.dma_mask = &mxc_sdhc ## n ## _dmamask, \
988addf8	292	.coherent_dma_mask = DMA_BIT_MASK(32), \
ccd0e42c UKK	293	}, \
	294	.num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \
	295	.resource = mxc_sdhc_resources ## n, \
	296	}
1a02be0e	297
ccd0e42c UKK	298	DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1);
ccd0e42c UKK	299	DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2);
1a02be0e	300
f6d2fa7d	301	#ifdef CONFIG_MACH_MX27
627fb3b9 M	302	static struct resource otg_resources[] = {
627fb3b9 M	303	{
58152a16 UKK	304	.start = MX27_USBOTG_BASE_ADDR,
	305	.end = MX27_USBOTG_BASE_ADDR + 0x1ff,
	306	.flags = IORESOURCE_MEM,
627fb3b9	307	}, {
58152a16 UKK	308	.start = MX27_INT_USB3,
	309	.end = MX27_INT_USB3,
	310	.flags = IORESOURCE_IRQ,
627fb3b9 M	311	},
	312	};
	313
3eb352c7	314	static u64 otg_dmamask = DMA_BIT_MASK(32);
627fb3b9 M	315
	316	/* OTG gadget device */
	317	struct platform_device mxc_otg_udc_device = {
	318	.name = "fsl-usb2-udc",
	319	.id = -1,
	320	.dev = {
	321	.dma_mask = &otg_dmamask,
3eb352c7	322	.coherent_dma_mask = DMA_BIT_MASK(32),
627fb3b9 M	323	},
	324	.resource = otg_resources,
	325	.num_resources = ARRAY_SIZE(otg_resources),
	326	};
	327
	328	/* OTG host */
	329	struct platform_device mxc_otg_host = {
	330	.name = "mxc-ehci",
	331	.id = 0,
	332	.dev = {
3eb352c7	333	.coherent_dma_mask = DMA_BIT_MASK(32),
627fb3b9 M	334	.dma_mask = &otg_dmamask,
	335	},
	336	.resource = otg_resources,
	337	.num_resources = ARRAY_SIZE(otg_resources),
	338	};
	339
	340	/* USB host 1 */
	341
3eb352c7	342	static u64 usbh1_dmamask = DMA_BIT_MASK(32);
627fb3b9 M	343
	344	static struct resource mxc_usbh1_resources[] = {
	345	{
58152a16 UKK	346	.start = MX27_USBOTG_BASE_ADDR + 0x200,
58152a16 UKK	347	.end = MX27_USBOTG_BASE_ADDR + 0x3ff,
627fb3b9 M	348	.flags = IORESOURCE_MEM,
627fb3b9 M	349	}, {
58152a16 UKK	350	.start = MX27_INT_USB1,
58152a16 UKK	351	.end = MX27_INT_USB1,
627fb3b9 M	352	.flags = IORESOURCE_IRQ,
	353	},
	354	};
	355
	356	struct platform_device mxc_usbh1 = {
	357	.name = "mxc-ehci",
	358	.id = 1,
	359	.dev = {
3eb352c7	360	.coherent_dma_mask = DMA_BIT_MASK(32),
627fb3b9 M	361	.dma_mask = &usbh1_dmamask,
	362	},
	363	.resource = mxc_usbh1_resources,
	364	.num_resources = ARRAY_SIZE(mxc_usbh1_resources),
	365	};
	366
	367	/* USB host 2 */
3eb352c7	368	static u64 usbh2_dmamask = DMA_BIT_MASK(32);
627fb3b9 M	369
	370	static struct resource mxc_usbh2_resources[] = {
	371	{
58152a16 UKK	372	.start = MX27_USBOTG_BASE_ADDR + 0x400,
58152a16 UKK	373	.end = MX27_USBOTG_BASE_ADDR + 0x5ff,
627fb3b9 M	374	.flags = IORESOURCE_MEM,
627fb3b9 M	375	}, {
58152a16 UKK	376	.start = MX27_INT_USB2,
58152a16 UKK	377	.end = MX27_INT_USB2,
627fb3b9 M	378	.flags = IORESOURCE_IRQ,
	379	},
	380	};
	381
	382	struct platform_device mxc_usbh2 = {
	383	.name = "mxc-ehci",
	384	.id = 2,
	385	.dev = {
3eb352c7	386	.coherent_dma_mask = DMA_BIT_MASK(32),
627fb3b9 M	387	.dma_mask = &usbh2_dmamask,
	388	},
	389	.resource = mxc_usbh2_resources,
	390	.num_resources = ARRAY_SIZE(mxc_usbh2_resources),
	391	};
f6d2fa7d	392	#endif
627fb3b9	393
69ddb488 UKK	394	#define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \
	395	{ \
	396	.name = _name, \
	397	.start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
	398	.end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
	399	.flags = IORESOURCE_DMA, \
	400	}
23291df4	401
69ddb488 UKK	402	#define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \
	403	static struct resource imx_ssi_resources ## n[] = { \
	404	{ \
	405	.start = MX2x_SSI ## ssin ## _BASE_ADDR, \
	406	.end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \
	407	.flags = IORESOURCE_MEM, \
	408	}, { \
	409	.start = MX2x_INT_SSI1, \
	410	.end = MX2x_INT_SSI1, \
	411	.flags = IORESOURCE_IRQ, \
	412	}, \
	413	DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \
	414	DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \
	415	DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \
	416	DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \
	417	}; \
	418	\
	419	struct platform_device imx_ssi_device ## n = { \
	420	.name = "imx-ssi", \
	421	.id = n, \
	422	.num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \
	423	.resource = imx_ssi_resources ## n, \
	424	}
23291df4	425
69ddb488 UKK	426	DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
69ddb488 UKK	427	DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
23291df4	428
e9ec2a17 UKK	429	#define DEFINE_IMX_UART_DEVICE(n, baseaddr, irq) \
	430	static struct resource imx2x_uart_resources ## n[] = { \
	431	{ \
	432	.start = baseaddr, \
	433	.end = baseaddr + 0xb5, \
	434	.flags = IORESOURCE_MEM, \
	435	}, { \
	436	.start = irq, \
	437	.end = irq, \
	438	.flags = IORESOURCE_IRQ, \
	439	}, \
	440	}; \
	441	\
	442	struct platform_device mxc_uart_device ## n = { \
	443	.name = "imx-uart", \
	444	.id = n, \
	445	.num_resources = ARRAY_SIZE(imx2x_uart_resources ## n), \
	446	.resource = imx2x_uart_resources ## n, \
	447	}
	448
	449	DEFINE_IMX_UART_DEVICE(0, MX2x_UART1_BASE_ADDR, MX2x_INT_UART1);
	450	DEFINE_IMX_UART_DEVICE(1, MX2x_UART2_BASE_ADDR, MX2x_INT_UART2);
	451	DEFINE_IMX_UART_DEVICE(2, MX2x_UART3_BASE_ADDR, MX2x_INT_UART3);
	452	DEFINE_IMX_UART_DEVICE(3, MX2x_UART4_BASE_ADDR, MX2x_INT_UART4);
	453
	454	#ifdef CONFIG_MACH_MX27
	455	DEFINE_IMX_UART_DEVICE(4, MX27_UART5_BASE_ADDR, MX27_INT_UART5);
	456	DEFINE_IMX_UART_DEVICE(5, MX27_UART6_BASE_ADDR, MX27_INT_UART6);
	457	#endif
	458
fc80a5e3	459	/* GPIO port description */
897359d5 UKK	460	#define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
	461	{ \
	462	.chip.label = "gpio-" #n, \
	463	.irq = _irq, \
	464	.base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
	465	n * 0x100), \
	466	.virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
	467	}
	468
	469	#define DEFINE_MXC_GPIO_PORT(SOC, n) \
	470	{ \
	471	.chip.label = "gpio-" #n, \
	472	.base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
	473	n * 0x100), \
	474	.virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
fc80a5e3	475	}
897359d5 UKK	476
	477	#define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \
	478	static struct mxc_gpio_port pfx ## _gpio_ports[] = { \
	479	DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \
	480	DEFINE_MXC_GPIO_PORT(SOC, 1), \
	481	DEFINE_MXC_GPIO_PORT(SOC, 2), \
	482	DEFINE_MXC_GPIO_PORT(SOC, 3), \
	483	DEFINE_MXC_GPIO_PORT(SOC, 4), \
	484	DEFINE_MXC_GPIO_PORT(SOC, 5), \
	485	}
	486
	487	#ifdef CONFIG_MACH_MX21
	488	DEFINE_MXC_GPIO_PORTS(MX21, imx21);
9a763bfb UKK	489
	490	int __init imx21_register_gpios(void)
	491	{
	492	return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
	493	}
897359d5 UKK	494	#endif
	495
	496	#ifdef CONFIG_MACH_MX27
	497	DEFINE_MXC_GPIO_PORTS(MX27, imx27);
fc80a5e3	498
9a763bfb	499	int __init imx27_register_gpios(void)
fc80a5e3	500	{
9a763bfb	501	return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
fc80a5e3	502	}
9a763bfb	503	#endif
4e0fa90d MF	504
	505	#ifdef CONFIG_MACH_MX21
	506	static struct resource mx21_usbhc_resources[] = {
	507	{
e1695307 WS	508	.start = MX21_USBOTG_BASE_ADDR,
e1695307 WS	509	.end = MX21_USBOTG_BASE_ADDR + SZ_8K - 1,
4e0fa90d MF	510	.flags = IORESOURCE_MEM,
	511	},
	512	{
988addf8 RK	513	.start = MX21_INT_USBHOST,
988addf8 RK	514	.end = MX21_INT_USBHOST,
4e0fa90d MF	515	.flags = IORESOURCE_IRQ,
	516	},
	517	};
	518
	519	struct platform_device mx21_usbhc_device = {
	520	.name = "imx21-hcd",
	521	.id = 0,
	522	.dev = {
	523	.dma_mask = &mx21_usbhc_device.dev.coherent_dma_mask,
	524	.coherent_dma_mask = DMA_BIT_MASK(32),
	525	},
	526	.num_resources = ARRAY_SIZE(mx21_usbhc_resources),
	527	.resource = mx21_usbhc_resources,
	528	};
	529	#endif