[deliverable/linux.git] / arch / arm / mach-imx / devices.c

/*
 * Author: MontaVista Software, Inc.
 *       <source@mvista.com>
 *
 * Based on the OMAP devices.c
 *
 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
 * terms of the GNU General Public License version 2. This program is
 * licensed "as is" without any warranty of any kind, whether express
 * or implied.
 *
 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/dma-mapping.h>
#include <linux/serial.h>

#include <mach/irqs.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/mmc.h>

#include "devices.h"

/*
 * SPI master controller
 *
 * - i.MX1: 2 channel (slighly different register setting)
 * - i.MX21: 2 channel
 * - i.MX27: 3 channel
 */
#define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq)					\
	static struct resource mxc_spi_resources ## n[] = {			\
		{								\
			.start = baseaddr,					\
			.end = baseaddr + SZ_4K - 1,				\
			.flags = IORESOURCE_MEM,				\
		}, {								\
			.start = irq,						\
			.end = irq,						\
			.flags = IORESOURCE_IRQ,				\
		},								\
	};									\
										\
	struct platform_device mxc_spi_device ## n = {				\
		.name = "spi_imx",						\
		.id = n,							\
		.num_resources = ARRAY_SIZE(mxc_spi_resources ## n),		\
		.resource = mxc_spi_resources ## n,				\
	}

DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1);
DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2);

#ifdef CONFIG_MACH_MX27
DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3);
#endif

/*
 * General Purpose Timer
 * - i.MX21: 3 timers
 * - i.MX27: 6 timers
 */
#define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq)				\
	static struct resource timer ## n ##_resources[] = {		\
		{							\
			.start = baseaddr,				\
			.end = baseaddr + SZ_4K - 1,			\
			.flags = IORESOURCE_MEM,			\
		}, {							\
			.start = irq,					\
			.end = irq,					\
			.flags = IORESOURCE_IRQ,			\
		}							\
	};								\
									\
	struct platform_device mxc_gpt ## n = {				\
		.name = "imx_gpt",					\
		.id = n,						\
		.num_resources = ARRAY_SIZE(timer ## n ## _resources),	\
		.resource = timer ## n ## _resources,			\
	}

/* We use gpt1 as system timer, so do not add a device for this one */
DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2);
DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3);

#ifdef CONFIG_MACH_MX27
DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4);
DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
#endif

/* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */
static struct resource mxc_wdt_resources[] = {
	{
		.start = MX2x_WDOG_BASE_ADDR,
		.end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
};

struct platform_device mxc_wdt = {
	.name = "imx2-wdt",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_wdt_resources),
	.resource = mxc_wdt_resources,
};

static struct resource mxc_w1_master_resources[] = {
	{
		.start = MX2x_OWIRE_BASE_ADDR,
		.end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
};

struct platform_device mxc_w1_master_device = {
	.name = "mxc_w1",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
	.resource = mxc_w1_master_resources,
};

#define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq)			\
	static struct resource pfx ## _nand_resources[] = {		\
		{							\
			.start = baseaddr,				\
			.end = baseaddr + SZ_4K - 1,			\
			.flags = IORESOURCE_MEM,			\
		}, {							\
			.start = irq,					\
			.end = irq,					\
			.flags = IORESOURCE_IRQ,			\
		},							\
	};								\
									\
	struct platform_device pfx ## _nand_device = {			\
		.name = "mxc_nand",					\
		.id = 0,						\
		.num_resources = ARRAY_SIZE(pfx ## _nand_resources),	\
		.resource = pfx ## _nand_resources,			\
	}

#ifdef CONFIG_MACH_MX21
DEFINE_MXC_NAND_DEVICE(imx21, MX21_NFC_BASE_ADDR, MX21_INT_NANDFC);
#endif

#ifdef CONFIG_MACH_MX27
DEFINE_MXC_NAND_DEVICE(imx27, MX27_NFC_BASE_ADDR, MX27_INT_NANDFC);
#endif

/*
 * lcdc:
 * - i.MX1: the basic controller
 * - i.MX21: to be checked
 * - i.MX27: like i.MX1, with slightly variations
 */
static struct resource mxc_fb[] = {
	{
		.start = MX2x_LCDC_BASE_ADDR,
		.end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MX2x_INT_LCDC,
		.end = MX2x_INT_LCDC,
		.flags = IORESOURCE_IRQ,
	}
};

/* mxc lcd driver */
struct platform_device mxc_fb_device = {
	.name = "imx-fb",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_fb),
	.resource = mxc_fb,
	.dev = {
		.coherent_dma_mask = DMA_BIT_MASK(32),
	},
};

#ifdef CONFIG_MACH_MX27
static struct resource mxc_fec_resources[] = {
	{
		.start = MX27_FEC_BASE_ADDR,
		.end = MX27_FEC_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MX27_INT_FEC,
		.end = MX27_INT_FEC,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_fec_device = {
	.name = "fec",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_fec_resources),
	.resource = mxc_fec_resources,
};
#endif

#define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq)				\
	static struct resource mxc_i2c_resources ## n[] = {		\
		{							\
			.start = baseaddr,				\
			.end = baseaddr + SZ_4K - 1,			\
			.flags = IORESOURCE_MEM,			\
		}, {							\
			.start = irq,					\
			.end = irq,					\
			.flags = IORESOURCE_IRQ,			\
		}							\
	};								\
									\
	struct platform_device mxc_i2c_device ## n = {			\
		.name = "imx-i2c",					\
		.id = n,						\
		.num_resources = ARRAY_SIZE(mxc_i2c_resources ## n),	\
		.resource = mxc_i2c_resources ## n,			\
	}

DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C);

#ifdef CONFIG_MACH_MX27
DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2);
#endif

static struct resource mxc_pwm_resources[] = {
	{
		.start = MX2x_PWM_BASE_ADDR,
		.end = MX2x_PWM_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MX2x_INT_PWM,
		.end = MX2x_INT_PWM,
		.flags = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_pwm_device = {
	.name = "mxc_pwm",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_pwm_resources),
	.resource = mxc_pwm_resources,
};

#define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq)			\
	static struct resource mxc_sdhc_resources ## n[] = {		\
		{							\
			.start = baseaddr,				\
			.end = baseaddr + SZ_4K - 1,			\
			.flags = IORESOURCE_MEM,			\
		}, {							\
			.start = irq,					\
			.end = irq,					\
			.flags = IORESOURCE_IRQ,			\
		}, {							\
			.start = dmareq,				\
			.end = dmareq,					\
			.flags = IORESOURCE_DMA,			\
		},							\
	};								\
									\
	static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32);	\
									\
	struct platform_device mxc_sdhc_device ## n = {			\
		.name = "mxc-mmc",					\
		.id = n,						\
		.dev = {						\
			.dma_mask = &mxc_sdhc ## n ## _dmamask,		\
			.coherent_dma_mask = DMA_BIT_MASK(32),		\
		},							\
		.num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n),	\
		.resource = mxc_sdhc_resources ## n,		\
	}

DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1);
DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2);

#ifdef CONFIG_MACH_MX27
static struct resource otg_resources[] = {
	{
		.start = MX27_USBOTG_BASE_ADDR,
		.end = MX27_USBOTG_BASE_ADDR + 0x1ff,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MX27_INT_USB3,
		.end = MX27_INT_USB3,
		.flags = IORESOURCE_IRQ,
	},
};

static u64 otg_dmamask = DMA_BIT_MASK(32);

/* OTG gadget device */
struct platform_device mxc_otg_udc_device = {
	.name		= "fsl-usb2-udc",
	.id		= -1,
	.dev		= {
		.dma_mask		= &otg_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
	.resource	= otg_resources,
	.num_resources	= ARRAY_SIZE(otg_resources),
};

/* OTG host */
struct platform_device mxc_otg_host = {
	.name = "mxc-ehci",
	.id = 0,
	.dev = {
		.coherent_dma_mask = DMA_BIT_MASK(32),
		.dma_mask = &otg_dmamask,
	},
	.resource = otg_resources,
	.num_resources = ARRAY_SIZE(otg_resources),
};

/* USB host 1 */

static u64 usbh1_dmamask = DMA_BIT_MASK(32);

static struct resource mxc_usbh1_resources[] = {
	{
		.start = MX27_USBOTG_BASE_ADDR + 0x200,
		.end = MX27_USBOTG_BASE_ADDR + 0x3ff,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MX27_INT_USB1,
		.end = MX27_INT_USB1,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_usbh1 = {
	.name = "mxc-ehci",
	.id = 1,
	.dev = {
		.coherent_dma_mask = DMA_BIT_MASK(32),
		.dma_mask = &usbh1_dmamask,
	},
	.resource = mxc_usbh1_resources,
	.num_resources = ARRAY_SIZE(mxc_usbh1_resources),
};

/* USB host 2 */
static u64 usbh2_dmamask = DMA_BIT_MASK(32);

static struct resource mxc_usbh2_resources[] = {
	{
		.start = MX27_USBOTG_BASE_ADDR + 0x400,
		.end = MX27_USBOTG_BASE_ADDR + 0x5ff,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MX27_INT_USB2,
		.end = MX27_INT_USB2,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_usbh2 = {
	.name = "mxc-ehci",
	.id = 2,
	.dev = {
		.coherent_dma_mask = DMA_BIT_MASK(32),
		.dma_mask = &usbh2_dmamask,
	},
	.resource = mxc_usbh2_resources,
	.num_resources = ARRAY_SIZE(mxc_usbh2_resources),
};
#endif

#define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix)			\
	{								\
		.name = _name,						\
		.start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix,	\
		.end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix,		\
		.flags = IORESOURCE_DMA,				\
	}

#define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq)			\
	static struct resource imx_ssi_resources ## n[] = {		\
		{							\
			.start = MX2x_SSI ## ssin ## _BASE_ADDR,	\
			.end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f,	\
			.flags = IORESOURCE_MEM,			\
		}, {							\
			.start = MX2x_INT_SSI1,				\
			.end = MX2x_INT_SSI1,				\
			.flags = IORESOURCE_IRQ,			\
		},							\
		DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0),		\
		DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0),		\
		DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1),		\
		DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1),		\
	};								\
									\
	struct platform_device imx_ssi_device ## n = {			\
		.name = "imx-ssi",					\
		.id = n,						\
		.num_resources = ARRAY_SIZE(imx_ssi_resources ## n),	\
		.resource = imx_ssi_resources ## n,			\
	}

DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);

#define DEFINE_IMX2x_UART_DEVICE(n, baseaddr, irq)			\
	static struct resource imx2x_uart_resources ## n[] = {		\
		{							\
			.start = baseaddr,				\
			.end = baseaddr + 0xb5,				\
			.flags = IORESOURCE_MEM,			\
		}, {							\
			.start = irq,					\
			.end = irq,					\
			.flags = IORESOURCE_IRQ,			\
		},							\
	};								\
									\
	struct platform_device imx2x_uart_device ## n = {		\
		.name = "imx-uart",					\
		.id = n,						\
		.num_resources = ARRAY_SIZE(imx2x_uart_resources ## n),	\
		.resource = imx2x_uart_resources ## n,			\
	}

DEFINE_IMX2x_UART_DEVICE(0, MX2x_UART1_BASE_ADDR, MX2x_INT_UART1);
DEFINE_IMX2x_UART_DEVICE(1, MX2x_UART2_BASE_ADDR, MX2x_INT_UART2);
DEFINE_IMX2x_UART_DEVICE(2, MX2x_UART3_BASE_ADDR, MX2x_INT_UART3);
DEFINE_IMX2x_UART_DEVICE(3, MX2x_UART4_BASE_ADDR, MX2x_INT_UART4);

#ifdef CONFIG_MACH_MX27
DEFINE_IMX2x_UART_DEVICE(4, MX27_UART5_BASE_ADDR, MX27_INT_UART5);
DEFINE_IMX2x_UART_DEVICE(5, MX27_UART6_BASE_ADDR, MX27_INT_UART6);
#endif

/* GPIO port description */
#define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq)				\
	{								\
		.chip.label = "gpio-" #n,				\
		.irq = _irq,						\
		.base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR +	\
				n * 0x100),				\
		.virtual_irq_start = MXC_GPIO_IRQ_START + n * 32,	\
	}

#define DEFINE_MXC_GPIO_PORT(SOC, n)					\
	{								\
		.chip.label = "gpio-" #n,				\
		.base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR +	\
				n * 0x100),				\
		.virtual_irq_start = MXC_GPIO_IRQ_START + n * 32,	\
	}

#define DEFINE_MXC_GPIO_PORTS(SOC, pfx)					\
	static struct mxc_gpio_port pfx ## _gpio_ports[] = {		\
		DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO),	\
		DEFINE_MXC_GPIO_PORT(SOC, 1),				\
		DEFINE_MXC_GPIO_PORT(SOC, 2),				\
		DEFINE_MXC_GPIO_PORT(SOC, 3),				\
		DEFINE_MXC_GPIO_PORT(SOC, 4),				\
		DEFINE_MXC_GPIO_PORT(SOC, 5),				\
	}

#ifdef CONFIG_MACH_MX21
DEFINE_MXC_GPIO_PORTS(MX21, imx21);

int __init imx21_register_gpios(void)
{
	return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
}
#endif

#ifdef CONFIG_MACH_MX27
DEFINE_MXC_GPIO_PORTS(MX27, imx27);

int __init imx27_register_gpios(void)
{
	return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
}
#endif

#ifdef CONFIG_MACH_MX21
static struct resource mx21_usbhc_resources[] = {
	{
		.start	= MX21_USBOTG_BASE_ADDR,
		.end	= MX21_USBOTG_BASE_ADDR + SZ_8K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start		= MX21_INT_USBHOST,
		.end		= MX21_INT_USBHOST,
		.flags		= IORESOURCE_IRQ,
	},
};

struct platform_device mx21_usbhc_device = {
	.name		= "imx21-hcd",
	.id		= 0,
	.dev		= {
		.dma_mask = &mx21_usbhc_device.dev.coherent_dma_mask,
		.coherent_dma_mask = DMA_BIT_MASK(32),
	},
	.num_resources	= ARRAY_SIZE(mx21_usbhc_resources),
	.resource	= mx21_usbhc_resources,
};
#endif
Commit	Line	Data
fc80a5e3 JB	1	/*
	2	* Author: MontaVista Software, Inc.
	3	* <source@mvista.com>
	4	*
	5	* Based on the OMAP devices.c
	6	*
	7	* 2005 (c) MontaVista Software, Inc. This file is licensed under the
	8	* terms of the GNU General Public License version 2. This program is
	9	* licensed "as is" without any warranty of any kind, whether express
	10	* or implied.
	11	*
	12	* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	13	* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License
	17	* as published by the Free Software Foundation; either version 2
	18	* of the License, or (at your option) any later version.
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	27	* MA 02110-1301, USA.
	28	*/
	29	#include <linux/module.h>
	30	#include <linux/kernel.h>
	31	#include <linux/init.h>
	32	#include <linux/platform_device.h>
	33	#include <linux/gpio.h>
3eb352c7	34	#include <linux/dma-mapping.h>
e9ec2a17	35	#include <linux/serial.h>
fc80a5e3	36
80b02c17	37	#include <mach/irqs.h>
a09e64fb	38	#include <mach/hardware.h>
058b7a6f	39	#include <mach/common.h>
1a02be0e	40	#include <mach/mmc.h>
058b7a6f HS	41
058b7a6f HS	42	#include "devices.h"
fc80a5e3	43
f420db84 SH	44	/*
	45	* SPI master controller
	46	*
	47	* - i.MX1: 2 channel (slighly different register setting)
	48	* - i.MX21: 2 channel
	49	* - i.MX27: 3 channel
	50	*/
68c94b40 UKK	51	#define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq) \
	52	static struct resource mxc_spi_resources ## n[] = { \
	53	{ \
	54	.start = baseaddr, \
	55	.end = baseaddr + SZ_4K - 1, \
	56	.flags = IORESOURCE_MEM, \
	57	}, { \
	58	.start = irq, \
	59	.end = irq, \
	60	.flags = IORESOURCE_IRQ, \
	61	}, \
	62	}; \
	63	\
	64	struct platform_device mxc_spi_device ## n = { \
	65	.name = "spi_imx", \
	66	.id = n, \
	67	.num_resources = ARRAY_SIZE(mxc_spi_resources ## n), \
	68	.resource = mxc_spi_resources ## n, \
	69	}
f420db84	70
68c94b40 UKK	71	DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1);
68c94b40 UKK	72	DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2);
f420db84 SH	73
f420db84 SH	74	#ifdef CONFIG_MACH_MX27
68c94b40	75	DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3);
f420db84 SH	76	#endif
f420db84 SH	77
fc80a5e3 JB	78	/*
fc80a5e3 JB	79	* General Purpose Timer
bf50bcc2 SH	80	* - i.MX21: 3 timers
bf50bcc2 SH	81	* - i.MX27: 6 timers
fc80a5e3	82	*/
2b84a364 UKK	83	#define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \
	84	static struct resource timer ## n ##_resources[] = { \
	85	{ \
	86	.start = baseaddr, \
	87	.end = baseaddr + SZ_4K - 1, \
	88	.flags = IORESOURCE_MEM, \
	89	}, { \
	90	.start = irq, \
	91	.end = irq, \
	92	.flags = IORESOURCE_IRQ, \
	93	} \
	94	}; \
	95	\
	96	struct platform_device mxc_gpt ## n = { \
	97	.name = "imx_gpt", \
	98	.id = n, \
	99	.num_resources = ARRAY_SIZE(timer ## n ## _resources), \
	100	.resource = timer ## n ## _resources, \
fc80a5e3	101	}
fc80a5e3	102
2b84a364 UKK	103	/* We use gpt1 as system timer, so do not add a device for this one */
	104	DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2);
	105	DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3);
fc80a5e3 JB	106
fc80a5e3 JB	107	#ifdef CONFIG_MACH_MX27
2b84a364 UKK	108	DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4);
	109	DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
	110	DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
fc80a5e3 JB	111	#endif
fc80a5e3 JB	112
6d38c1cf	113	/* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */
fc80a5e3 JB	114	static struct resource mxc_wdt_resources[] = {
fc80a5e3 JB	115	{
58152a16 UKK	116	.start = MX2x_WDOG_BASE_ADDR,
	117	.end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1,
	118	.flags = IORESOURCE_MEM,
fc80a5e3 JB	119	},
	120	};
	121
	122	struct platform_device mxc_wdt = {
6d38c1cf	123	.name = "imx2-wdt",
fc80a5e3 JB	124	.id = 0,
	125	.num_resources = ARRAY_SIZE(mxc_wdt_resources),
	126	.resource = mxc_wdt_resources,
	127	};
	128
3d89baa7 SH	129	static struct resource mxc_w1_master_resources[] = {
3d89baa7 SH	130	{
58152a16 UKK	131	.start = MX2x_OWIRE_BASE_ADDR,
58152a16 UKK	132	.end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1,
3d89baa7 SH	133	.flags = IORESOURCE_MEM,
	134	},
	135	};
	136
	137	struct platform_device mxc_w1_master_device = {
	138	.name = "mxc_w1",
	139	.id = 0,
	140	.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
	141	.resource = mxc_w1_master_resources,
	142	};
	143
f0d3ab49 UKK	144	#define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq) \
	145	static struct resource pfx ## _nand_resources[] = { \
	146	{ \
	147	.start = baseaddr, \
	148	.end = baseaddr + SZ_4K - 1, \
	149	.flags = IORESOURCE_MEM, \
	150	}, { \
	151	.start = irq, \
	152	.end = irq, \
	153	.flags = IORESOURCE_IRQ, \
	154	}, \
	155	}; \
	156	\
	157	struct platform_device pfx ## _nand_device = { \
	158	.name = "mxc_nand", \
	159	.id = 0, \
	160	.num_resources = ARRAY_SIZE(pfx ## _nand_resources), \
	161	.resource = pfx ## _nand_resources, \
	162	}
02870978	163
f0d3ab49 UKK	164	#ifdef CONFIG_MACH_MX21
	165	DEFINE_MXC_NAND_DEVICE(imx21, MX21_NFC_BASE_ADDR, MX21_INT_NANDFC);
	166	#endif
	167
	168	#ifdef CONFIG_MACH_MX27
	169	DEFINE_MXC_NAND_DEVICE(imx27, MX27_NFC_BASE_ADDR, MX27_INT_NANDFC);
	170	#endif
02870978	171
e4813551 HS	172	/*
	173	* lcdc:
	174	* - i.MX1: the basic controller
	175	* - i.MX21: to be checked
	176	* - i.MX27: like i.MX1, with slightly variations
	177	*/
	178	static struct resource mxc_fb[] = {
	179	{
58152a16 UKK	180	.start = MX2x_LCDC_BASE_ADDR,
58152a16 UKK	181	.end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1,
e4813551	182	.flags = IORESOURCE_MEM,
bf50bcc2	183	}, {
58152a16 UKK	184	.start = MX2x_INT_LCDC,
58152a16 UKK	185	.end = MX2x_INT_LCDC,
e4813551 HS	186	.flags = IORESOURCE_IRQ,
	187	}
	188	};
	189
	190	/* mxc lcd driver */
	191	struct platform_device mxc_fb_device = {
	192	.name = "imx-fb",
	193	.id = 0,
	194	.num_resources = ARRAY_SIZE(mxc_fb),
	195	.resource = mxc_fb,
	196	.dev = {
3eb352c7	197	.coherent_dma_mask = DMA_BIT_MASK(32),
e4813551 HS	198	},
	199	};
	200
879fea1b SH	201	#ifdef CONFIG_MACH_MX27
	202	static struct resource mxc_fec_resources[] = {
	203	{
58152a16 UKK	204	.start = MX27_FEC_BASE_ADDR,
	205	.end = MX27_FEC_BASE_ADDR + SZ_4K - 1,
	206	.flags = IORESOURCE_MEM,
879fea1b	207	}, {
58152a16 UKK	208	.start = MX27_INT_FEC,
	209	.end = MX27_INT_FEC,
	210	.flags = IORESOURCE_IRQ,
879fea1b SH	211	},
	212	};
	213
	214	struct platform_device mxc_fec_device = {
	215	.name = "fec",
	216	.id = 0,
	217	.num_resources = ARRAY_SIZE(mxc_fec_resources),
	218	.resource = mxc_fec_resources,
	219	};
e4813551 HS	220	#endif
e4813551 HS	221
9309b2ba UKK	222	#define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq) \
	223	static struct resource mxc_i2c_resources ## n[] = { \
	224	{ \
	225	.start = baseaddr, \
	226	.end = baseaddr + SZ_4K - 1, \
	227	.flags = IORESOURCE_MEM, \
	228	}, { \
	229	.start = irq, \
	230	.end = irq, \
	231	.flags = IORESOURCE_IRQ, \
	232	} \
	233	}; \
	234	\
	235	struct platform_device mxc_i2c_device ## n = { \
	236	.name = "imx-i2c", \
	237	.id = n, \
	238	.num_resources = ARRAY_SIZE(mxc_i2c_resources ## n), \
	239	.resource = mxc_i2c_resources ## n, \
c5d4dbff	240	}
c5d4dbff	241
9309b2ba	242	DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C);
c5d4dbff SH	243
c5d4dbff SH	244	#ifdef CONFIG_MACH_MX27
9309b2ba	245	DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2);
c5d4dbff SH	246	#endif
c5d4dbff SH	247
824b16e6	248	static struct resource mxc_pwm_resources[] = {
bf50bcc2	249	{
58152a16 UKK	250	.start = MX2x_PWM_BASE_ADDR,
	251	.end = MX2x_PWM_BASE_ADDR + SZ_4K - 1,
	252	.flags = IORESOURCE_MEM,
bf50bcc2	253	}, {
58152a16 UKK	254	.start = MX2x_INT_PWM,
	255	.end = MX2x_INT_PWM,
	256	.flags = IORESOURCE_IRQ,
824b16e6 SH	257	}
	258	};
	259
	260	struct platform_device mxc_pwm_device = {
	261	.name = "mxc_pwm",
	262	.id = 0,
	263	.num_resources = ARRAY_SIZE(mxc_pwm_resources),
bf50bcc2	264	.resource = mxc_pwm_resources,
824b16e6 SH	265	};
824b16e6 SH	266
ccd0e42c UKK	267	#define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \
	268	static struct resource mxc_sdhc_resources ## n[] = { \
	269	{ \
	270	.start = baseaddr, \
	271	.end = baseaddr + SZ_4K - 1, \
	272	.flags = IORESOURCE_MEM, \
	273	}, { \
	274	.start = irq, \
	275	.end = irq, \
	276	.flags = IORESOURCE_IRQ, \
	277	}, { \
	278	.start = dmareq, \
	279	.end = dmareq, \
	280	.flags = IORESOURCE_DMA, \
	281	}, \
	282	}; \
	283	\
988addf8	284	static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32); \
ccd0e42c UKK	285	\
	286	struct platform_device mxc_sdhc_device ## n = { \
	287	.name = "mxc-mmc", \
	288	.id = n, \
	289	.dev = { \
	290	.dma_mask = &mxc_sdhc ## n ## _dmamask, \
988addf8	291	.coherent_dma_mask = DMA_BIT_MASK(32), \
ccd0e42c UKK	292	}, \
	293	.num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \
	294	.resource = mxc_sdhc_resources ## n, \
	295	}
1a02be0e	296
ccd0e42c UKK	297	DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1);
ccd0e42c UKK	298	DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2);
1a02be0e	299
f6d2fa7d	300	#ifdef CONFIG_MACH_MX27
627fb3b9 M	301	static struct resource otg_resources[] = {
627fb3b9 M	302	{
58152a16 UKK	303	.start = MX27_USBOTG_BASE_ADDR,
	304	.end = MX27_USBOTG_BASE_ADDR + 0x1ff,
	305	.flags = IORESOURCE_MEM,
627fb3b9	306	}, {
58152a16 UKK	307	.start = MX27_INT_USB3,
	308	.end = MX27_INT_USB3,
	309	.flags = IORESOURCE_IRQ,
627fb3b9 M	310	},
	311	};
	312
3eb352c7	313	static u64 otg_dmamask = DMA_BIT_MASK(32);
627fb3b9 M	314
	315	/* OTG gadget device */
	316	struct platform_device mxc_otg_udc_device = {
	317	.name = "fsl-usb2-udc",
	318	.id = -1,
	319	.dev = {
	320	.dma_mask = &otg_dmamask,
3eb352c7	321	.coherent_dma_mask = DMA_BIT_MASK(32),
627fb3b9 M	322	},
	323	.resource = otg_resources,
	324	.num_resources = ARRAY_SIZE(otg_resources),
	325	};
	326
	327	/* OTG host */
	328	struct platform_device mxc_otg_host = {
	329	.name = "mxc-ehci",
	330	.id = 0,
	331	.dev = {
3eb352c7	332	.coherent_dma_mask = DMA_BIT_MASK(32),
627fb3b9 M	333	.dma_mask = &otg_dmamask,
	334	},
	335	.resource = otg_resources,
	336	.num_resources = ARRAY_SIZE(otg_resources),
	337	};
	338
	339	/* USB host 1 */
	340
3eb352c7	341	static u64 usbh1_dmamask = DMA_BIT_MASK(32);
627fb3b9 M	342
	343	static struct resource mxc_usbh1_resources[] = {
	344	{
58152a16 UKK	345	.start = MX27_USBOTG_BASE_ADDR + 0x200,
58152a16 UKK	346	.end = MX27_USBOTG_BASE_ADDR + 0x3ff,
627fb3b9 M	347	.flags = IORESOURCE_MEM,
627fb3b9 M	348	}, {
58152a16 UKK	349	.start = MX27_INT_USB1,
58152a16 UKK	350	.end = MX27_INT_USB1,
627fb3b9 M	351	.flags = IORESOURCE_IRQ,
	352	},
	353	};
	354
	355	struct platform_device mxc_usbh1 = {
	356	.name = "mxc-ehci",
	357	.id = 1,
	358	.dev = {
3eb352c7	359	.coherent_dma_mask = DMA_BIT_MASK(32),
627fb3b9 M	360	.dma_mask = &usbh1_dmamask,
	361	},
	362	.resource = mxc_usbh1_resources,
	363	.num_resources = ARRAY_SIZE(mxc_usbh1_resources),
	364	};
	365
	366	/* USB host 2 */
3eb352c7	367	static u64 usbh2_dmamask = DMA_BIT_MASK(32);
627fb3b9 M	368
	369	static struct resource mxc_usbh2_resources[] = {
	370	{
58152a16 UKK	371	.start = MX27_USBOTG_BASE_ADDR + 0x400,
58152a16 UKK	372	.end = MX27_USBOTG_BASE_ADDR + 0x5ff,
627fb3b9 M	373	.flags = IORESOURCE_MEM,
627fb3b9 M	374	}, {
58152a16 UKK	375	.start = MX27_INT_USB2,
58152a16 UKK	376	.end = MX27_INT_USB2,
627fb3b9 M	377	.flags = IORESOURCE_IRQ,
	378	},
	379	};
	380
	381	struct platform_device mxc_usbh2 = {
	382	.name = "mxc-ehci",
	383	.id = 2,
	384	.dev = {
3eb352c7	385	.coherent_dma_mask = DMA_BIT_MASK(32),
627fb3b9 M	386	.dma_mask = &usbh2_dmamask,
	387	},
	388	.resource = mxc_usbh2_resources,
	389	.num_resources = ARRAY_SIZE(mxc_usbh2_resources),
	390	};
f6d2fa7d	391	#endif
627fb3b9	392
69ddb488 UKK	393	#define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \
	394	{ \
	395	.name = _name, \
	396	.start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
	397	.end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
	398	.flags = IORESOURCE_DMA, \
	399	}
23291df4	400
69ddb488 UKK	401	#define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \
	402	static struct resource imx_ssi_resources ## n[] = { \
	403	{ \
	404	.start = MX2x_SSI ## ssin ## _BASE_ADDR, \
	405	.end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \
	406	.flags = IORESOURCE_MEM, \
	407	}, { \
	408	.start = MX2x_INT_SSI1, \
	409	.end = MX2x_INT_SSI1, \
	410	.flags = IORESOURCE_IRQ, \
	411	}, \
	412	DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \
	413	DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \
	414	DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \
	415	DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \
	416	}; \
	417	\
	418	struct platform_device imx_ssi_device ## n = { \
	419	.name = "imx-ssi", \
	420	.id = n, \
	421	.num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \
	422	.resource = imx_ssi_resources ## n, \
	423	}
23291df4	424
69ddb488 UKK	425	DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
69ddb488 UKK	426	DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
23291df4	427
551823e7	428	#define DEFINE_IMX2x_UART_DEVICE(n, baseaddr, irq) \
e9ec2a17 UKK	429	static struct resource imx2x_uart_resources ## n[] = { \
	430	{ \
	431	.start = baseaddr, \
	432	.end = baseaddr + 0xb5, \
	433	.flags = IORESOURCE_MEM, \
	434	}, { \
	435	.start = irq, \
	436	.end = irq, \
	437	.flags = IORESOURCE_IRQ, \
	438	}, \
	439	}; \
	440	\
551823e7	441	struct platform_device imx2x_uart_device ## n = { \
e9ec2a17 UKK	442	.name = "imx-uart", \
	443	.id = n, \
	444	.num_resources = ARRAY_SIZE(imx2x_uart_resources ## n), \
	445	.resource = imx2x_uart_resources ## n, \
	446	}
	447
551823e7 UKK	448	DEFINE_IMX2x_UART_DEVICE(0, MX2x_UART1_BASE_ADDR, MX2x_INT_UART1);
	449	DEFINE_IMX2x_UART_DEVICE(1, MX2x_UART2_BASE_ADDR, MX2x_INT_UART2);
	450	DEFINE_IMX2x_UART_DEVICE(2, MX2x_UART3_BASE_ADDR, MX2x_INT_UART3);
	451	DEFINE_IMX2x_UART_DEVICE(3, MX2x_UART4_BASE_ADDR, MX2x_INT_UART4);
e9ec2a17 UKK	452
e9ec2a17 UKK	453	#ifdef CONFIG_MACH_MX27
551823e7 UKK	454	DEFINE_IMX2x_UART_DEVICE(4, MX27_UART5_BASE_ADDR, MX27_INT_UART5);
551823e7 UKK	455	DEFINE_IMX2x_UART_DEVICE(5, MX27_UART6_BASE_ADDR, MX27_INT_UART6);
e9ec2a17 UKK	456	#endif
e9ec2a17 UKK	457
fc80a5e3	458	/* GPIO port description */
897359d5 UKK	459	#define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
	460	{ \
	461	.chip.label = "gpio-" #n, \
	462	.irq = _irq, \
	463	.base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
	464	n * 0x100), \
	465	.virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
	466	}
	467
	468	#define DEFINE_MXC_GPIO_PORT(SOC, n) \
	469	{ \
	470	.chip.label = "gpio-" #n, \
	471	.base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
	472	n * 0x100), \
	473	.virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
fc80a5e3	474	}
897359d5 UKK	475
	476	#define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \
	477	static struct mxc_gpio_port pfx ## _gpio_ports[] = { \
	478	DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \
	479	DEFINE_MXC_GPIO_PORT(SOC, 1), \
	480	DEFINE_MXC_GPIO_PORT(SOC, 2), \
	481	DEFINE_MXC_GPIO_PORT(SOC, 3), \
	482	DEFINE_MXC_GPIO_PORT(SOC, 4), \
	483	DEFINE_MXC_GPIO_PORT(SOC, 5), \
	484	}
	485
	486	#ifdef CONFIG_MACH_MX21
	487	DEFINE_MXC_GPIO_PORTS(MX21, imx21);
9a763bfb UKK	488
	489	int __init imx21_register_gpios(void)
	490	{
	491	return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
	492	}
897359d5 UKK	493	#endif
	494
	495	#ifdef CONFIG_MACH_MX27
	496	DEFINE_MXC_GPIO_PORTS(MX27, imx27);
fc80a5e3	497
9a763bfb	498	int __init imx27_register_gpios(void)
fc80a5e3	499	{
9a763bfb	500	return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
fc80a5e3	501	}
9a763bfb	502	#endif
4e0fa90d MF	503
	504	#ifdef CONFIG_MACH_MX21
	505	static struct resource mx21_usbhc_resources[] = {
	506	{
e1695307 WS	507	.start = MX21_USBOTG_BASE_ADDR,
e1695307 WS	508	.end = MX21_USBOTG_BASE_ADDR + SZ_8K - 1,
4e0fa90d MF	509	.flags = IORESOURCE_MEM,
	510	},
	511	{
988addf8 RK	512	.start = MX21_INT_USBHOST,
988addf8 RK	513	.end = MX21_INT_USBHOST,
4e0fa90d MF	514	.flags = IORESOURCE_IRQ,
	515	},
	516	};
	517
	518	struct platform_device mx21_usbhc_device = {
	519	.name = "imx21-hcd",
	520	.id = 0,
	521	.dev = {
	522	.dma_mask = &mx21_usbhc_device.dev.coherent_dma_mask,
	523	.coherent_dma_mask = DMA_BIT_MASK(32),
	524	},
	525	.num_resources = ARRAY_SIZE(mx21_usbhc_resources),
	526	.resource = mx21_usbhc_resources,
	527	};
	528	#endif