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cb07625d SH |
1 | /* |
2 | * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> | |
3 | * Copyright (C) 2010 Freescale Semiconductor, Inc. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License as published by the | |
7 | * Free Software Foundation; either version 2 of the License, or (at your | |
8 | * option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
12 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
13 | * for more details. | |
14 | */ | |
15 | ||
16 | #include <linux/platform_device.h> | |
17 | #include <linux/io.h> | |
82906b13 | 18 | #include <linux/platform_data/usb-ehci-mxc.h> |
cb07625d | 19 | |
641dfe8b | 20 | #include "ehci.h" |
50f2de61 SG |
21 | #include "hardware.h" |
22 | ||
cb07625d SH |
23 | #define USBCTRL_OTGBASE_OFFSET 0x600 |
24 | ||
25 | #define MX35_OTG_SIC_SHIFT 29 | |
26 | #define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT) | |
27 | #define MX35_OTG_PM_BIT (1 << 24) | |
5cfe82c6 BT |
28 | #define MX35_OTG_PP_BIT (1 << 11) |
29 | #define MX35_OTG_OCPOL_BIT (1 << 3) | |
cb07625d SH |
30 | |
31 | #define MX35_H1_SIC_SHIFT 21 | |
32 | #define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT) | |
5cfe82c6 | 33 | #define MX35_H1_PP_BIT (1 << 18) |
3d5e2abe | 34 | #define MX35_H1_PM_BIT (1 << 16) |
cb07625d SH |
35 | #define MX35_H1_IPPUE_UP_BIT (1 << 7) |
36 | #define MX35_H1_IPPUE_DOWN_BIT (1 << 6) | |
37 | #define MX35_H1_TLL_BIT (1 << 5) | |
38 | #define MX35_H1_USBTE_BIT (1 << 4) | |
5cfe82c6 | 39 | #define MX35_H1_OCPOL_BIT (1 << 2) |
cb07625d SH |
40 | |
41 | int mx35_initialize_usb_hw(int port, unsigned int flags) | |
42 | { | |
43 | unsigned int v; | |
44 | ||
45 | v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); | |
46 | ||
47 | switch (port) { | |
48 | case 0: /* OTG port */ | |
5cfe82c6 BT |
49 | v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT | |
50 | MX35_OTG_OCPOL_BIT); | |
cb07625d SH |
51 | v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT; |
52 | ||
53 | if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) | |
54 | v |= MX35_OTG_PM_BIT; | |
55 | ||
5cfe82c6 BT |
56 | if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) |
57 | v |= MX35_OTG_PP_BIT; | |
58 | ||
59 | if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) | |
60 | v |= MX35_OTG_OCPOL_BIT; | |
61 | ||
cb07625d SH |
62 | break; |
63 | case 1: /* H1 port */ | |
5cfe82c6 BT |
64 | v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT | |
65 | MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT | MX35_H1_USBTE_BIT | | |
66 | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT); | |
cb07625d SH |
67 | v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT; |
68 | ||
69 | if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) | |
70 | v |= MX35_H1_PM_BIT; | |
71 | ||
5cfe82c6 BT |
72 | if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) |
73 | v |= MX35_H1_PP_BIT; | |
74 | ||
75 | if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) | |
76 | v |= MX35_H1_OCPOL_BIT; | |
77 | ||
cb07625d SH |
78 | if (!(flags & MXC_EHCI_TTL_ENABLED)) |
79 | v |= MX35_H1_TLL_BIT; | |
80 | ||
81 | if (flags & MXC_EHCI_INTERNAL_PHY) | |
82 | v |= MX35_H1_USBTE_BIT; | |
83 | ||
84 | if (flags & MXC_EHCI_IPPUE_DOWN) | |
85 | v |= MX35_H1_IPPUE_DOWN_BIT; | |
86 | ||
87 | if (flags & MXC_EHCI_IPPUE_UP) | |
88 | v |= MX35_H1_IPPUE_UP_BIT; | |
89 | ||
90 | break; | |
91 | default: | |
92 | return -EINVAL; | |
93 | } | |
94 | ||
95 | writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); | |
96 | ||
97 | return 0; | |
98 | } |