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21744f19 EB |
1 | /* |
2 | * Copyright (C) 2010 Eric Benard - eric@eukrea.com | |
3 | * | |
4 | * Based on pcm970-baseboard.c which is : | |
5 | * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version 2 | |
10 | * of the License, or (at your option) any later version. | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
19 | * MA 02110-1301, USA. | |
20 | */ | |
21 | ||
22 | #include <linux/types.h> | |
23 | #include <linux/init.h> | |
24 | ||
25 | #include <linux/gpio.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/leds.h> | |
28 | #include <linux/platform_device.h> | |
21744f19 | 29 | #include <linux/input.h> |
0e189858 | 30 | #include <linux/spi/spi.h> |
21744f19 EB |
31 | #include <video/platform_lcd.h> |
32 | #include <linux/i2c.h> | |
33 | ||
34 | #include <asm/mach-types.h> | |
35 | #include <asm/mach/arch.h> | |
36 | #include <asm/mach/time.h> | |
37 | #include <asm/mach/map.h> | |
38 | ||
21744f19 EB |
39 | #include <mach/hardware.h> |
40 | #include <mach/common.h> | |
21744f19 | 41 | #include <mach/iomux-mx35.h> |
21744f19 | 42 | |
2dcf78c0 | 43 | #include "devices-imx35.h" |
21744f19 EB |
44 | |
45 | static const struct fb_videomode fb_modedb[] = { | |
46 | { | |
c0550c4b | 47 | .name = "CMO-QVGA", |
21744f19 EB |
48 | .refresh = 60, |
49 | .xres = 320, | |
50 | .yres = 240, | |
51 | .pixclock = KHZ2PICOS(6500), | |
52 | .left_margin = 68, | |
53 | .right_margin = 20, | |
54 | .upper_margin = 15, | |
55 | .lower_margin = 4, | |
56 | .hsync_len = 30, | |
57 | .vsync_len = 3, | |
58 | .sync = 0, | |
59 | .vmode = FB_VMODE_NONINTERLACED, | |
60 | .flag = 0, | |
61 | }, | |
c0550c4b EB |
62 | { |
63 | .name = "DVI-VGA", | |
64 | .refresh = 60, | |
65 | .xres = 640, | |
66 | .yres = 480, | |
67 | .pixclock = 32000, | |
68 | .left_margin = 100, | |
69 | .right_margin = 100, | |
70 | .upper_margin = 7, | |
71 | .lower_margin = 100, | |
72 | .hsync_len = 7, | |
73 | .vsync_len = 7, | |
74 | .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT | | |
75 | FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT, | |
76 | .vmode = FB_VMODE_NONINTERLACED, | |
77 | .flag = 0, | |
78 | }, | |
79 | { | |
80 | .name = "DVI-SVGA", | |
81 | .refresh = 60, | |
82 | .xres = 800, | |
83 | .yres = 600, | |
84 | .pixclock = 25000, | |
85 | .left_margin = 75, | |
86 | .right_margin = 75, | |
87 | .upper_margin = 7, | |
88 | .lower_margin = 75, | |
89 | .hsync_len = 7, | |
90 | .vsync_len = 7, | |
91 | .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT | | |
92 | FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT, | |
93 | .vmode = FB_VMODE_NONINTERLACED, | |
94 | .flag = 0, | |
95 | }, | |
21744f19 EB |
96 | }; |
97 | ||
afa77ef3 | 98 | static struct mx3fb_platform_data mx3fb_pdata __initdata = { |
c0550c4b | 99 | .name = "CMO-QVGA", |
21744f19 EB |
100 | .mode = fb_modedb, |
101 | .num_modes = ARRAY_SIZE(fb_modedb), | |
102 | }; | |
103 | ||
8f5260c8 | 104 | static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = { |
21744f19 EB |
105 | /* LCD */ |
106 | MX35_PAD_LD0__IPU_DISPB_DAT_0, | |
107 | MX35_PAD_LD1__IPU_DISPB_DAT_1, | |
108 | MX35_PAD_LD2__IPU_DISPB_DAT_2, | |
109 | MX35_PAD_LD3__IPU_DISPB_DAT_3, | |
110 | MX35_PAD_LD4__IPU_DISPB_DAT_4, | |
111 | MX35_PAD_LD5__IPU_DISPB_DAT_5, | |
112 | MX35_PAD_LD6__IPU_DISPB_DAT_6, | |
113 | MX35_PAD_LD7__IPU_DISPB_DAT_7, | |
114 | MX35_PAD_LD8__IPU_DISPB_DAT_8, | |
115 | MX35_PAD_LD9__IPU_DISPB_DAT_9, | |
116 | MX35_PAD_LD10__IPU_DISPB_DAT_10, | |
117 | MX35_PAD_LD11__IPU_DISPB_DAT_11, | |
118 | MX35_PAD_LD12__IPU_DISPB_DAT_12, | |
119 | MX35_PAD_LD13__IPU_DISPB_DAT_13, | |
120 | MX35_PAD_LD14__IPU_DISPB_DAT_14, | |
121 | MX35_PAD_LD15__IPU_DISPB_DAT_15, | |
122 | MX35_PAD_LD16__IPU_DISPB_DAT_16, | |
123 | MX35_PAD_LD17__IPU_DISPB_DAT_17, | |
124 | MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC, | |
125 | MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK, | |
126 | MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY, | |
127 | MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC, | |
128 | /* Backlight */ | |
129 | MX35_PAD_CONTRAST__IPU_DISPB_CONTR, | |
130 | /* LCD_PWR */ | |
131 | MX35_PAD_D3_CLS__GPIO1_4, | |
132 | /* LED */ | |
133 | MX35_PAD_LD23__GPIO3_29, | |
134 | /* SWITCH */ | |
135 | MX35_PAD_LD19__GPIO3_25, | |
136 | /* UART2 */ | |
137 | MX35_PAD_CTS2__UART2_CTS, | |
138 | MX35_PAD_RTS2__UART2_RTS, | |
139 | MX35_PAD_TXD2__UART2_TXD_MUX, | |
140 | MX35_PAD_RXD2__UART2_RXD_MUX, | |
141 | /* I2S */ | |
142 | MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS, | |
143 | MX35_PAD_STXD4__AUDMUX_AUD4_TXD, | |
144 | MX35_PAD_SRXD4__AUDMUX_AUD4_RXD, | |
145 | MX35_PAD_SCK4__AUDMUX_AUD4_TXC, | |
438a4d66 EB |
146 | /* CAN2 */ |
147 | MX35_PAD_TX5_RX0__CAN2_TXCAN, | |
148 | MX35_PAD_TX4_RX1__CAN2_RXCAN, | |
149 | /* SDCARD */ | |
150 | MX35_PAD_SD1_CMD__ESDHC1_CMD, | |
151 | MX35_PAD_SD1_CLK__ESDHC1_CLK, | |
152 | MX35_PAD_SD1_DATA0__ESDHC1_DAT0, | |
153 | MX35_PAD_SD1_DATA1__ESDHC1_DAT1, | |
154 | MX35_PAD_SD1_DATA2__ESDHC1_DAT2, | |
155 | MX35_PAD_SD1_DATA3__ESDHC1_DAT3, | |
d335cf97 EB |
156 | /* SD1 CD */ |
157 | MX35_PAD_LD18__GPIO3_24, | |
0e189858 EB |
158 | /* SPI */ |
159 | MX35_PAD_CSPI1_MOSI__CSPI1_MOSI, | |
160 | MX35_PAD_CSPI1_MISO__CSPI1_MISO, | |
161 | MX35_PAD_CSPI1_SS0__GPIO1_18, | |
162 | MX35_PAD_CSPI1_SS1__GPIO1_19, | |
163 | MX35_PAD_CSPI1_SCLK__CSPI1_SCLK, | |
164 | MX35_PAD_CSPI1_SPI_RDY__GPIO3_5, | |
21744f19 EB |
165 | }; |
166 | ||
d4abe933 WS |
167 | #define GPIO_LED1 IMX_GPIO_NR(3, 29) |
168 | #define GPIO_SWITCH1 IMX_GPIO_NR(3, 25) | |
da8db3aa | 169 | #define GPIO_LCDPWR IMX_GPIO_NR(1, 4) |
d335cf97 | 170 | #define GPIO_SD1CD IMX_GPIO_NR(3, 24) |
0e189858 EB |
171 | #define GPIO_SPI1_SS0 IMX_GPIO_NR(1, 18) |
172 | #define GPIO_SPI1_SS1 IMX_GPIO_NR(1, 19) | |
173 | #define GPIO_SPI1_IRQ IMX_GPIO_NR(3, 5) | |
21744f19 EB |
174 | |
175 | static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd, | |
176 | unsigned int power) | |
177 | { | |
178 | if (power) | |
179 | gpio_direction_output(GPIO_LCDPWR, 1); | |
180 | else | |
181 | gpio_direction_output(GPIO_LCDPWR, 0); | |
182 | } | |
183 | ||
184 | static struct plat_lcd_data eukrea_mbimxsd_lcd_power_data = { | |
185 | .set_power = eukrea_mbimxsd_lcd_power_set, | |
186 | }; | |
187 | ||
188 | static struct platform_device eukrea_mbimxsd_lcd_powerdev = { | |
189 | .name = "platform-lcd", | |
190 | .dev.platform_data = &eukrea_mbimxsd_lcd_power_data, | |
191 | }; | |
192 | ||
193 | static struct gpio_led eukrea_mbimxsd_leds[] = { | |
194 | { | |
195 | .name = "led1", | |
196 | .default_trigger = "heartbeat", | |
197 | .active_low = 1, | |
198 | .gpio = GPIO_LED1, | |
199 | }, | |
200 | }; | |
201 | ||
47e837b5 UKK |
202 | static const struct gpio_led_platform_data |
203 | eukrea_mbimxsd_led_info __initconst = { | |
21744f19 EB |
204 | .leds = eukrea_mbimxsd_leds, |
205 | .num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds), | |
206 | }; | |
207 | ||
21744f19 EB |
208 | static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = { |
209 | { | |
210 | .gpio = GPIO_SWITCH1, | |
211 | .code = BTN_0, | |
212 | .desc = "BP1", | |
213 | .active_low = 1, | |
214 | .wakeup = 1, | |
215 | }, | |
216 | }; | |
217 | ||
5309498a UKK |
218 | static const struct gpio_keys_platform_data |
219 | eukrea_mbimxsd_button_data __initconst = { | |
21744f19 EB |
220 | .buttons = eukrea_mbimxsd_gpio_buttons, |
221 | .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons), | |
222 | }; | |
223 | ||
21744f19 | 224 | static struct platform_device *platform_devices[] __initdata = { |
21744f19 EB |
225 | &eukrea_mbimxsd_lcd_powerdev, |
226 | }; | |
227 | ||
2dcf78c0 | 228 | static const struct imxuart_platform_data uart_pdata __initconst = { |
21744f19 EB |
229 | .flags = IMXUART_HAVE_RTSCTS, |
230 | }; | |
231 | ||
232 | static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = { | |
233 | { | |
234 | I2C_BOARD_INFO("tlv320aic23", 0x1a), | |
235 | }, | |
236 | }; | |
237 | ||
4697bb92 UKK |
238 | static const |
239 | struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = { | |
21744f19 EB |
240 | .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE, |
241 | }; | |
242 | ||
d335cf97 EB |
243 | static struct esdhc_platform_data sd1_pdata = { |
244 | .cd_gpio = GPIO_SD1CD, | |
913413c3 SG |
245 | .cd_type = ESDHC_CD_GPIO, |
246 | .wp_type = ESDHC_WP_NONE, | |
d335cf97 EB |
247 | }; |
248 | ||
0e189858 EB |
249 | static struct spi_board_info eukrea_mbimxsd35_spi_board_info[] __initdata = { |
250 | { | |
251 | .modalias = "spidev", | |
252 | .max_speed_hz = 20000000, | |
253 | .bus_num = 0, | |
254 | .chip_select = 0, | |
255 | .mode = SPI_MODE_0, | |
256 | }, | |
257 | { | |
258 | .modalias = "spidev", | |
259 | .max_speed_hz = 20000000, | |
260 | .bus_num = 0, | |
261 | .chip_select = 1, | |
262 | .mode = SPI_MODE_0, | |
263 | }, | |
264 | }; | |
265 | ||
266 | static int eukrea_mbimxsd35_spi_cs[] = {GPIO_SPI1_SS0, GPIO_SPI1_SS1}; | |
267 | ||
268 | static const struct spi_imx_master eukrea_mbimxsd35_spi0_data __initconst = { | |
269 | .chipselect = eukrea_mbimxsd35_spi_cs, | |
270 | .num_chipselect = ARRAY_SIZE(eukrea_mbimxsd35_spi_cs), | |
271 | }; | |
272 | ||
21744f19 EB |
273 | /* |
274 | * system init for baseboard usage. Will be called by cpuimx35 init. | |
275 | * | |
276 | * Add platform devices present on this baseboard and init | |
277 | * them from CPU side as far as required to use them later on | |
278 | */ | |
ec53fe3d | 279 | void __init eukrea_mbimxsd35_baseboard_init(void) |
21744f19 EB |
280 | { |
281 | if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads, | |
282 | ARRAY_SIZE(eukrea_mbimxsd_pads))) | |
283 | printk(KERN_ERR "error setting mbimxsd pads !\n"); | |
284 | ||
2dcf78c0 | 285 | imx35_add_imx_uart1(&uart_pdata); |
88289c80 | 286 | imx35_add_ipu_core(); |
afa77ef3 | 287 | imx35_add_mx3_sdc_fb(&mx3fb_pdata); |
21744f19 | 288 | |
4697bb92 | 289 | imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata); |
21744f19 | 290 | |
438a4d66 | 291 | imx35_add_flexcan1(NULL); |
d335cf97 | 292 | imx35_add_sdhci_esdhc_imx(0, &sd1_pdata); |
438a4d66 | 293 | |
21744f19 EB |
294 | gpio_request(GPIO_LED1, "LED1"); |
295 | gpio_direction_output(GPIO_LED1, 1); | |
296 | gpio_free(GPIO_LED1); | |
297 | ||
298 | gpio_request(GPIO_SWITCH1, "SWITCH1"); | |
299 | gpio_direction_input(GPIO_SWITCH1); | |
300 | gpio_free(GPIO_SWITCH1); | |
301 | ||
302 | gpio_request(GPIO_LCDPWR, "LCDPWR"); | |
303 | gpio_direction_output(GPIO_LCDPWR, 1); | |
21744f19 EB |
304 | |
305 | i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices, | |
306 | ARRAY_SIZE(eukrea_mbimxsd_i2c_devices)); | |
307 | ||
0e189858 EB |
308 | gpio_request(GPIO_SPI1_IRQ, "SPI1_IRQ"); |
309 | gpio_direction_input(GPIO_SPI1_IRQ); | |
310 | gpio_free(GPIO_SPI1_IRQ); | |
311 | imx35_add_spi_imx0(&eukrea_mbimxsd35_spi0_data); | |
312 | spi_register_board_info(eukrea_mbimxsd35_spi_board_info, | |
313 | ARRAY_SIZE(eukrea_mbimxsd35_spi_board_info)); | |
314 | ||
21744f19 | 315 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); |
47e837b5 | 316 | gpio_led_register_device(-1, &eukrea_mbimxsd_led_info); |
5309498a | 317 | imx_add_gpio_keys(&eukrea_mbimxsd_button_data); |
21744f19 | 318 | } |