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9fbbe689 | 1 | /* |
263475d4 | 2 | * Copyright 2011-2013 Freescale Semiconductor, Inc. |
9fbbe689 SG |
3 | * Copyright 2011 Linaro Ltd. |
4 | * | |
5 | * The code contained herein is licensed under the GNU General Public | |
6 | * License. You may obtain a copy of the GNU General Public License | |
7 | * Version 2 or later at the following locations: | |
8 | * | |
9 | * http://www.opensource.org/licenses/gpl-license.html | |
10 | * http://www.gnu.org/copyleft/gpl.html | |
11 | */ | |
12 | ||
13 | #include <linux/io.h> | |
14 | #include <linux/irq.h> | |
15 | #include <linux/of.h> | |
16 | #include <linux/of_address.h> | |
17 | #include <linux/of_irq.h> | |
520f7bd7 | 18 | #include <linux/irqchip/arm-gic.h> |
9a67a6fd | 19 | #include "common.h" |
9fbbe689 SG |
20 | |
21 | #define GPC_IMR1 0x008 | |
22 | #define GPC_PGC_CPU_PDN 0x2a0 | |
23 | ||
24 | #define IMR_NUM 4 | |
25 | ||
26 | static void __iomem *gpc_base; | |
27 | static u32 gpc_wake_irqs[IMR_NUM]; | |
28 | static u32 gpc_saved_imrs[IMR_NUM]; | |
29 | ||
30 | void imx_gpc_pre_suspend(void) | |
31 | { | |
32 | void __iomem *reg_imr1 = gpc_base + GPC_IMR1; | |
33 | int i; | |
34 | ||
35 | /* Tell GPC to power off ARM core when suspend */ | |
36 | writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN); | |
37 | ||
38 | for (i = 0; i < IMR_NUM; i++) { | |
39 | gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4); | |
40 | writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4); | |
41 | } | |
42 | } | |
43 | ||
44 | void imx_gpc_post_resume(void) | |
45 | { | |
46 | void __iomem *reg_imr1 = gpc_base + GPC_IMR1; | |
47 | int i; | |
48 | ||
49 | /* Keep ARM core powered on for other low-power modes */ | |
50 | writel_relaxed(0x0, gpc_base + GPC_PGC_CPU_PDN); | |
51 | ||
52 | for (i = 0; i < IMR_NUM; i++) | |
53 | writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); | |
54 | } | |
55 | ||
56 | static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on) | |
57 | { | |
58 | unsigned int idx = d->irq / 32 - 1; | |
59 | u32 mask; | |
60 | ||
61 | /* Sanity check for SPI irq */ | |
62 | if (d->irq < 32) | |
63 | return -EINVAL; | |
64 | ||
65 | mask = 1 << d->irq % 32; | |
66 | gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask : | |
67 | gpc_wake_irqs[idx] & ~mask; | |
68 | ||
69 | return 0; | |
70 | } | |
71 | ||
263475d4 AH |
72 | void imx_gpc_mask_all(void) |
73 | { | |
74 | void __iomem *reg_imr1 = gpc_base + GPC_IMR1; | |
75 | int i; | |
76 | ||
77 | for (i = 0; i < IMR_NUM; i++) { | |
78 | gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4); | |
79 | writel_relaxed(~0, reg_imr1 + i * 4); | |
80 | } | |
81 | ||
82 | } | |
83 | ||
84 | void imx_gpc_restore_all(void) | |
85 | { | |
86 | void __iomem *reg_imr1 = gpc_base + GPC_IMR1; | |
87 | int i; | |
88 | ||
89 | for (i = 0; i < IMR_NUM; i++) | |
90 | writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); | |
91 | } | |
92 | ||
d48866fe | 93 | void imx_gpc_irq_unmask(struct irq_data *d) |
9fbbe689 SG |
94 | { |
95 | void __iomem *reg; | |
96 | u32 val; | |
97 | ||
98 | /* Sanity check for SPI irq */ | |
99 | if (d->irq < 32) | |
100 | return; | |
101 | ||
102 | reg = gpc_base + GPC_IMR1 + (d->irq / 32 - 1) * 4; | |
103 | val = readl_relaxed(reg); | |
104 | val &= ~(1 << d->irq % 32); | |
105 | writel_relaxed(val, reg); | |
106 | } | |
107 | ||
d48866fe | 108 | void imx_gpc_irq_mask(struct irq_data *d) |
9fbbe689 SG |
109 | { |
110 | void __iomem *reg; | |
111 | u32 val; | |
112 | ||
113 | /* Sanity check for SPI irq */ | |
114 | if (d->irq < 32) | |
115 | return; | |
116 | ||
117 | reg = gpc_base + GPC_IMR1 + (d->irq / 32 - 1) * 4; | |
118 | val = readl_relaxed(reg); | |
119 | val |= 1 << (d->irq % 32); | |
120 | writel_relaxed(val, reg); | |
121 | } | |
122 | ||
123 | void __init imx_gpc_init(void) | |
124 | { | |
125 | struct device_node *np; | |
485863b8 | 126 | int i; |
9fbbe689 SG |
127 | |
128 | np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc"); | |
129 | gpc_base = of_iomap(np, 0); | |
130 | WARN_ON(!gpc_base); | |
131 | ||
485863b8 SG |
132 | /* Initially mask all interrupts */ |
133 | for (i = 0; i < IMR_NUM; i++) | |
134 | writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4); | |
135 | ||
9fbbe689 SG |
136 | /* Register GPC as the secondary interrupt controller behind GIC */ |
137 | gic_arch_extn.irq_mask = imx_gpc_irq_mask; | |
138 | gic_arch_extn.irq_unmask = imx_gpc_irq_unmask; | |
139 | gic_arch_extn.irq_set_wake = imx_gpc_irq_set_wake; | |
140 | } |