[deliverable/linux.git] / arch / arm / mach-imx / gpc.c

/*
 * Copyright 2011-2013 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/regulator/consumer.h>
#include <linux/irqchip/arm-gic.h>
#include "common.h"
#include "hardware.h"

#define GPC_CNTR		0x000
#define GPC_IMR1		0x008
#define GPC_PGC_GPU_PDN		0x260
#define GPC_PGC_GPU_PUPSCR	0x264
#define GPC_PGC_GPU_PDNSCR	0x268
#define GPC_PGC_CPU_PDN		0x2a0
#define GPC_PGC_CPU_PUPSCR	0x2a4
#define GPC_PGC_CPU_PDNSCR	0x2a8
#define GPC_PGC_SW2ISO_SHIFT	0x8
#define GPC_PGC_SW_SHIFT	0x0

#define IMR_NUM			4
#define GPC_MAX_IRQS		(IMR_NUM * 32)

#define GPU_VPU_PUP_REQ		BIT(1)
#define GPU_VPU_PDN_REQ		BIT(0)

#define GPC_CLK_MAX		6

struct pu_domain {
	struct generic_pm_domain base;
	struct regulator *reg;
	struct clk *clk[GPC_CLK_MAX];
	int num_clks;
};

static void __iomem *gpc_base;
static u32 gpc_wake_irqs[IMR_NUM];
static u32 gpc_saved_imrs[IMR_NUM];

void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw)
{
	writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) |
		(sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PUPSCR);
}

void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw)
{
	writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) |
		(sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PDNSCR);
}

void imx_gpc_set_arm_power_in_lpm(bool power_off)
{
	writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN);
}

void imx_gpc_pre_suspend(bool arm_power_off)
{
	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	int i;

	/* Tell GPC to power off ARM core when suspend */
	if (arm_power_off)
		imx_gpc_set_arm_power_in_lpm(arm_power_off);

	for (i = 0; i < IMR_NUM; i++) {
		gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
		writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4);
	}
}

void imx_gpc_post_resume(void)
{
	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	int i;

	/* Keep ARM core powered on for other low-power modes */
	imx_gpc_set_arm_power_in_lpm(false);

	for (i = 0; i < IMR_NUM; i++)
		writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
}

static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
{
	unsigned int idx = d->hwirq / 32;
	u32 mask;

	mask = 1 << d->hwirq % 32;
	gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
				  gpc_wake_irqs[idx] & ~mask;

	/*
	 * Do *not* call into the parent, as the GIC doesn't have any
	 * wake-up facility...
	 */
	return 0;
}

void imx_gpc_mask_all(void)
{
	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	int i;

	for (i = 0; i < IMR_NUM; i++) {
		gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
		writel_relaxed(~0, reg_imr1 + i * 4);
	}

}

void imx_gpc_restore_all(void)
{
	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	int i;

	for (i = 0; i < IMR_NUM; i++)
		writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
}

void imx_gpc_hwirq_unmask(unsigned int hwirq)
{
	void __iomem *reg;
	u32 val;

	reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
	val = readl_relaxed(reg);
	val &= ~(1 << hwirq % 32);
	writel_relaxed(val, reg);
}

void imx_gpc_hwirq_mask(unsigned int hwirq)
{
	void __iomem *reg;
	u32 val;

	reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
	val = readl_relaxed(reg);
	val |= 1 << (hwirq % 32);
	writel_relaxed(val, reg);
}

static void imx_gpc_irq_unmask(struct irq_data *d)
{
	imx_gpc_hwirq_unmask(d->hwirq);
	irq_chip_unmask_parent(d);
}

static void imx_gpc_irq_mask(struct irq_data *d)
{
	imx_gpc_hwirq_mask(d->hwirq);
	irq_chip_mask_parent(d);
}

static struct irq_chip imx_gpc_chip = {
	.name			= "GPC",
	.irq_eoi		= irq_chip_eoi_parent,
	.irq_mask		= imx_gpc_irq_mask,
	.irq_unmask		= imx_gpc_irq_unmask,
	.irq_retrigger		= irq_chip_retrigger_hierarchy,
	.irq_set_wake		= imx_gpc_irq_set_wake,
#ifdef CONFIG_SMP
	.irq_set_affinity	= irq_chip_set_affinity_parent,
#endif
};

static int imx_gpc_domain_translate(struct irq_domain *d,
				    struct irq_fwspec *fwspec,
				    unsigned long *hwirq,
				    unsigned int *type)
{
	if (is_of_node(fwspec->fwnode)) {
		if (fwspec->param_count != 3)
			return -EINVAL;

		/* No PPI should point to this domain */
		if (fwspec->param[0] != 0)
			return -EINVAL;

		*hwirq = fwspec->param[1];
		*type = fwspec->param[2];
		return 0;
	}

	return -EINVAL;
}

static int imx_gpc_domain_alloc(struct irq_domain *domain,
				  unsigned int irq,
				  unsigned int nr_irqs, void *data)
{
	struct irq_fwspec *fwspec = data;
	struct irq_fwspec parent_fwspec;
	irq_hw_number_t hwirq;
	int i;

	if (fwspec->param_count != 3)
		return -EINVAL;	/* Not GIC compliant */
	if (fwspec->param[0] != 0)
		return -EINVAL;	/* No PPI should point to this domain */

	hwirq = fwspec->param[1];
	if (hwirq >= GPC_MAX_IRQS)
		return -EINVAL;	/* Can't deal with this */

	for (i = 0; i < nr_irqs; i++)
		irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i,
					      &imx_gpc_chip, NULL);

	parent_fwspec = *fwspec;
	parent_fwspec.fwnode = domain->parent->fwnode;
	return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs,
					    &parent_fwspec);
}

static const struct irq_domain_ops imx_gpc_domain_ops = {
	.translate	= imx_gpc_domain_translate,
	.alloc		= imx_gpc_domain_alloc,
	.free		= irq_domain_free_irqs_common,
};

static int __init imx_gpc_init(struct device_node *node,
			       struct device_node *parent)
{
	struct irq_domain *parent_domain, *domain;
	int i;

	if (!parent) {
		pr_err("%s: no parent, giving up\n", node->full_name);
		return -ENODEV;
	}

	parent_domain = irq_find_host(parent);
	if (!parent_domain) {
		pr_err("%s: unable to obtain parent domain\n", node->full_name);
		return -ENXIO;
	}

	gpc_base = of_iomap(node, 0);
	if (WARN_ON(!gpc_base))
	        return -ENOMEM;

	domain = irq_domain_add_hierarchy(parent_domain, 0, GPC_MAX_IRQS,
					  node, &imx_gpc_domain_ops,
					  NULL);
	if (!domain) {
		iounmap(gpc_base);
		return -ENOMEM;
	}

	/* Initially mask all interrupts */
	for (i = 0; i < IMR_NUM; i++)
		writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);

	return 0;
}
IRQCHIP_DECLARE(imx_gpc, "fsl,imx6q-gpc", imx_gpc_init);

void __init imx_gpc_check_dt(void)
{
	struct device_node *np;

	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
	if (WARN_ON(!np))
		return;

	if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) {
		pr_warn("Outdated DT detected, suspend/resume will NOT work\n");

		/* map GPC, so that at least CPUidle and WARs keep working */
		gpc_base = of_iomap(np, 0);
	}
}

static void _imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
{
	int iso, iso2sw;
	u32 val;

	/* Read ISO and ISO2SW power down delays */
	val = readl_relaxed(gpc_base + GPC_PGC_GPU_PDNSCR);
	iso = val & 0x3f;
	iso2sw = (val >> 8) & 0x3f;

	/* Gate off PU domain when GPU/VPU when powered down */
	writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);

	/* Request GPC to power down GPU/VPU */
	val = readl_relaxed(gpc_base + GPC_CNTR);
	val |= GPU_VPU_PDN_REQ;
	writel_relaxed(val, gpc_base + GPC_CNTR);

	/* Wait ISO + ISO2SW IPG clock cycles */
	ndelay((iso + iso2sw) * 1000 / 66);
}

static int imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
{
	struct pu_domain *pu = container_of(genpd, struct pu_domain, base);

	_imx6q_pm_pu_power_off(genpd);

	if (pu->reg)
		regulator_disable(pu->reg);

	return 0;
}

static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd)
{
	struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
	int i, ret, sw, sw2iso;
	u32 val;

	if (pu->reg)
		ret = regulator_enable(pu->reg);
	if (pu->reg && ret) {
		pr_err("%s: failed to enable regulator: %d\n", __func__, ret);
		return ret;
	}

	/* Enable reset clocks for all devices in the PU domain */
	for (i = 0; i < pu->num_clks; i++)
		clk_prepare_enable(pu->clk[i]);

	/* Gate off PU domain when GPU/VPU when powered down */
	writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);

	/* Read ISO and ISO2SW power down delays */
	val = readl_relaxed(gpc_base + GPC_PGC_GPU_PUPSCR);
	sw = val & 0x3f;
	sw2iso = (val >> 8) & 0x3f;

	/* Request GPC to power up GPU/VPU */
	val = readl_relaxed(gpc_base + GPC_CNTR);
	val |= GPU_VPU_PUP_REQ;
	writel_relaxed(val, gpc_base + GPC_CNTR);

	/* Wait ISO + ISO2SW IPG clock cycles */
	ndelay((sw + sw2iso) * 1000 / 66);

	/* Disable reset clocks for all devices in the PU domain */
	for (i = 0; i < pu->num_clks; i++)
		clk_disable_unprepare(pu->clk[i]);

	return 0;
}

static struct generic_pm_domain imx6q_arm_domain = {
	.name = "ARM",
};

static struct pu_domain imx6q_pu_domain = {
	.base = {
		.name = "PU",
		.power_off = imx6q_pm_pu_power_off,
		.power_on = imx6q_pm_pu_power_on,
		.power_off_latency_ns = 25000,
		.power_on_latency_ns = 2000000,
	},
};

static struct generic_pm_domain imx6sl_display_domain = {
	.name = "DISPLAY",
};

static struct generic_pm_domain *imx_gpc_domains[] = {
	&imx6q_arm_domain,
	&imx6q_pu_domain.base,
	&imx6sl_display_domain,
};

static struct genpd_onecell_data imx_gpc_onecell_data = {
	.domains = imx_gpc_domains,
	.num_domains = ARRAY_SIZE(imx_gpc_domains),
};

static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg)
{
	struct clk *clk;
	int i;

	imx6q_pu_domain.reg = pu_reg;

	for (i = 0; ; i++) {
		clk = of_clk_get(dev->of_node, i);
		if (IS_ERR(clk))
			break;
		if (i >= GPC_CLK_MAX) {
			dev_err(dev, "more than %d clocks\n", GPC_CLK_MAX);
			goto clk_err;
		}
		imx6q_pu_domain.clk[i] = clk;
	}
	imx6q_pu_domain.num_clks = i;

	/* Enable power always in case bootloader disabled it. */
	imx6q_pm_pu_power_on(&imx6q_pu_domain.base);

	if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS))
		return 0;

	pm_genpd_init(&imx6q_pu_domain.base, NULL, false);
	return of_genpd_add_provider_onecell(dev->of_node,
					     &imx_gpc_onecell_data);

clk_err:
	while (i--)
		clk_put(imx6q_pu_domain.clk[i]);
	return -EINVAL;
}

static int imx_gpc_probe(struct platform_device *pdev)
{
	struct regulator *pu_reg;
	int ret;

	/* bail out if DT too old and doesn't provide the necessary info */
	if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells"))
		return 0;

	pu_reg = devm_regulator_get_optional(&pdev->dev, "pu");
	if (PTR_ERR(pu_reg) == -ENODEV)
		pu_reg = NULL;
	if (IS_ERR(pu_reg)) {
		ret = PTR_ERR(pu_reg);
		dev_err(&pdev->dev, "failed to get pu regulator: %d\n", ret);
		return ret;
	}

	return imx_gpc_genpd_init(&pdev->dev, pu_reg);
}

static const struct of_device_id imx_gpc_dt_ids[] = {
	{ .compatible = "fsl,imx6q-gpc" },
	{ .compatible = "fsl,imx6sl-gpc" },
	{ }
};

static struct platform_driver imx_gpc_driver = {
	.driver = {
		.name = "imx-gpc",
		.of_match_table = imx_gpc_dt_ids,
	},
	.probe = imx_gpc_probe,
};

static int __init imx_pgc_init(void)
{
	return platform_driver_register(&imx_gpc_driver);
}
subsys_initcall(imx_pgc_init);
Commit	Line	Data
9fbbe689	1	/*
263475d4	2	* Copyright 2011-2013 Freescale Semiconductor, Inc.
9fbbe689 SG	3	* Copyright 2011 Linaro Ltd.
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
00eb60a8 PZ	13	#include <linux/clk.h>
00eb60a8 PZ	14	#include <linux/delay.h>
9fbbe689 SG	15	#include <linux/io.h>
9fbbe689 SG	16	#include <linux/irq.h>
0cc09e85	17	#include <linux/irqchip.h>
9fbbe689 SG	18	#include <linux/of.h>
	19	#include <linux/of_address.h>
	20	#include <linux/of_irq.h>
00eb60a8 PZ	21	#include <linux/platform_device.h>
	22	#include <linux/pm_domain.h>
	23	#include <linux/regulator/consumer.h>
520f7bd7	24	#include <linux/irqchip/arm-gic.h>
9a67a6fd	25	#include "common.h"
00eb60a8	26	#include "hardware.h"
9fbbe689	27
00eb60a8	28	#define GPC_CNTR 0x000
9fbbe689	29	#define GPC_IMR1 0x008
00eb60a8 PZ	30	#define GPC_PGC_GPU_PDN 0x260
	31	#define GPC_PGC_GPU_PUPSCR 0x264
	32	#define GPC_PGC_GPU_PDNSCR 0x268
9fbbe689	33	#define GPC_PGC_CPU_PDN 0x2a0
05136f08 AH	34	#define GPC_PGC_CPU_PUPSCR 0x2a4
	35	#define GPC_PGC_CPU_PDNSCR 0x2a8
	36	#define GPC_PGC_SW2ISO_SHIFT 0x8
	37	#define GPC_PGC_SW_SHIFT 0x0
9fbbe689 SG	38
9fbbe689 SG	39	#define IMR_NUM 4
b923ff6a	40	#define GPC_MAX_IRQS (IMR_NUM * 32)
9fbbe689	41
00eb60a8 PZ	42	#define GPU_VPU_PUP_REQ BIT(1)
	43	#define GPU_VPU_PDN_REQ BIT(0)
	44
	45	#define GPC_CLK_MAX 6
	46
	47	struct pu_domain {
	48	struct generic_pm_domain base;
	49	struct regulator *reg;
	50	struct clk *clk[GPC_CLK_MAX];
	51	int num_clks;
	52	};
	53
9fbbe689 SG	54	static void __iomem *gpc_base;
	55	static u32 gpc_wake_irqs[IMR_NUM];
	56	static u32 gpc_saved_imrs[IMR_NUM];
	57
05136f08 AH	58	void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw)
	59	{
	60	writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) \|
	61	(sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PUPSCR);
	62	}
	63
	64	void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw)
	65	{
	66	writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) \|
	67	(sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PDNSCR);
	68	}
	69
	70	void imx_gpc_set_arm_power_in_lpm(bool power_off)
	71	{
	72	writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN);
	73	}
	74
80c0ecdc	75	void imx_gpc_pre_suspend(bool arm_power_off)
9fbbe689 SG	76	{
	77	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	78	int i;
	79
	80	/* Tell GPC to power off ARM core when suspend */
80c0ecdc	81	if (arm_power_off)
05136f08	82	imx_gpc_set_arm_power_in_lpm(arm_power_off);
9fbbe689 SG	83
	84	for (i = 0; i < IMR_NUM; i++) {
	85	gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
	86	writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4);
	87	}
	88	}
	89
	90	void imx_gpc_post_resume(void)
	91	{
	92	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	93	int i;
	94
	95	/* Keep ARM core powered on for other low-power modes */
05136f08	96	imx_gpc_set_arm_power_in_lpm(false);
9fbbe689 SG	97
	98	for (i = 0; i < IMR_NUM; i++)
	99	writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
	100	}
	101
	102	static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
	103	{
b923ff6a	104	unsigned int idx = d->hwirq / 32;
9fbbe689 SG	105	u32 mask;
9fbbe689 SG	106
e2fd06f6	107	mask = 1 << d->hwirq % 32;
9fbbe689 SG	108	gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] \| mask :
	109	gpc_wake_irqs[idx] & ~mask;
	110
b923ff6a MZ	111	/*
	112	* Do not call into the parent, as the GIC doesn't have any
	113	* wake-up facility...
	114	*/
9fbbe689 SG	115	return 0;
	116	}
	117
263475d4 AH	118	void imx_gpc_mask_all(void)
	119	{
	120	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	121	int i;
	122
	123	for (i = 0; i < IMR_NUM; i++) {
	124	gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
	125	writel_relaxed(~0, reg_imr1 + i * 4);
	126	}
	127
	128	}
	129
	130	void imx_gpc_restore_all(void)
	131	{
	132	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	133	int i;
	134
	135	for (i = 0; i < IMR_NUM; i++)
	136	writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
	137	}
	138
65bb688a	139	void imx_gpc_hwirq_unmask(unsigned int hwirq)
9fbbe689 SG	140	{
	141	void __iomem *reg;
	142	u32 val;
	143
b923ff6a	144	reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
9fbbe689	145	val = readl_relaxed(reg);
65bb688a	146	val &= ~(1 << hwirq % 32);
9fbbe689 SG	147	writel_relaxed(val, reg);
	148	}
	149
65bb688a	150	void imx_gpc_hwirq_mask(unsigned int hwirq)
9fbbe689 SG	151	{
	152	void __iomem *reg;
	153	u32 val;
	154
b923ff6a	155	reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
65bb688a MZ	156	val = readl_relaxed(reg);
	157	val \|= 1 << (hwirq % 32);
	158	writel_relaxed(val, reg);
	159	}
	160
	161	static void imx_gpc_irq_unmask(struct irq_data *d)
	162	{
65bb688a	163	imx_gpc_hwirq_unmask(d->hwirq);
b923ff6a	164	irq_chip_unmask_parent(d);
65bb688a MZ	165	}
	166
	167	static void imx_gpc_irq_mask(struct irq_data *d)
	168	{
65bb688a	169	imx_gpc_hwirq_mask(d->hwirq);
b923ff6a	170	irq_chip_mask_parent(d);
9fbbe689 SG	171	}
9fbbe689 SG	172
b923ff6a	173	static struct irq_chip imx_gpc_chip = {
e33b6752 MZ	174	.name = "GPC",
	175	.irq_eoi = irq_chip_eoi_parent,
	176	.irq_mask = imx_gpc_irq_mask,
	177	.irq_unmask = imx_gpc_irq_unmask,
	178	.irq_retrigger = irq_chip_retrigger_hierarchy,
	179	.irq_set_wake = imx_gpc_irq_set_wake,
	180	#ifdef CONFIG_SMP
	181	.irq_set_affinity = irq_chip_set_affinity_parent,
	182	#endif
b923ff6a MZ	183	};
b923ff6a MZ	184
f833f57f MZ	185	static int imx_gpc_domain_translate(struct irq_domain *d,
	186	struct irq_fwspec *fwspec,
	187	unsigned long *hwirq,
	188	unsigned int *type)
9fbbe689	189	{
f833f57f MZ	190	if (is_of_node(fwspec->fwnode)) {
	191	if (fwspec->param_count != 3)
	192	return -EINVAL;
b923ff6a	193
f833f57f MZ	194	/* No PPI should point to this domain */
	195	if (fwspec->param[0] != 0)
	196	return -EINVAL;
	197
	198	*hwirq = fwspec->param[1];
	199	*type = fwspec->param[2];
	200	return 0;
	201	}
	202
	203	return -EINVAL;
b923ff6a MZ	204	}
	205
	206	static int imx_gpc_domain_alloc(struct irq_domain *domain,
	207	unsigned int irq,
	208	unsigned int nr_irqs, void *data)
	209	{
f833f57f MZ	210	struct irq_fwspec *fwspec = data;
f833f57f MZ	211	struct irq_fwspec parent_fwspec;
b923ff6a	212	irq_hw_number_t hwirq;
485863b8	213	int i;
9fbbe689	214
f833f57f	215	if (fwspec->param_count != 3)
b923ff6a	216	return -EINVAL; /* Not GIC compliant */
f833f57f	217	if (fwspec->param[0] != 0)
b923ff6a MZ	218	return -EINVAL; /* No PPI should point to this domain */
b923ff6a MZ	219
f833f57f	220	hwirq = fwspec->param[1];
b923ff6a MZ	221	if (hwirq >= GPC_MAX_IRQS)
	222	return -EINVAL; /* Can't deal with this */
	223
	224	for (i = 0; i < nr_irqs; i++)
	225	irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i,
	226	&imx_gpc_chip, NULL);
	227
f833f57f MZ	228	parent_fwspec = *fwspec;
	229	parent_fwspec.fwnode = domain->parent->fwnode;
	230	return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs,
	231	&parent_fwspec);
b923ff6a MZ	232	}
b923ff6a MZ	233
9b589a83	234	static const struct irq_domain_ops imx_gpc_domain_ops = {
f833f57f MZ	235	.translate = imx_gpc_domain_translate,
	236	.alloc = imx_gpc_domain_alloc,
	237	.free = irq_domain_free_irqs_common,
b923ff6a MZ	238	};
	239
	240	static int __init imx_gpc_init(struct device_node *node,
	241	struct device_node *parent)
	242	{
	243	struct irq_domain parent_domain, domain;
	244	int i;
	245
	246	if (!parent) {
	247	pr_err("%s: no parent, giving up\n", node->full_name);
	248	return -ENODEV;
	249	}
	250
	251	parent_domain = irq_find_host(parent);
	252	if (!parent_domain) {
	253	pr_err("%s: unable to obtain parent domain\n", node->full_name);
	254	return -ENXIO;
	255	}
	256
	257	gpc_base = of_iomap(node, 0);
	258	if (WARN_ON(!gpc_base))
	259	return -ENOMEM;
	260
	261	domain = irq_domain_add_hierarchy(parent_domain, 0, GPC_MAX_IRQS,
	262	node, &imx_gpc_domain_ops,
	263	NULL);
	264	if (!domain) {
	265	iounmap(gpc_base);
	266	return -ENOMEM;
	267	}
9fbbe689	268
485863b8 SG	269	/* Initially mask all interrupts */
	270	for (i = 0; i < IMR_NUM; i++)
	271	writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);
	272
b923ff6a	273	return 0;
9fbbe689	274	}
0cc09e85	275	IRQCHIP_DECLARE(imx_gpc, "fsl,imx6q-gpc", imx_gpc_init);
b923ff6a	276
14517564 MZ	277	void __init imx_gpc_check_dt(void)
	278	{
	279	struct device_node *np;
	280
	281	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
634a6037 LS	282	if (WARN_ON(!np))
	283	return;
	284
	285	if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) {
	286	pr_warn("Outdated DT detected, suspend/resume will NOT work\n");
	287
	288	/* map GPC, so that at least CPUidle and WARs keep working */
	289	gpc_base = of_iomap(np, 0);
	290	}
14517564 MZ	291	}
14517564 MZ	292
00eb60a8 PZ	293	static void _imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
	294	{
	295	int iso, iso2sw;
	296	u32 val;
	297
	298	/* Read ISO and ISO2SW power down delays */
	299	val = readl_relaxed(gpc_base + GPC_PGC_GPU_PDNSCR);
	300	iso = val & 0x3f;
	301	iso2sw = (val >> 8) & 0x3f;
	302
	303	/* Gate off PU domain when GPU/VPU when powered down */
	304	writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
	305
	306	/* Request GPC to power down GPU/VPU */
	307	val = readl_relaxed(gpc_base + GPC_CNTR);
	308	val \|= GPU_VPU_PDN_REQ;
	309	writel_relaxed(val, gpc_base + GPC_CNTR);
	310
	311	/* Wait ISO + ISO2SW IPG clock cycles */
	312	ndelay((iso + iso2sw) * 1000 / 66);
	313	}
	314
	315	static int imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
	316	{
	317	struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
	318
	319	_imx6q_pm_pu_power_off(genpd);
	320
	321	if (pu->reg)
	322	regulator_disable(pu->reg);
	323
	324	return 0;
	325	}
	326
	327	static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd)
	328	{
	329	struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
	330	int i, ret, sw, sw2iso;
	331	u32 val;
	332
	333	if (pu->reg)
	334	ret = regulator_enable(pu->reg);
	335	if (pu->reg && ret) {
	336	pr_err("%s: failed to enable regulator: %d\n", __func__, ret);
	337	return ret;
	338	}
	339
	340	/* Enable reset clocks for all devices in the PU domain */
	341	for (i = 0; i < pu->num_clks; i++)
	342	clk_prepare_enable(pu->clk[i]);
	343
	344	/* Gate off PU domain when GPU/VPU when powered down */
	345	writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
	346
	347	/* Read ISO and ISO2SW power down delays */
	348	val = readl_relaxed(gpc_base + GPC_PGC_GPU_PUPSCR);
	349	sw = val & 0x3f;
	350	sw2iso = (val >> 8) & 0x3f;
	351
	352	/* Request GPC to power up GPU/VPU */
	353	val = readl_relaxed(gpc_base + GPC_CNTR);
	354	val \|= GPU_VPU_PUP_REQ;
	355	writel_relaxed(val, gpc_base + GPC_CNTR);
	356
357	/* Wait ISO + ISO2SW IPG clock cycles */
358	ndelay((sw + sw2iso) * 1000 / 66);
359
360	/* Disable reset clocks for all devices in the PU domain */
361	for (i = 0; i < pu->num_clks; i++)
362	clk_disable_unprepare(pu->clk[i]);
363
364	return 0;
365	}
366
367	static struct generic_pm_domain imx6q_arm_domain = {
368	.name = "ARM",
369	};
370
371	static struct pu_domain imx6q_pu_domain = {
372	.base = {
373	.name = "PU",
374	.power_off = imx6q_pm_pu_power_off,
375	.power_on = imx6q_pm_pu_power_on,
376	.power_off_latency_ns = 25000,
377	.power_on_latency_ns = 2000000,
378	},
379	};
380
381	static struct generic_pm_domain imx6sl_display_domain = {
382	.name = "DISPLAY",
383	};
384
385	static struct generic_pm_domain *imx_gpc_domains[] = {
386	&imx6q_arm_domain,
387	&imx6q_pu_domain.base,
388	&imx6sl_display_domain,
389	};
390
391	static struct genpd_onecell_data imx_gpc_onecell_data = {
392	.domains = imx_gpc_domains,
393	.num_domains = ARRAY_SIZE(imx_gpc_domains),
394	};
395
396	static int imx_gpc_genpd_init(struct device dev, struct regulator pu_reg)
397	{
398	struct clk *clk;
00eb60a8 PZ	399	int i;
	400
	401	imx6q_pu_domain.reg = pu_reg;
	402
	403	for (i = 0; ; i++) {
	404	clk = of_clk_get(dev->of_node, i);
	405	if (IS_ERR(clk))
	406	break;
	407	if (i >= GPC_CLK_MAX) {
	408	dev_err(dev, "more than %d clocks\n", GPC_CLK_MAX);
	409	goto clk_err;
	410	}
	411	imx6q_pu_domain.clk[i] = clk;
	412	}
	413	imx6q_pu_domain.num_clks = i;
	414
d438462c LS	415	/* Enable power always in case bootloader disabled it. */
	416	imx6q_pm_pu_power_on(&imx6q_pu_domain.base);
	417
	418	if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS))
	419	return 0;
00eb60a8	420
d438462c	421	pm_genpd_init(&imx6q_pu_domain.base, NULL, false);
00eb60a8 PZ	422	return of_genpd_add_provider_onecell(dev->of_node,
	423	&imx_gpc_onecell_data);
	424
	425	clk_err:
	426	while (i--)
	427	clk_put(imx6q_pu_domain.clk[i]);
	428	return -EINVAL;
	429	}
	430
00eb60a8 PZ	431	static int imx_gpc_probe(struct platform_device *pdev)
	432	{
	433	struct regulator *pu_reg;
	434	int ret;
	435
b17c70cd LS	436	/* bail out if DT too old and doesn't provide the necessary info */
	437	if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells"))
	438	return 0;
	439
00eb60a8 PZ	440	pu_reg = devm_regulator_get_optional(&pdev->dev, "pu");
	441	if (PTR_ERR(pu_reg) == -ENODEV)
	442	pu_reg = NULL;
	443	if (IS_ERR(pu_reg)) {
	444	ret = PTR_ERR(pu_reg);
	445	dev_err(&pdev->dev, "failed to get pu regulator: %d\n", ret);
	446	return ret;
	447	}
	448
	449	return imx_gpc_genpd_init(&pdev->dev, pu_reg);
	450	}
	451
	452	static const struct of_device_id imx_gpc_dt_ids[] = {
	453	{ .compatible = "fsl,imx6q-gpc" },
	454	{ .compatible = "fsl,imx6sl-gpc" },
	455	{ }
	456	};
	457
	458	static struct platform_driver imx_gpc_driver = {
	459	.driver = {
	460	.name = "imx-gpc",
00eb60a8 PZ	461	.of_match_table = imx_gpc_dt_ids,
	462	},
	463	.probe = imx_gpc_probe,
	464	};
	465
	466	static int __init imx_pgc_init(void)
	467	{
	468	return platform_driver_register(&imx_gpc_driver);
	469	}
	470	subsys_initcall(imx_pgc_init);