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9fbbe689 | 1 | /* |
263475d4 | 2 | * Copyright 2011-2013 Freescale Semiconductor, Inc. |
9fbbe689 SG |
3 | * Copyright 2011 Linaro Ltd. |
4 | * | |
5 | * The code contained herein is licensed under the GNU General Public | |
6 | * License. You may obtain a copy of the GNU General Public License | |
7 | * Version 2 or later at the following locations: | |
8 | * | |
9 | * http://www.opensource.org/licenses/gpl-license.html | |
10 | * http://www.gnu.org/copyleft/gpl.html | |
11 | */ | |
12 | ||
00eb60a8 PZ |
13 | #include <linux/clk.h> |
14 | #include <linux/delay.h> | |
9fbbe689 SG |
15 | #include <linux/io.h> |
16 | #include <linux/irq.h> | |
0cc09e85 | 17 | #include <linux/irqchip.h> |
9fbbe689 SG |
18 | #include <linux/of.h> |
19 | #include <linux/of_address.h> | |
20 | #include <linux/of_irq.h> | |
00eb60a8 PZ |
21 | #include <linux/platform_device.h> |
22 | #include <linux/pm_domain.h> | |
23 | #include <linux/regulator/consumer.h> | |
520f7bd7 | 24 | #include <linux/irqchip/arm-gic.h> |
9a67a6fd | 25 | #include "common.h" |
00eb60a8 | 26 | #include "hardware.h" |
9fbbe689 | 27 | |
00eb60a8 | 28 | #define GPC_CNTR 0x000 |
9fbbe689 | 29 | #define GPC_IMR1 0x008 |
00eb60a8 PZ |
30 | #define GPC_PGC_GPU_PDN 0x260 |
31 | #define GPC_PGC_GPU_PUPSCR 0x264 | |
32 | #define GPC_PGC_GPU_PDNSCR 0x268 | |
9fbbe689 | 33 | #define GPC_PGC_CPU_PDN 0x2a0 |
05136f08 AH |
34 | #define GPC_PGC_CPU_PUPSCR 0x2a4 |
35 | #define GPC_PGC_CPU_PDNSCR 0x2a8 | |
36 | #define GPC_PGC_SW2ISO_SHIFT 0x8 | |
37 | #define GPC_PGC_SW_SHIFT 0x0 | |
9fbbe689 SG |
38 | |
39 | #define IMR_NUM 4 | |
b923ff6a | 40 | #define GPC_MAX_IRQS (IMR_NUM * 32) |
9fbbe689 | 41 | |
00eb60a8 PZ |
42 | #define GPU_VPU_PUP_REQ BIT(1) |
43 | #define GPU_VPU_PDN_REQ BIT(0) | |
44 | ||
45 | #define GPC_CLK_MAX 6 | |
46 | ||
47 | struct pu_domain { | |
48 | struct generic_pm_domain base; | |
49 | struct regulator *reg; | |
50 | struct clk *clk[GPC_CLK_MAX]; | |
51 | int num_clks; | |
52 | }; | |
53 | ||
9fbbe689 SG |
54 | static void __iomem *gpc_base; |
55 | static u32 gpc_wake_irqs[IMR_NUM]; | |
56 | static u32 gpc_saved_imrs[IMR_NUM]; | |
57 | ||
05136f08 AH |
58 | void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw) |
59 | { | |
60 | writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) | | |
61 | (sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PUPSCR); | |
62 | } | |
63 | ||
64 | void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw) | |
65 | { | |
66 | writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) | | |
67 | (sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PDNSCR); | |
68 | } | |
69 | ||
70 | void imx_gpc_set_arm_power_in_lpm(bool power_off) | |
71 | { | |
72 | writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN); | |
73 | } | |
74 | ||
80c0ecdc | 75 | void imx_gpc_pre_suspend(bool arm_power_off) |
9fbbe689 SG |
76 | { |
77 | void __iomem *reg_imr1 = gpc_base + GPC_IMR1; | |
78 | int i; | |
79 | ||
80 | /* Tell GPC to power off ARM core when suspend */ | |
80c0ecdc | 81 | if (arm_power_off) |
05136f08 | 82 | imx_gpc_set_arm_power_in_lpm(arm_power_off); |
9fbbe689 SG |
83 | |
84 | for (i = 0; i < IMR_NUM; i++) { | |
85 | gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4); | |
86 | writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4); | |
87 | } | |
88 | } | |
89 | ||
90 | void imx_gpc_post_resume(void) | |
91 | { | |
92 | void __iomem *reg_imr1 = gpc_base + GPC_IMR1; | |
93 | int i; | |
94 | ||
95 | /* Keep ARM core powered on for other low-power modes */ | |
05136f08 | 96 | imx_gpc_set_arm_power_in_lpm(false); |
9fbbe689 SG |
97 | |
98 | for (i = 0; i < IMR_NUM; i++) | |
99 | writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); | |
100 | } | |
101 | ||
102 | static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on) | |
103 | { | |
b923ff6a | 104 | unsigned int idx = d->hwirq / 32; |
9fbbe689 SG |
105 | u32 mask; |
106 | ||
e2fd06f6 | 107 | mask = 1 << d->hwirq % 32; |
9fbbe689 SG |
108 | gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask : |
109 | gpc_wake_irqs[idx] & ~mask; | |
110 | ||
b923ff6a MZ |
111 | /* |
112 | * Do *not* call into the parent, as the GIC doesn't have any | |
113 | * wake-up facility... | |
114 | */ | |
9fbbe689 SG |
115 | return 0; |
116 | } | |
117 | ||
263475d4 AH |
118 | void imx_gpc_mask_all(void) |
119 | { | |
120 | void __iomem *reg_imr1 = gpc_base + GPC_IMR1; | |
121 | int i; | |
122 | ||
123 | for (i = 0; i < IMR_NUM; i++) { | |
124 | gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4); | |
125 | writel_relaxed(~0, reg_imr1 + i * 4); | |
126 | } | |
127 | ||
128 | } | |
129 | ||
130 | void imx_gpc_restore_all(void) | |
131 | { | |
132 | void __iomem *reg_imr1 = gpc_base + GPC_IMR1; | |
133 | int i; | |
134 | ||
135 | for (i = 0; i < IMR_NUM; i++) | |
136 | writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); | |
137 | } | |
138 | ||
65bb688a | 139 | void imx_gpc_hwirq_unmask(unsigned int hwirq) |
9fbbe689 SG |
140 | { |
141 | void __iomem *reg; | |
142 | u32 val; | |
143 | ||
b923ff6a | 144 | reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4; |
9fbbe689 | 145 | val = readl_relaxed(reg); |
65bb688a | 146 | val &= ~(1 << hwirq % 32); |
9fbbe689 SG |
147 | writel_relaxed(val, reg); |
148 | } | |
149 | ||
65bb688a | 150 | void imx_gpc_hwirq_mask(unsigned int hwirq) |
9fbbe689 SG |
151 | { |
152 | void __iomem *reg; | |
153 | u32 val; | |
154 | ||
b923ff6a | 155 | reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4; |
65bb688a MZ |
156 | val = readl_relaxed(reg); |
157 | val |= 1 << (hwirq % 32); | |
158 | writel_relaxed(val, reg); | |
159 | } | |
160 | ||
161 | static void imx_gpc_irq_unmask(struct irq_data *d) | |
162 | { | |
65bb688a | 163 | imx_gpc_hwirq_unmask(d->hwirq); |
b923ff6a | 164 | irq_chip_unmask_parent(d); |
65bb688a MZ |
165 | } |
166 | ||
167 | static void imx_gpc_irq_mask(struct irq_data *d) | |
168 | { | |
65bb688a | 169 | imx_gpc_hwirq_mask(d->hwirq); |
b923ff6a | 170 | irq_chip_mask_parent(d); |
9fbbe689 SG |
171 | } |
172 | ||
b923ff6a | 173 | static struct irq_chip imx_gpc_chip = { |
e33b6752 MZ |
174 | .name = "GPC", |
175 | .irq_eoi = irq_chip_eoi_parent, | |
176 | .irq_mask = imx_gpc_irq_mask, | |
177 | .irq_unmask = imx_gpc_irq_unmask, | |
178 | .irq_retrigger = irq_chip_retrigger_hierarchy, | |
179 | .irq_set_wake = imx_gpc_irq_set_wake, | |
4699ccbf | 180 | .irq_set_type = irq_chip_set_type_parent, |
e33b6752 MZ |
181 | #ifdef CONFIG_SMP |
182 | .irq_set_affinity = irq_chip_set_affinity_parent, | |
183 | #endif | |
b923ff6a MZ |
184 | }; |
185 | ||
f833f57f MZ |
186 | static int imx_gpc_domain_translate(struct irq_domain *d, |
187 | struct irq_fwspec *fwspec, | |
188 | unsigned long *hwirq, | |
189 | unsigned int *type) | |
9fbbe689 | 190 | { |
f833f57f MZ |
191 | if (is_of_node(fwspec->fwnode)) { |
192 | if (fwspec->param_count != 3) | |
193 | return -EINVAL; | |
b923ff6a | 194 | |
f833f57f MZ |
195 | /* No PPI should point to this domain */ |
196 | if (fwspec->param[0] != 0) | |
197 | return -EINVAL; | |
198 | ||
199 | *hwirq = fwspec->param[1]; | |
200 | *type = fwspec->param[2]; | |
201 | return 0; | |
202 | } | |
203 | ||
204 | return -EINVAL; | |
b923ff6a MZ |
205 | } |
206 | ||
207 | static int imx_gpc_domain_alloc(struct irq_domain *domain, | |
208 | unsigned int irq, | |
209 | unsigned int nr_irqs, void *data) | |
210 | { | |
f833f57f MZ |
211 | struct irq_fwspec *fwspec = data; |
212 | struct irq_fwspec parent_fwspec; | |
b923ff6a | 213 | irq_hw_number_t hwirq; |
485863b8 | 214 | int i; |
9fbbe689 | 215 | |
f833f57f | 216 | if (fwspec->param_count != 3) |
b923ff6a | 217 | return -EINVAL; /* Not GIC compliant */ |
f833f57f | 218 | if (fwspec->param[0] != 0) |
b923ff6a MZ |
219 | return -EINVAL; /* No PPI should point to this domain */ |
220 | ||
f833f57f | 221 | hwirq = fwspec->param[1]; |
b923ff6a MZ |
222 | if (hwirq >= GPC_MAX_IRQS) |
223 | return -EINVAL; /* Can't deal with this */ | |
224 | ||
225 | for (i = 0; i < nr_irqs; i++) | |
226 | irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i, | |
227 | &imx_gpc_chip, NULL); | |
228 | ||
f833f57f MZ |
229 | parent_fwspec = *fwspec; |
230 | parent_fwspec.fwnode = domain->parent->fwnode; | |
231 | return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs, | |
232 | &parent_fwspec); | |
b923ff6a MZ |
233 | } |
234 | ||
9b589a83 | 235 | static const struct irq_domain_ops imx_gpc_domain_ops = { |
f833f57f MZ |
236 | .translate = imx_gpc_domain_translate, |
237 | .alloc = imx_gpc_domain_alloc, | |
238 | .free = irq_domain_free_irqs_common, | |
b923ff6a MZ |
239 | }; |
240 | ||
241 | static int __init imx_gpc_init(struct device_node *node, | |
242 | struct device_node *parent) | |
243 | { | |
244 | struct irq_domain *parent_domain, *domain; | |
245 | int i; | |
246 | ||
247 | if (!parent) { | |
248 | pr_err("%s: no parent, giving up\n", node->full_name); | |
249 | return -ENODEV; | |
250 | } | |
251 | ||
252 | parent_domain = irq_find_host(parent); | |
253 | if (!parent_domain) { | |
254 | pr_err("%s: unable to obtain parent domain\n", node->full_name); | |
255 | return -ENXIO; | |
256 | } | |
257 | ||
258 | gpc_base = of_iomap(node, 0); | |
259 | if (WARN_ON(!gpc_base)) | |
260 | return -ENOMEM; | |
261 | ||
262 | domain = irq_domain_add_hierarchy(parent_domain, 0, GPC_MAX_IRQS, | |
263 | node, &imx_gpc_domain_ops, | |
264 | NULL); | |
265 | if (!domain) { | |
266 | iounmap(gpc_base); | |
267 | return -ENOMEM; | |
268 | } | |
9fbbe689 | 269 | |
485863b8 SG |
270 | /* Initially mask all interrupts */ |
271 | for (i = 0; i < IMR_NUM; i++) | |
272 | writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4); | |
273 | ||
b923ff6a | 274 | return 0; |
9fbbe689 | 275 | } |
0cc09e85 | 276 | IRQCHIP_DECLARE(imx_gpc, "fsl,imx6q-gpc", imx_gpc_init); |
b923ff6a | 277 | |
14517564 MZ |
278 | void __init imx_gpc_check_dt(void) |
279 | { | |
280 | struct device_node *np; | |
281 | ||
282 | np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc"); | |
634a6037 LS |
283 | if (WARN_ON(!np)) |
284 | return; | |
285 | ||
286 | if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) { | |
287 | pr_warn("Outdated DT detected, suspend/resume will NOT work\n"); | |
288 | ||
289 | /* map GPC, so that at least CPUidle and WARs keep working */ | |
290 | gpc_base = of_iomap(np, 0); | |
291 | } | |
14517564 MZ |
292 | } |
293 | ||
00eb60a8 PZ |
294 | static void _imx6q_pm_pu_power_off(struct generic_pm_domain *genpd) |
295 | { | |
296 | int iso, iso2sw; | |
297 | u32 val; | |
298 | ||
299 | /* Read ISO and ISO2SW power down delays */ | |
300 | val = readl_relaxed(gpc_base + GPC_PGC_GPU_PDNSCR); | |
301 | iso = val & 0x3f; | |
302 | iso2sw = (val >> 8) & 0x3f; | |
303 | ||
304 | /* Gate off PU domain when GPU/VPU when powered down */ | |
305 | writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN); | |
306 | ||
307 | /* Request GPC to power down GPU/VPU */ | |
308 | val = readl_relaxed(gpc_base + GPC_CNTR); | |
309 | val |= GPU_VPU_PDN_REQ; | |
310 | writel_relaxed(val, gpc_base + GPC_CNTR); | |
311 | ||
312 | /* Wait ISO + ISO2SW IPG clock cycles */ | |
313 | ndelay((iso + iso2sw) * 1000 / 66); | |
314 | } | |
315 | ||
316 | static int imx6q_pm_pu_power_off(struct generic_pm_domain *genpd) | |
317 | { | |
318 | struct pu_domain *pu = container_of(genpd, struct pu_domain, base); | |
319 | ||
320 | _imx6q_pm_pu_power_off(genpd); | |
321 | ||
322 | if (pu->reg) | |
323 | regulator_disable(pu->reg); | |
324 | ||
325 | return 0; | |
326 | } | |
327 | ||
328 | static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd) | |
329 | { | |
330 | struct pu_domain *pu = container_of(genpd, struct pu_domain, base); | |
331 | int i, ret, sw, sw2iso; | |
332 | u32 val; | |
333 | ||
334 | if (pu->reg) | |
335 | ret = regulator_enable(pu->reg); | |
336 | if (pu->reg && ret) { | |
337 | pr_err("%s: failed to enable regulator: %d\n", __func__, ret); | |
338 | return ret; | |
339 | } | |
340 | ||
341 | /* Enable reset clocks for all devices in the PU domain */ | |
342 | for (i = 0; i < pu->num_clks; i++) | |
343 | clk_prepare_enable(pu->clk[i]); | |
344 | ||
345 | /* Gate off PU domain when GPU/VPU when powered down */ | |
346 | writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN); | |
347 | ||
348 | /* Read ISO and ISO2SW power down delays */ | |
349 | val = readl_relaxed(gpc_base + GPC_PGC_GPU_PUPSCR); | |
350 | sw = val & 0x3f; | |
351 | sw2iso = (val >> 8) & 0x3f; | |
352 | ||
353 | /* Request GPC to power up GPU/VPU */ | |
354 | val = readl_relaxed(gpc_base + GPC_CNTR); | |
355 | val |= GPU_VPU_PUP_REQ; | |
356 | writel_relaxed(val, gpc_base + GPC_CNTR); | |
357 | ||
358 | /* Wait ISO + ISO2SW IPG clock cycles */ | |
359 | ndelay((sw + sw2iso) * 1000 / 66); | |
360 | ||
361 | /* Disable reset clocks for all devices in the PU domain */ | |
362 | for (i = 0; i < pu->num_clks; i++) | |
363 | clk_disable_unprepare(pu->clk[i]); | |
364 | ||
365 | return 0; | |
366 | } | |
367 | ||
368 | static struct generic_pm_domain imx6q_arm_domain = { | |
369 | .name = "ARM", | |
370 | }; | |
371 | ||
372 | static struct pu_domain imx6q_pu_domain = { | |
373 | .base = { | |
374 | .name = "PU", | |
375 | .power_off = imx6q_pm_pu_power_off, | |
376 | .power_on = imx6q_pm_pu_power_on, | |
377 | .power_off_latency_ns = 25000, | |
378 | .power_on_latency_ns = 2000000, | |
379 | }, | |
380 | }; | |
381 | ||
382 | static struct generic_pm_domain imx6sl_display_domain = { | |
383 | .name = "DISPLAY", | |
384 | }; | |
385 | ||
386 | static struct generic_pm_domain *imx_gpc_domains[] = { | |
387 | &imx6q_arm_domain, | |
388 | &imx6q_pu_domain.base, | |
389 | &imx6sl_display_domain, | |
390 | }; | |
391 | ||
392 | static struct genpd_onecell_data imx_gpc_onecell_data = { | |
393 | .domains = imx_gpc_domains, | |
394 | .num_domains = ARRAY_SIZE(imx_gpc_domains), | |
395 | }; | |
396 | ||
397 | static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg) | |
398 | { | |
399 | struct clk *clk; | |
00eb60a8 PZ |
400 | int i; |
401 | ||
402 | imx6q_pu_domain.reg = pu_reg; | |
403 | ||
404 | for (i = 0; ; i++) { | |
405 | clk = of_clk_get(dev->of_node, i); | |
406 | if (IS_ERR(clk)) | |
407 | break; | |
408 | if (i >= GPC_CLK_MAX) { | |
409 | dev_err(dev, "more than %d clocks\n", GPC_CLK_MAX); | |
410 | goto clk_err; | |
411 | } | |
412 | imx6q_pu_domain.clk[i] = clk; | |
413 | } | |
414 | imx6q_pu_domain.num_clks = i; | |
415 | ||
d438462c LS |
416 | /* Enable power always in case bootloader disabled it. */ |
417 | imx6q_pm_pu_power_on(&imx6q_pu_domain.base); | |
418 | ||
419 | if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) | |
420 | return 0; | |
00eb60a8 | 421 | |
d438462c | 422 | pm_genpd_init(&imx6q_pu_domain.base, NULL, false); |
00eb60a8 PZ |
423 | return of_genpd_add_provider_onecell(dev->of_node, |
424 | &imx_gpc_onecell_data); | |
425 | ||
426 | clk_err: | |
427 | while (i--) | |
428 | clk_put(imx6q_pu_domain.clk[i]); | |
429 | return -EINVAL; | |
430 | } | |
431 | ||
00eb60a8 PZ |
432 | static int imx_gpc_probe(struct platform_device *pdev) |
433 | { | |
434 | struct regulator *pu_reg; | |
435 | int ret; | |
436 | ||
b17c70cd LS |
437 | /* bail out if DT too old and doesn't provide the necessary info */ |
438 | if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells")) | |
439 | return 0; | |
440 | ||
00eb60a8 PZ |
441 | pu_reg = devm_regulator_get_optional(&pdev->dev, "pu"); |
442 | if (PTR_ERR(pu_reg) == -ENODEV) | |
443 | pu_reg = NULL; | |
444 | if (IS_ERR(pu_reg)) { | |
445 | ret = PTR_ERR(pu_reg); | |
446 | dev_err(&pdev->dev, "failed to get pu regulator: %d\n", ret); | |
447 | return ret; | |
448 | } | |
449 | ||
450 | return imx_gpc_genpd_init(&pdev->dev, pu_reg); | |
451 | } | |
452 | ||
453 | static const struct of_device_id imx_gpc_dt_ids[] = { | |
454 | { .compatible = "fsl,imx6q-gpc" }, | |
455 | { .compatible = "fsl,imx6sl-gpc" }, | |
456 | { } | |
457 | }; | |
458 | ||
459 | static struct platform_driver imx_gpc_driver = { | |
460 | .driver = { | |
461 | .name = "imx-gpc", | |
00eb60a8 PZ |
462 | .of_match_table = imx_gpc_dt_ids, |
463 | }, | |
464 | .probe = imx_gpc_probe, | |
465 | }; | |
466 | ||
467 | static int __init imx_pgc_init(void) | |
468 | { | |
469 | return platform_driver_register(&imx_gpc_driver); | |
470 | } | |
471 | subsys_initcall(imx_pgc_init); |