[deliverable/linux.git] / arch / arm / mach-imx / gpc.c

/*
 * Copyright 2011 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/io.h>
#include <linux/irq.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/irqchip/arm-gic.h>
#include "common.h"

#define GPC_IMR1		0x008
#define GPC_PGC_CPU_PDN		0x2a0

#define IMR_NUM			4

static void __iomem *gpc_base;
static u32 gpc_wake_irqs[IMR_NUM];
static u32 gpc_saved_imrs[IMR_NUM];

void imx_gpc_pre_suspend(void)
{
	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	int i;

	/* Tell GPC to power off ARM core when suspend */
	writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN);

	for (i = 0; i < IMR_NUM; i++) {
		gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
		writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4);
	}
}

void imx_gpc_post_resume(void)
{
	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	int i;

	/* Keep ARM core powered on for other low-power modes */
	writel_relaxed(0x0, gpc_base + GPC_PGC_CPU_PDN);

	for (i = 0; i < IMR_NUM; i++)
		writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
}

static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
{
	unsigned int idx = d->irq / 32 - 1;
	u32 mask;

	/* Sanity check for SPI irq */
	if (d->irq < 32)
		return -EINVAL;

	mask = 1 << d->irq % 32;
	gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
				  gpc_wake_irqs[idx] & ~mask;

	return 0;
}

static void imx_gpc_irq_unmask(struct irq_data *d)
{
	void __iomem *reg;
	u32 val;

	/* Sanity check for SPI irq */
	if (d->irq < 32)
		return;

	reg = gpc_base + GPC_IMR1 + (d->irq / 32 - 1) * 4;
	val = readl_relaxed(reg);
	val &= ~(1 << d->irq % 32);
	writel_relaxed(val, reg);
}

static void imx_gpc_irq_mask(struct irq_data *d)
{
	void __iomem *reg;
	u32 val;

	/* Sanity check for SPI irq */
	if (d->irq < 32)
		return;

	reg = gpc_base + GPC_IMR1 + (d->irq / 32 - 1) * 4;
	val = readl_relaxed(reg);
	val |= 1 << (d->irq % 32);
	writel_relaxed(val, reg);
}

void __init imx_gpc_init(void)
{
	struct device_node *np;
	int i;

	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
	gpc_base = of_iomap(np, 0);
	WARN_ON(!gpc_base);

	/* Initially mask all interrupts */
	for (i = 0; i < IMR_NUM; i++)
		writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);

	/* Register GPC as the secondary interrupt controller behind GIC */
	gic_arch_extn.irq_mask = imx_gpc_irq_mask;
	gic_arch_extn.irq_unmask = imx_gpc_irq_unmask;
	gic_arch_extn.irq_set_wake = imx_gpc_irq_set_wake;
}
Commit	Line	Data
9fbbe689 SG	1	/*
	2	* Copyright 2011 Freescale Semiconductor, Inc.
	3	* Copyright 2011 Linaro Ltd.
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
	13	#include <linux/io.h>
	14	#include <linux/irq.h>
	15	#include <linux/of.h>
	16	#include <linux/of_address.h>
	17	#include <linux/of_irq.h>
520f7bd7	18	#include <linux/irqchip/arm-gic.h>
9a67a6fd	19	#include "common.h"
9fbbe689 SG	20
	21	#define GPC_IMR1 0x008
	22	#define GPC_PGC_CPU_PDN 0x2a0
	23
	24	#define IMR_NUM 4
	25
	26	static void __iomem *gpc_base;
	27	static u32 gpc_wake_irqs[IMR_NUM];
	28	static u32 gpc_saved_imrs[IMR_NUM];
	29
	30	void imx_gpc_pre_suspend(void)
	31	{
	32	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	33	int i;
	34
	35	/* Tell GPC to power off ARM core when suspend */
	36	writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN);
	37
	38	for (i = 0; i < IMR_NUM; i++) {
	39	gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
	40	writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4);
	41	}
	42	}
	43
	44	void imx_gpc_post_resume(void)
	45	{
	46	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
	47	int i;
	48
	49	/* Keep ARM core powered on for other low-power modes */
	50	writel_relaxed(0x0, gpc_base + GPC_PGC_CPU_PDN);
	51
	52	for (i = 0; i < IMR_NUM; i++)
	53	writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
	54	}
	55
	56	static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
	57	{
	58	unsigned int idx = d->irq / 32 - 1;
	59	u32 mask;
	60
	61	/* Sanity check for SPI irq */
	62	if (d->irq < 32)
	63	return -EINVAL;
	64
	65	mask = 1 << d->irq % 32;
	66	gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] \| mask :
	67	gpc_wake_irqs[idx] & ~mask;
	68
	69	return 0;
	70	}
	71
	72	static void imx_gpc_irq_unmask(struct irq_data *d)
	73	{
	74	void __iomem *reg;
	75	u32 val;
	76
	77	/* Sanity check for SPI irq */
	78	if (d->irq < 32)
	79	return;
	80
	81	reg = gpc_base + GPC_IMR1 + (d->irq / 32 - 1) * 4;
	82	val = readl_relaxed(reg);
	83	val &= ~(1 << d->irq % 32);
84	writel_relaxed(val, reg);
85	}
86
87	static void imx_gpc_irq_mask(struct irq_data *d)
88	{
89	void __iomem *reg;
90	u32 val;
91
92	/* Sanity check for SPI irq */
93	if (d->irq < 32)
94	return;
95
96	reg = gpc_base + GPC_IMR1 + (d->irq / 32 - 1) * 4;
97	val = readl_relaxed(reg);
98	val \|= 1 << (d->irq % 32);
99	writel_relaxed(val, reg);
100	}
101
102	void __init imx_gpc_init(void)
103	{
104	struct device_node *np;
485863b8	105	int i;
9fbbe689 SG	106
	107	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
	108	gpc_base = of_iomap(np, 0);
	109	WARN_ON(!gpc_base);
	110
485863b8 SG	111	/* Initially mask all interrupts */
	112	for (i = 0; i < IMR_NUM; i++)
	113	writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);
	114
9fbbe689 SG	115	/* Register GPC as the secondary interrupt controller behind GIC */
	116	gic_arch_extn.irq_mask = imx_gpc_irq_mask;
	117	gic_arch_extn.irq_unmask = imx_gpc_irq_unmask;
	118	gic_arch_extn.irq_set_wake = imx_gpc_irq_set_wake;
	119	}