[deliverable/linux.git] / arch / arm / mach-imx / mach-cpuimx51sd.c

/*
 *
 * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
 *
 * based on board-mx51_babbage.c which is
 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/i2c/tsc2007.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/i2c-gpio.h>
#include <linux/spi/spi.h>
#include <linux/can/platform/mcp251x.h>

#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>

#include "common.h"
#include "devices-imx51.h"
#include "eukrea-baseboards.h"
#include "hardware.h"
#include "iomux-mx51.h"

#define USBH1_RST		IMX_GPIO_NR(2, 28)
#define ETH_RST			IMX_GPIO_NR(2, 31)
#define TSC2007_IRQGPIO_REV2	IMX_GPIO_NR(3, 12)
#define TSC2007_IRQGPIO_REV3	IMX_GPIO_NR(4, 0)
#define CAN_IRQGPIO		IMX_GPIO_NR(1, 1)
#define CAN_RST			IMX_GPIO_NR(4, 15)
#define CAN_NCS			IMX_GPIO_NR(4, 24)
#define CAN_RXOBF_REV2		IMX_GPIO_NR(1, 4)
#define CAN_RXOBF_REV3		IMX_GPIO_NR(3, 12)
#define CAN_RX1BF		IMX_GPIO_NR(1, 6)
#define CAN_TXORTS		IMX_GPIO_NR(1, 7)
#define CAN_TX1RTS		IMX_GPIO_NR(1, 8)
#define CAN_TX2RTS		IMX_GPIO_NR(1, 9)
#define I2C_SCL			IMX_GPIO_NR(4, 16)
#define I2C_SDA			IMX_GPIO_NR(4, 17)

/* USB_CTRL_1 */
#define MX51_USB_CTRL_1_OFFSET		0x10
#define MX51_USB_CTRL_UH1_EXT_CLK_EN	(1 << 25)

#define	MX51_USB_PLLDIV_12_MHZ		0x00
#define	MX51_USB_PLL_DIV_19_2_MHZ	0x01
#define	MX51_USB_PLL_DIV_24_MHZ		0x02

static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
	/* UART1 */
	MX51_PAD_UART1_RXD__UART1_RXD,
	MX51_PAD_UART1_TXD__UART1_TXD,
	MX51_PAD_UART1_RTS__UART1_RTS,
	MX51_PAD_UART1_CTS__UART1_CTS,

	/* USB HOST1 */
	MX51_PAD_USBH1_CLK__USBH1_CLK,
	MX51_PAD_USBH1_DIR__USBH1_DIR,
	MX51_PAD_USBH1_NXT__USBH1_NXT,
	MX51_PAD_USBH1_DATA0__USBH1_DATA0,
	MX51_PAD_USBH1_DATA1__USBH1_DATA1,
	MX51_PAD_USBH1_DATA2__USBH1_DATA2,
	MX51_PAD_USBH1_DATA3__USBH1_DATA3,
	MX51_PAD_USBH1_DATA4__USBH1_DATA4,
	MX51_PAD_USBH1_DATA5__USBH1_DATA5,
	MX51_PAD_USBH1_DATA6__USBH1_DATA6,
	MX51_PAD_USBH1_DATA7__USBH1_DATA7,
	MX51_PAD_USBH1_STP__USBH1_STP,
	MX51_PAD_EIM_CS3__GPIO2_28,		/* PHY nRESET */

	/* FEC */
	MX51_PAD_EIM_DTACK__GPIO2_31,		/* PHY nRESET */

	/* HSI2C */
	MX51_PAD_I2C1_CLK__GPIO4_16,
	MX51_PAD_I2C1_DAT__GPIO4_17,

	/* I2C1 */
	MX51_PAD_SD2_CMD__I2C1_SCL,
	MX51_PAD_SD2_CLK__I2C1_SDA,

	/* CAN */
	MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
	MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
	MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
	MX51_PAD_CSPI1_SS0__GPIO4_24,		/* nCS */
	MX51_PAD_CSI2_PIXCLK__GPIO4_15,		/* nReset */
	MX51_PAD_GPIO1_1__GPIO1_1,		/* IRQ */
	MX51_PAD_GPIO1_4__GPIO1_4,		/* Control signals */
	MX51_PAD_GPIO1_6__GPIO1_6,
	MX51_PAD_GPIO1_7__GPIO1_7,
	MX51_PAD_GPIO1_8__GPIO1_8,
	MX51_PAD_GPIO1_9__GPIO1_9,

	/* Touchscreen */
	/* IRQ */
	NEW_PAD_CTRL(MX51_PAD_GPIO_NAND__GPIO_NAND, PAD_CTL_PUS_22K_UP |
			PAD_CTL_PKE | PAD_CTL_SRE_FAST |
			PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
	NEW_PAD_CTRL(MX51_PAD_NANDF_D8__GPIO4_0, PAD_CTL_PUS_22K_UP |
			PAD_CTL_PKE | PAD_CTL_SRE_FAST |
			PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
};

static const struct imxuart_platform_data uart_pdata __initconst = {
	.flags = IMXUART_HAVE_RTSCTS,
};

static int tsc2007_get_pendown_state(struct device *dev)
{
	if (mx51_revision() < IMX_CHIP_REVISION_3_0)
		return !gpio_get_value(TSC2007_IRQGPIO_REV2);
	else
		return !gpio_get_value(TSC2007_IRQGPIO_REV3);
}

static struct tsc2007_platform_data tsc2007_info = {
	.model			= 2007,
	.x_plate_ohms		= 180,
	.get_pendown_state	= tsc2007_get_pendown_state,
};

static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
	{
		I2C_BOARD_INFO("pcf8563", 0x51),
	}, {
		I2C_BOARD_INFO("tsc2007", 0x49),
		.platform_data	= &tsc2007_info,
	},
};

static const struct mxc_nand_platform_data
		eukrea_cpuimx51sd_nand_board_info __initconst = {
	.width		= 1,
	.hw_ecc		= 1,
	.flash_bbt	= 1,
};

/* This function is board specific as the bit mask for the plldiv will also
be different for other Freescale SoCs, thus a common bitmask is not
possible and cannot get place in /plat-mxc/ehci.c.*/
static int initialize_otg_port(struct platform_device *pdev)
{
	u32 v;
	void __iomem *usb_base;
	void __iomem *usbother_base;

	usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
	if (!usb_base)
		return -ENOMEM;
	usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;

	/* Set the PHY clock to 19.2MHz */
	v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
	v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
	v |= MX51_USB_PLL_DIV_19_2_MHZ;
	__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
	iounmap(usb_base);

	mdelay(10);

	return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
}

static int initialize_usbh1_port(struct platform_device *pdev)
{
	u32 v;
	void __iomem *usb_base;
	void __iomem *usbother_base;

	usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
	if (!usb_base)
		return -ENOMEM;
	usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;

	/* The clock for the USBH1 ULPI port will come from the PHY. */
	v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
	__raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
			usbother_base + MX51_USB_CTRL_1_OFFSET);
	iounmap(usb_base);

	mdelay(10);

	return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
			MXC_EHCI_ITC_NO_THRESHOLD);
}

static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
	.init		= initialize_otg_port,
	.portsc	= MXC_EHCI_UTMI_16BIT,
};

static const struct fsl_usb2_platform_data usb_pdata __initconst = {
	.operating_mode	= FSL_USB2_DR_DEVICE,
	.phy_mode	= FSL_USB2_PHY_UTMI_WIDE,
};

static const struct mxc_usbh_platform_data usbh1_config __initconst = {
	.init		= initialize_usbh1_port,
	.portsc	= MXC_EHCI_MODE_ULPI,
};

static bool otg_mode_host __initdata;

static int __init eukrea_cpuimx51sd_otg_mode(char *options)
{
	if (!strcmp(options, "host"))
		otg_mode_host = true;
	else if (!strcmp(options, "device"))
		otg_mode_host = false;
	else
		pr_info("otg_mode neither \"host\" nor \"device\". "
			"Defaulting to device\n");
	return 1;
}
__setup("otg_mode=", eukrea_cpuimx51sd_otg_mode);

static struct i2c_gpio_platform_data pdata = {
	.sda_pin		= I2C_SDA,
	.sda_is_open_drain	= 0,
	.scl_pin		= I2C_SCL,
	.scl_is_open_drain	= 0,
	.udelay			= 2,
};

static struct platform_device hsi2c_gpio_device = {
	.name			= "i2c-gpio",
	.id			= 0,
	.dev.platform_data	= &pdata,
};

static struct mcp251x_platform_data mcp251x_info = {
	.oscillator_frequency = 24E6,
};

static struct spi_board_info cpuimx51sd_spi_device[] = {
	{
		.modalias        = "mcp2515",
		.max_speed_hz    = 10000000,
		.bus_num         = 0,
		.mode		= SPI_MODE_0,
		.chip_select     = 0,
		.platform_data   = &mcp251x_info,
		/* irq number is run-time assigned */
	},
};

static int cpuimx51sd_spi1_cs[] = {
	CAN_NCS,
};

static const struct spi_imx_master cpuimx51sd_ecspi1_pdata __initconst = {
	.chipselect	= cpuimx51sd_spi1_cs,
	.num_chipselect	= ARRAY_SIZE(cpuimx51sd_spi1_cs),
};

static struct platform_device *rev2_platform_devices[] __initdata = {
	&hsi2c_gpio_device,
};

static const struct imxi2c_platform_data cpuimx51sd_i2c_data __initconst = {
	.bitrate = 100000,
};

static void __init eukrea_cpuimx51sd_init(void)
{
	imx51_soc_init();

	mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
					ARRAY_SIZE(eukrea_cpuimx51sd_pads));

	imx51_add_imx_uart(0, &uart_pdata);
	imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
	imx51_add_imx2_wdt(0);

	gpio_request(ETH_RST, "eth_rst");
	gpio_set_value(ETH_RST, 1);
	imx51_add_fec(NULL);

	gpio_request(CAN_IRQGPIO, "can_irq");
	gpio_direction_input(CAN_IRQGPIO);
	gpio_free(CAN_IRQGPIO);
	gpio_request(CAN_NCS, "can_ncs");
	gpio_direction_output(CAN_NCS, 1);
	gpio_free(CAN_NCS);
	gpio_request(CAN_RST, "can_rst");
	gpio_direction_output(CAN_RST, 0);
	msleep(20);
	gpio_set_value(CAN_RST, 1);
	imx51_add_ecspi(0, &cpuimx51sd_ecspi1_pdata);
	cpuimx51sd_spi_device[0].irq = gpio_to_irq(CAN_IRQGPIO);
	spi_register_board_info(cpuimx51sd_spi_device,
				ARRAY_SIZE(cpuimx51sd_spi_device));

	if (mx51_revision() < IMX_CHIP_REVISION_3_0) {
		eukrea_cpuimx51sd_i2c_devices[1].irq =
			gpio_to_irq(TSC2007_IRQGPIO_REV2),
		platform_add_devices(rev2_platform_devices,
			ARRAY_SIZE(rev2_platform_devices));
		gpio_request(TSC2007_IRQGPIO_REV2, "tsc2007_irq");
		gpio_direction_input(TSC2007_IRQGPIO_REV2);
		gpio_free(TSC2007_IRQGPIO_REV2);
	} else {
		eukrea_cpuimx51sd_i2c_devices[1].irq =
			gpio_to_irq(TSC2007_IRQGPIO_REV3),
		imx51_add_imx_i2c(0, &cpuimx51sd_i2c_data);
		gpio_request(TSC2007_IRQGPIO_REV3, "tsc2007_irq");
		gpio_direction_input(TSC2007_IRQGPIO_REV3);
		gpio_free(TSC2007_IRQGPIO_REV3);
	}

	i2c_register_board_info(0, eukrea_cpuimx51sd_i2c_devices,
			ARRAY_SIZE(eukrea_cpuimx51sd_i2c_devices));

	if (otg_mode_host)
		imx51_add_mxc_ehci_otg(&dr_utmi_config);
	else {
		initialize_otg_port(NULL);
		imx51_add_fsl_usb2_udc(&usb_pdata);
	}

	gpio_request(USBH1_RST, "usb_rst");
	gpio_direction_output(USBH1_RST, 0);
	msleep(20);
	gpio_set_value(USBH1_RST, 1);
	imx51_add_mxc_ehci_hs(1, &usbh1_config);

#ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD
	eukrea_mbimxsd51_baseboard_init();
#endif
}

static void __init eukrea_cpuimx51sd_timer_init(void)
{
	mx51_clocks_init(32768, 24000000, 22579200, 0);
}

MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
	/* Maintainer: Eric Bénard <eric@eukrea.com> */
	.atag_offset = 0x100,
	.map_io = mx51_map_io,
	.init_early = imx51_init_early,
	.init_irq = mx51_init_irq,
	.handle_irq = imx51_handle_irq,
	.init_time	= eukrea_cpuimx51sd_timer_init,
	.init_machine = eukrea_cpuimx51sd_init,
	.init_late	= imx51_init_late,
	.restart	= mxc_restart,
MACHINE_END
Commit	Line	Data
70b17268 EB	1	/*
	2	*
	3	* Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
	4	*
	5	* based on board-mx51_babbage.c which is
	6	* Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
	7	* Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
	8	*
	9	* The code contained herein is licensed under the GNU General Public
	10	* License. You may obtain a copy of the GNU General Public License
	11	* Version 2 or later at the following locations:
	12	*
	13	* http://www.opensource.org/licenses/gpl-license.html
	14	* http://www.gnu.org/copyleft/gpl.html
	15	*/
	16
	17	#include <linux/init.h>
	18	#include <linux/platform_device.h>
	19	#include <linux/i2c.h>
	20	#include <linux/i2c/tsc2007.h>
	21	#include <linux/gpio.h>
	22	#include <linux/delay.h>
	23	#include <linux/io.h>
	24	#include <linux/interrupt.h>
70b17268 EB	25	#include <linux/i2c-gpio.h>
	26	#include <linux/spi/spi.h>
	27	#include <linux/can/platform/mcp251x.h>
	28
70b17268 EB	29	#include <asm/setup.h>
	30	#include <asm/mach-types.h>
	31	#include <asm/mach/arch.h>
	32	#include <asm/mach/time.h>
	33
e3372474	34	#include "common.h"
70b17268	35	#include "devices-imx51.h"
3ed0bcb4	36	#include "eukrea-baseboards.h"
50f2de61	37	#include "hardware.h"
267dd34c	38	#include "iomux-mx51.h"
70b17268	39
96886c43 APR	40	#define USBH1_RST IMX_GPIO_NR(2, 28)
96886c43 APR	41	#define ETH_RST IMX_GPIO_NR(2, 31)
7138a7f9 EB	42	#define TSC2007_IRQGPIO_REV2 IMX_GPIO_NR(3, 12)
7138a7f9 EB	43	#define TSC2007_IRQGPIO_REV3 IMX_GPIO_NR(4, 0)
96886c43 APR	44	#define CAN_IRQGPIO IMX_GPIO_NR(1, 1)
	45	#define CAN_RST IMX_GPIO_NR(4, 15)
	46	#define CAN_NCS IMX_GPIO_NR(4, 24)
7138a7f9 EB	47	#define CAN_RXOBF_REV2 IMX_GPIO_NR(1, 4)
7138a7f9 EB	48	#define CAN_RXOBF_REV3 IMX_GPIO_NR(3, 12)
96886c43 APR	49	#define CAN_RX1BF IMX_GPIO_NR(1, 6)
	50	#define CAN_TXORTS IMX_GPIO_NR(1, 7)
	51	#define CAN_TX1RTS IMX_GPIO_NR(1, 8)
	52	#define CAN_TX2RTS IMX_GPIO_NR(1, 9)
	53	#define I2C_SCL IMX_GPIO_NR(4, 16)
	54	#define I2C_SDA IMX_GPIO_NR(4, 17)
70b17268 EB	55
	56	/* USB_CTRL_1 */
	57	#define MX51_USB_CTRL_1_OFFSET 0x10
	58	#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
	59
	60	#define MX51_USB_PLLDIV_12_MHZ 0x00
	61	#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
	62	#define MX51_USB_PLL_DIV_24_MHZ 0x02
	63
8f5260c8	64	static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
70b17268 EB	65	/* UART1 */
	66	MX51_PAD_UART1_RXD__UART1_RXD,
	67	MX51_PAD_UART1_TXD__UART1_TXD,
	68	MX51_PAD_UART1_RTS__UART1_RTS,
	69	MX51_PAD_UART1_CTS__UART1_CTS,
	70
	71	/* USB HOST1 */
	72	MX51_PAD_USBH1_CLK__USBH1_CLK,
	73	MX51_PAD_USBH1_DIR__USBH1_DIR,
	74	MX51_PAD_USBH1_NXT__USBH1_NXT,
	75	MX51_PAD_USBH1_DATA0__USBH1_DATA0,
	76	MX51_PAD_USBH1_DATA1__USBH1_DATA1,
	77	MX51_PAD_USBH1_DATA2__USBH1_DATA2,
	78	MX51_PAD_USBH1_DATA3__USBH1_DATA3,
	79	MX51_PAD_USBH1_DATA4__USBH1_DATA4,
	80	MX51_PAD_USBH1_DATA5__USBH1_DATA5,
	81	MX51_PAD_USBH1_DATA6__USBH1_DATA6,
	82	MX51_PAD_USBH1_DATA7__USBH1_DATA7,
	83	MX51_PAD_USBH1_STP__USBH1_STP,
ee1ae4d7	84	MX51_PAD_EIM_CS3__GPIO2_28, /* PHY nRESET */
70b17268 EB	85
70b17268 EB	86	/* FEC */
ee1ae4d7	87	MX51_PAD_EIM_DTACK__GPIO2_31, /* PHY nRESET */
70b17268 EB	88
70b17268 EB	89	/* HSI2C */
ee1ae4d7 SH	90	MX51_PAD_I2C1_CLK__GPIO4_16,
ee1ae4d7 SH	91	MX51_PAD_I2C1_DAT__GPIO4_17,
70b17268	92
7138a7f9 EB	93	/* I2C1 */
	94	MX51_PAD_SD2_CMD__I2C1_SCL,
	95	MX51_PAD_SD2_CLK__I2C1_SDA,
	96
70b17268 EB	97	/* CAN */
	98	MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
	99	MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
	100	MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
ee1ae4d7 SH	101	MX51_PAD_CSPI1_SS0__GPIO4_24, /* nCS */
	102	MX51_PAD_CSI2_PIXCLK__GPIO4_15, /* nReset */
	103	MX51_PAD_GPIO1_1__GPIO1_1, /* IRQ */
	104	MX51_PAD_GPIO1_4__GPIO1_4, /* Control signals */
	105	MX51_PAD_GPIO1_6__GPIO1_6,
	106	MX51_PAD_GPIO1_7__GPIO1_7,
	107	MX51_PAD_GPIO1_8__GPIO1_8,
	108	MX51_PAD_GPIO1_9__GPIO1_9,
70b17268 EB	109
70b17268 EB	110	/* Touchscreen */
ee1ae4d7	111	/* IRQ */
7242e24a	112	NEW_PAD_CTRL(MX51_PAD_GPIO_NAND__GPIO_NAND, PAD_CTL_PUS_22K_UP \|
ee1ae4d7 SH	113	PAD_CTL_PKE \| PAD_CTL_SRE_FAST \|
ee1ae4d7 SH	114	PAD_CTL_DSE_HIGH \| PAD_CTL_PUE \| PAD_CTL_HYS),
7138a7f9 EB	115	NEW_PAD_CTRL(MX51_PAD_NANDF_D8__GPIO4_0, PAD_CTL_PUS_22K_UP \|
	116	PAD_CTL_PKE \| PAD_CTL_SRE_FAST \|
	117	PAD_CTL_DSE_HIGH \| PAD_CTL_PUE \| PAD_CTL_HYS),
70b17268 EB	118	};
	119
	120	static const struct imxuart_platform_data uart_pdata __initconst = {
	121	.flags = IMXUART_HAVE_RTSCTS,
	122	};
	123
07f9e5cf	124	static int tsc2007_get_pendown_state(struct device *dev)
7138a7f9 EB	125	{
	126	if (mx51_revision() < IMX_CHIP_REVISION_3_0)
	127	return !gpio_get_value(TSC2007_IRQGPIO_REV2);
	128	else
	129	return !gpio_get_value(TSC2007_IRQGPIO_REV3);
	130	}
	131
70b17268 EB	132	static struct tsc2007_platform_data tsc2007_info = {
	133	.model = 2007,
	134	.x_plate_ohms = 180,
7138a7f9	135	.get_pendown_state = tsc2007_get_pendown_state,
70b17268 EB	136	};
	137
	138	static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
	139	{
	140	I2C_BOARD_INFO("pcf8563", 0x51),
	141	}, {
	142	I2C_BOARD_INFO("tsc2007", 0x49),
70b17268	143	.platform_data = &tsc2007_info,
70b17268 EB	144	},
	145	};
	146
	147	static const struct mxc_nand_platform_data
	148	eukrea_cpuimx51sd_nand_board_info __initconst = {
	149	.width = 1,
	150	.hw_ecc = 1,
	151	.flash_bbt = 1,
	152	};
	153
	154	/* This function is board specific as the bit mask for the plldiv will also
	155	be different for other Freescale SoCs, thus a common bitmask is not
	156	possible and cannot get place in /plat-mxc/ehci.c.*/
	157	static int initialize_otg_port(struct platform_device *pdev)
	158	{
	159	u32 v;
	160	void __iomem *usb_base;
	161	void __iomem *usbother_base;
	162
7d92e8e6	163	usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
28a4f908 FE	164	if (!usb_base)
28a4f908 FE	165	return -ENOMEM;
70b17268 EB	166	usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
	167
	168	/* Set the PHY clock to 19.2MHz */
	169	v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
	170	v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
	171	v \|= MX51_USB_PLL_DIV_19_2_MHZ;
	172	__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
	173	iounmap(usb_base);
4bd597b6 SH	174
	175	mdelay(10);
	176
	177	return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
70b17268 EB	178	}
	179
	180	static int initialize_usbh1_port(struct platform_device *pdev)
	181	{
	182	u32 v;
	183	void __iomem *usb_base;
	184	void __iomem *usbother_base;
	185
7d92e8e6	186	usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
28a4f908 FE	187	if (!usb_base)
28a4f908 FE	188	return -ENOMEM;
70b17268 EB	189	usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
	190
	191	/* The clock for the USBH1 ULPI port will come from the PHY. */
	192	v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
	193	__raw_writel(v \| MX51_USB_CTRL_UH1_EXT_CLK_EN,
	194	usbother_base + MX51_USB_CTRL_1_OFFSET);
	195	iounmap(usb_base);
4bd597b6 SH	196
	197	mdelay(10);
	198
	199	return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED \|
	200	MXC_EHCI_ITC_NO_THRESHOLD);
70b17268 EB	201	}
70b17268 EB	202
7d92e8e6	203	static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
70b17268 EB	204	.init = initialize_otg_port,
70b17268 EB	205	.portsc = MXC_EHCI_UTMI_16BIT,
70b17268 EB	206	};
70b17268 EB	207
6cafe48a	208	static const struct fsl_usb2_platform_data usb_pdata __initconst = {
70b17268 EB	209	.operating_mode = FSL_USB2_DR_DEVICE,
	210	.phy_mode = FSL_USB2_PHY_UTMI_WIDE,
	211	};
	212
7d92e8e6	213	static const struct mxc_usbh_platform_data usbh1_config __initconst = {
70b17268 EB	214	.init = initialize_usbh1_port,
70b17268 EB	215	.portsc = MXC_EHCI_MODE_ULPI,
70b17268 EB	216	};
70b17268 EB	217
33a264dd	218	static bool otg_mode_host __initdata;
70b17268 EB	219
	220	static int __init eukrea_cpuimx51sd_otg_mode(char *options)
	221	{
	222	if (!strcmp(options, "host"))
33a264dd	223	otg_mode_host = true;
70b17268	224	else if (!strcmp(options, "device"))
33a264dd	225	otg_mode_host = false;
70b17268 EB	226	else
	227	pr_info("otg_mode neither \"host\" nor \"device\". "
	228	"Defaulting to device\n");
33a264dd	229	return 1;
70b17268 EB	230	}
	231	__setup("otg_mode=", eukrea_cpuimx51sd_otg_mode);
	232
	233	static struct i2c_gpio_platform_data pdata = {
	234	.sda_pin = I2C_SDA,
	235	.sda_is_open_drain = 0,
	236	.scl_pin = I2C_SCL,
	237	.scl_is_open_drain = 0,
	238	.udelay = 2,
	239	};
	240
	241	static struct platform_device hsi2c_gpio_device = {
	242	.name = "i2c-gpio",
	243	.id = 0,
	244	.dev.platform_data = &pdata,
	245	};
	246
	247	static struct mcp251x_platform_data mcp251x_info = {
	248	.oscillator_frequency = 24E6,
	249	};
	250
	251	static struct spi_board_info cpuimx51sd_spi_device[] = {
	252	{
	253	.modalias = "mcp2515",
8c3f2d7a	254	.max_speed_hz = 10000000,
70b17268 EB	255	.bus_num = 0,
	256	.mode = SPI_MODE_0,
	257	.chip_select = 0,
	258	.platform_data = &mcp251x_info,
84715dd6	259	/* irq number is run-time assigned */
70b17268 EB	260	},
	261	};
	262
	263	static int cpuimx51sd_spi1_cs[] = {
	264	CAN_NCS,
	265	};
	266
	267	static const struct spi_imx_master cpuimx51sd_ecspi1_pdata __initconst = {
	268	.chipselect = cpuimx51sd_spi1_cs,
	269	.num_chipselect = ARRAY_SIZE(cpuimx51sd_spi1_cs),
	270	};
	271
7138a7f9	272	static struct platform_device *rev2_platform_devices[] __initdata = {
70b17268 EB	273	&hsi2c_gpio_device,
	274	};
	275
7138a7f9 EB	276	static const struct imxi2c_platform_data cpuimx51sd_i2c_data __initconst = {
	277	.bitrate = 100000,
	278	};
	279
70b17268 EB	280	static void __init eukrea_cpuimx51sd_init(void)
70b17268 EB	281	{
b78d8e59 SG	282	imx51_soc_init();
b78d8e59 SG	283
70b17268 EB	284	mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
	285	ARRAY_SIZE(eukrea_cpuimx51sd_pads));
	286
	287	imx51_add_imx_uart(0, &uart_pdata);
	288	imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
bec31a85	289	imx51_add_imx2_wdt(0);
70b17268 EB	290
	291	gpio_request(ETH_RST, "eth_rst");
	292	gpio_set_value(ETH_RST, 1);
	293	imx51_add_fec(NULL);
	294
	295	gpio_request(CAN_IRQGPIO, "can_irq");
	296	gpio_direction_input(CAN_IRQGPIO);
	297	gpio_free(CAN_IRQGPIO);
	298	gpio_request(CAN_NCS, "can_ncs");
	299	gpio_direction_output(CAN_NCS, 1);
	300	gpio_free(CAN_NCS);
	301	gpio_request(CAN_RST, "can_rst");
	302	gpio_direction_output(CAN_RST, 0);
	303	msleep(20);
	304	gpio_set_value(CAN_RST, 1);
	305	imx51_add_ecspi(0, &cpuimx51sd_ecspi1_pdata);
84715dd6	306	cpuimx51sd_spi_device[0].irq = gpio_to_irq(CAN_IRQGPIO);
70b17268 EB	307	spi_register_board_info(cpuimx51sd_spi_device,
	308	ARRAY_SIZE(cpuimx51sd_spi_device));
	309
7138a7f9 EB	310	if (mx51_revision() < IMX_CHIP_REVISION_3_0) {
	311	eukrea_cpuimx51sd_i2c_devices[1].irq =
	312	gpio_to_irq(TSC2007_IRQGPIO_REV2),
	313	platform_add_devices(rev2_platform_devices,
	314	ARRAY_SIZE(rev2_platform_devices));
	315	gpio_request(TSC2007_IRQGPIO_REV2, "tsc2007_irq");
	316	gpio_direction_input(TSC2007_IRQGPIO_REV2);
	317	gpio_free(TSC2007_IRQGPIO_REV2);
	318	} else {
	319	eukrea_cpuimx51sd_i2c_devices[1].irq =
	320	gpio_to_irq(TSC2007_IRQGPIO_REV3),
	321	imx51_add_imx_i2c(0, &cpuimx51sd_i2c_data);
	322	gpio_request(TSC2007_IRQGPIO_REV3, "tsc2007_irq");
	323	gpio_direction_input(TSC2007_IRQGPIO_REV3);
	324	gpio_free(TSC2007_IRQGPIO_REV3);
	325	}
70b17268 EB	326
	327	i2c_register_board_info(0, eukrea_cpuimx51sd_i2c_devices,
	328	ARRAY_SIZE(eukrea_cpuimx51sd_i2c_devices));
70b17268 EB	329
70b17268 EB	330	if (otg_mode_host)
7d92e8e6	331	imx51_add_mxc_ehci_otg(&dr_utmi_config);
70b17268 EB	332	else {
70b17268 EB	333	initialize_otg_port(NULL);
6cafe48a	334	imx51_add_fsl_usb2_udc(&usb_pdata);
70b17268 EB	335	}
	336
	337	gpio_request(USBH1_RST, "usb_rst");
	338	gpio_direction_output(USBH1_RST, 0);
	339	msleep(20);
	340	gpio_set_value(USBH1_RST, 1);
7d92e8e6	341	imx51_add_mxc_ehci_hs(1, &usbh1_config);
70b17268 EB	342
	343	#ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD
	344	eukrea_mbimxsd51_baseboard_init();
	345	#endif
	346	}
	347
	348	static void __init eukrea_cpuimx51sd_timer_init(void)
	349	{
	350	mx51_clocks_init(32768, 24000000, 22579200, 0);
	351	}
	352
70b17268 EB	353	MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
70b17268 EB	354	/* Maintainer: Eric Bénard <eric@eukrea.com> */
6192935c	355	.atag_offset = 0x100,
70b17268	356	.map_io = mx51_map_io,
ab130421	357	.init_early = imx51_init_early,
70b17268	358	.init_irq = mx51_init_irq,
ffa2ea3f	359	.handle_irq = imx51_handle_irq,
6bb27d73	360	.init_time = eukrea_cpuimx51sd_timer_init,
ab130421	361	.init_machine = eukrea_cpuimx51sd_init,
8321b758	362	.init_late = imx51_init_late,
65ea7884	363	.restart = mxc_restart,
70b17268	364	MACHINE_END