[deliverable/linux.git] / arch / arm / mach-imx / mach-cpuimx51sd.c

/*
 *
 * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
 *
 * based on board-mx51_babbage.c which is
 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/i2c/tsc2007.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/i2c-gpio.h>
#include <linux/spi/spi.h>
#include <linux/can/platform/mcp251x.h>

#include <mach/eukrea-baseboards.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx51.h>

#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>

#include "devices-imx51.h"
#include "cpu_op-mx51.h"

#define USBH1_RST		IMX_GPIO_NR(2, 28)
#define ETH_RST			IMX_GPIO_NR(2, 31)
#define TSC2007_IRQGPIO_REV2	IMX_GPIO_NR(3, 12)
#define TSC2007_IRQGPIO_REV3	IMX_GPIO_NR(4, 0)
#define CAN_IRQGPIO		IMX_GPIO_NR(1, 1)
#define CAN_RST			IMX_GPIO_NR(4, 15)
#define CAN_NCS			IMX_GPIO_NR(4, 24)
#define CAN_RXOBF_REV2		IMX_GPIO_NR(1, 4)
#define CAN_RXOBF_REV3		IMX_GPIO_NR(3, 12)
#define CAN_RX1BF		IMX_GPIO_NR(1, 6)
#define CAN_TXORTS		IMX_GPIO_NR(1, 7)
#define CAN_TX1RTS		IMX_GPIO_NR(1, 8)
#define CAN_TX2RTS		IMX_GPIO_NR(1, 9)
#define I2C_SCL			IMX_GPIO_NR(4, 16)
#define I2C_SDA			IMX_GPIO_NR(4, 17)

/* USB_CTRL_1 */
#define MX51_USB_CTRL_1_OFFSET		0x10
#define MX51_USB_CTRL_UH1_EXT_CLK_EN	(1 << 25)

#define	MX51_USB_PLLDIV_12_MHZ		0x00
#define	MX51_USB_PLL_DIV_19_2_MHZ	0x01
#define	MX51_USB_PLL_DIV_24_MHZ		0x02

static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
	/* UART1 */
	MX51_PAD_UART1_RXD__UART1_RXD,
	MX51_PAD_UART1_TXD__UART1_TXD,
	MX51_PAD_UART1_RTS__UART1_RTS,
	MX51_PAD_UART1_CTS__UART1_CTS,

	/* USB HOST1 */
	MX51_PAD_USBH1_CLK__USBH1_CLK,
	MX51_PAD_USBH1_DIR__USBH1_DIR,
	MX51_PAD_USBH1_NXT__USBH1_NXT,
	MX51_PAD_USBH1_DATA0__USBH1_DATA0,
	MX51_PAD_USBH1_DATA1__USBH1_DATA1,
	MX51_PAD_USBH1_DATA2__USBH1_DATA2,
	MX51_PAD_USBH1_DATA3__USBH1_DATA3,
	MX51_PAD_USBH1_DATA4__USBH1_DATA4,
	MX51_PAD_USBH1_DATA5__USBH1_DATA5,
	MX51_PAD_USBH1_DATA6__USBH1_DATA6,
	MX51_PAD_USBH1_DATA7__USBH1_DATA7,
	MX51_PAD_USBH1_STP__USBH1_STP,
	MX51_PAD_EIM_CS3__GPIO2_28,		/* PHY nRESET */

	/* FEC */
	MX51_PAD_EIM_DTACK__GPIO2_31,		/* PHY nRESET */

	/* HSI2C */
	MX51_PAD_I2C1_CLK__GPIO4_16,
	MX51_PAD_I2C1_DAT__GPIO4_17,

	/* I2C1 */
	MX51_PAD_SD2_CMD__I2C1_SCL,
	MX51_PAD_SD2_CLK__I2C1_SDA,

	/* CAN */
	MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
	MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
	MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
	MX51_PAD_CSPI1_SS0__GPIO4_24,		/* nCS */
	MX51_PAD_CSI2_PIXCLK__GPIO4_15,		/* nReset */
	MX51_PAD_GPIO1_1__GPIO1_1,		/* IRQ */
	MX51_PAD_GPIO1_4__GPIO1_4,		/* Control signals */
	MX51_PAD_GPIO1_6__GPIO1_6,
	MX51_PAD_GPIO1_7__GPIO1_7,
	MX51_PAD_GPIO1_8__GPIO1_8,
	MX51_PAD_GPIO1_9__GPIO1_9,

	/* Touchscreen */
	/* IRQ */
	NEW_PAD_CTRL(MX51_PAD_GPIO_NAND__GPIO_NAND, PAD_CTL_PUS_22K_UP |
			PAD_CTL_PKE | PAD_CTL_SRE_FAST |
			PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
	NEW_PAD_CTRL(MX51_PAD_NANDF_D8__GPIO4_0, PAD_CTL_PUS_22K_UP |
			PAD_CTL_PKE | PAD_CTL_SRE_FAST |
			PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
};

static const struct imxuart_platform_data uart_pdata __initconst = {
	.flags = IMXUART_HAVE_RTSCTS,
};

static int tsc2007_get_pendown_state(void)
{
	if (mx51_revision() < IMX_CHIP_REVISION_3_0)
		return !gpio_get_value(TSC2007_IRQGPIO_REV2);
	else
		return !gpio_get_value(TSC2007_IRQGPIO_REV3);
}

static struct tsc2007_platform_data tsc2007_info = {
	.model			= 2007,
	.x_plate_ohms		= 180,
	.get_pendown_state	= tsc2007_get_pendown_state,
};

static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
	{
		I2C_BOARD_INFO("pcf8563", 0x51),
	}, {
		I2C_BOARD_INFO("tsc2007", 0x49),
		.platform_data	= &tsc2007_info,
	},
};

static const struct mxc_nand_platform_data
		eukrea_cpuimx51sd_nand_board_info __initconst = {
	.width		= 1,
	.hw_ecc		= 1,
	.flash_bbt	= 1,
};

/* This function is board specific as the bit mask for the plldiv will also
be different for other Freescale SoCs, thus a common bitmask is not
possible and cannot get place in /plat-mxc/ehci.c.*/
static int initialize_otg_port(struct platform_device *pdev)
{
	u32 v;
	void __iomem *usb_base;
	void __iomem *usbother_base;

	usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
	if (!usb_base)
		return -ENOMEM;
	usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;

	/* Set the PHY clock to 19.2MHz */
	v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
	v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
	v |= MX51_USB_PLL_DIV_19_2_MHZ;
	__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
	iounmap(usb_base);

	mdelay(10);

	return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
}

static int initialize_usbh1_port(struct platform_device *pdev)
{
	u32 v;
	void __iomem *usb_base;
	void __iomem *usbother_base;

	usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
	if (!usb_base)
		return -ENOMEM;
	usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;

	/* The clock for the USBH1 ULPI port will come from the PHY. */
	v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
	__raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
			usbother_base + MX51_USB_CTRL_1_OFFSET);
	iounmap(usb_base);

	mdelay(10);

	return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
			MXC_EHCI_ITC_NO_THRESHOLD);
}

static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
	.init		= initialize_otg_port,
	.portsc	= MXC_EHCI_UTMI_16BIT,
};

static const struct fsl_usb2_platform_data usb_pdata __initconst = {
	.operating_mode	= FSL_USB2_DR_DEVICE,
	.phy_mode	= FSL_USB2_PHY_UTMI_WIDE,
};

static const struct mxc_usbh_platform_data usbh1_config __initconst = {
	.init		= initialize_usbh1_port,
	.portsc	= MXC_EHCI_MODE_ULPI,
};

static int otg_mode_host;

static int __init eukrea_cpuimx51sd_otg_mode(char *options)
{
	if (!strcmp(options, "host"))
		otg_mode_host = 1;
	else if (!strcmp(options, "device"))
		otg_mode_host = 0;
	else
		pr_info("otg_mode neither \"host\" nor \"device\". "
			"Defaulting to device\n");
	return 0;
}
__setup("otg_mode=", eukrea_cpuimx51sd_otg_mode);

static struct i2c_gpio_platform_data pdata = {
	.sda_pin		= I2C_SDA,
	.sda_is_open_drain	= 0,
	.scl_pin		= I2C_SCL,
	.scl_is_open_drain	= 0,
	.udelay			= 2,
};

static struct platform_device hsi2c_gpio_device = {
	.name			= "i2c-gpio",
	.id			= 0,
	.dev.platform_data	= &pdata,
};

static struct mcp251x_platform_data mcp251x_info = {
	.oscillator_frequency = 24E6,
};

static struct spi_board_info cpuimx51sd_spi_device[] = {
	{
		.modalias        = "mcp2515",
		.max_speed_hz    = 10000000,
		.bus_num         = 0,
		.mode		= SPI_MODE_0,
		.chip_select     = 0,
		.platform_data   = &mcp251x_info,
		.irq             = IMX_GPIO_TO_IRQ(CAN_IRQGPIO)
	},
};

static int cpuimx51sd_spi1_cs[] = {
	CAN_NCS,
};

static const struct spi_imx_master cpuimx51sd_ecspi1_pdata __initconst = {
	.chipselect	= cpuimx51sd_spi1_cs,
	.num_chipselect	= ARRAY_SIZE(cpuimx51sd_spi1_cs),
};

static struct platform_device *rev2_platform_devices[] __initdata = {
	&hsi2c_gpio_device,
};

static const struct imxi2c_platform_data cpuimx51sd_i2c_data __initconst = {
	.bitrate = 100000,
};

static void __init eukrea_cpuimx51sd_init(void)
{
	imx51_soc_init();

	mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
					ARRAY_SIZE(eukrea_cpuimx51sd_pads));

#if defined(CONFIG_CPU_FREQ_IMX)
	get_cpu_op = mx51_get_cpu_op;
#endif

	imx51_add_imx_uart(0, &uart_pdata);
	imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
	imx51_add_imx2_wdt(0, NULL);

	gpio_request(ETH_RST, "eth_rst");
	gpio_set_value(ETH_RST, 1);
	imx51_add_fec(NULL);

	gpio_request(CAN_IRQGPIO, "can_irq");
	gpio_direction_input(CAN_IRQGPIO);
	gpio_free(CAN_IRQGPIO);
	gpio_request(CAN_NCS, "can_ncs");
	gpio_direction_output(CAN_NCS, 1);
	gpio_free(CAN_NCS);
	gpio_request(CAN_RST, "can_rst");
	gpio_direction_output(CAN_RST, 0);
	msleep(20);
	gpio_set_value(CAN_RST, 1);
	imx51_add_ecspi(0, &cpuimx51sd_ecspi1_pdata);
	spi_register_board_info(cpuimx51sd_spi_device,
				ARRAY_SIZE(cpuimx51sd_spi_device));

	if (mx51_revision() < IMX_CHIP_REVISION_3_0) {
		eukrea_cpuimx51sd_i2c_devices[1].irq =
			gpio_to_irq(TSC2007_IRQGPIO_REV2),
		platform_add_devices(rev2_platform_devices,
			ARRAY_SIZE(rev2_platform_devices));
		gpio_request(TSC2007_IRQGPIO_REV2, "tsc2007_irq");
		gpio_direction_input(TSC2007_IRQGPIO_REV2);
		gpio_free(TSC2007_IRQGPIO_REV2);
	} else {
		eukrea_cpuimx51sd_i2c_devices[1].irq =
			gpio_to_irq(TSC2007_IRQGPIO_REV3),
		imx51_add_imx_i2c(0, &cpuimx51sd_i2c_data);
		gpio_request(TSC2007_IRQGPIO_REV3, "tsc2007_irq");
		gpio_direction_input(TSC2007_IRQGPIO_REV3);
		gpio_free(TSC2007_IRQGPIO_REV3);
	}

	i2c_register_board_info(0, eukrea_cpuimx51sd_i2c_devices,
			ARRAY_SIZE(eukrea_cpuimx51sd_i2c_devices));

	if (otg_mode_host)
		imx51_add_mxc_ehci_otg(&dr_utmi_config);
	else {
		initialize_otg_port(NULL);
		imx51_add_fsl_usb2_udc(&usb_pdata);
	}

	gpio_request(USBH1_RST, "usb_rst");
	gpio_direction_output(USBH1_RST, 0);
	msleep(20);
	gpio_set_value(USBH1_RST, 1);
	imx51_add_mxc_ehci_hs(1, &usbh1_config);

#ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD
	eukrea_mbimxsd51_baseboard_init();
#endif
}

static void __init eukrea_cpuimx51sd_timer_init(void)
{
	mx51_clocks_init(32768, 24000000, 22579200, 0);
}

static struct sys_timer mxc_timer = {
	.init	= eukrea_cpuimx51sd_timer_init,
};

MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
	/* Maintainer: Eric Bénard <eric@eukrea.com> */
	.atag_offset = 0x100,
	.map_io = mx51_map_io,
	.init_early = imx51_init_early,
	.init_irq = mx51_init_irq,
	.handle_irq = imx51_handle_irq,
	.timer = &mxc_timer,
	.init_machine = eukrea_cpuimx51sd_init,
	.init_late	= imx51_init_late,
	.restart	= mxc_restart,
MACHINE_END
Commit	Line	Data
70b17268 EB	1	/*
	2	*
	3	* Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
	4	*
	5	* based on board-mx51_babbage.c which is
	6	* Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
	7	* Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
	8	*
	9	* The code contained herein is licensed under the GNU General Public
	10	* License. You may obtain a copy of the GNU General Public License
	11	* Version 2 or later at the following locations:
	12	*
	13	* http://www.opensource.org/licenses/gpl-license.html
	14	* http://www.gnu.org/copyleft/gpl.html
	15	*/
	16
	17	#include <linux/init.h>
	18	#include <linux/platform_device.h>
	19	#include <linux/i2c.h>
	20	#include <linux/i2c/tsc2007.h>
	21	#include <linux/gpio.h>
	22	#include <linux/delay.h>
	23	#include <linux/io.h>
	24	#include <linux/interrupt.h>
70b17268 EB	25	#include <linux/i2c-gpio.h>
	26	#include <linux/spi/spi.h>
	27	#include <linux/can/platform/mcp251x.h>
	28
	29	#include <mach/eukrea-baseboards.h>
	30	#include <mach/common.h>
	31	#include <mach/hardware.h>
	32	#include <mach/iomux-mx51.h>
70b17268	33
70b17268 EB	34	#include <asm/setup.h>
	35	#include <asm/mach-types.h>
	36	#include <asm/mach/arch.h>
	37	#include <asm/mach/time.h>
	38
	39	#include "devices-imx51.h"
b1372146	40	#include "cpu_op-mx51.h"
70b17268	41
96886c43 APR	42	#define USBH1_RST IMX_GPIO_NR(2, 28)
96886c43 APR	43	#define ETH_RST IMX_GPIO_NR(2, 31)
7138a7f9 EB	44	#define TSC2007_IRQGPIO_REV2 IMX_GPIO_NR(3, 12)
7138a7f9 EB	45	#define TSC2007_IRQGPIO_REV3 IMX_GPIO_NR(4, 0)
96886c43 APR	46	#define CAN_IRQGPIO IMX_GPIO_NR(1, 1)
	47	#define CAN_RST IMX_GPIO_NR(4, 15)
	48	#define CAN_NCS IMX_GPIO_NR(4, 24)
7138a7f9 EB	49	#define CAN_RXOBF_REV2 IMX_GPIO_NR(1, 4)
7138a7f9 EB	50	#define CAN_RXOBF_REV3 IMX_GPIO_NR(3, 12)
96886c43 APR	51	#define CAN_RX1BF IMX_GPIO_NR(1, 6)
	52	#define CAN_TXORTS IMX_GPIO_NR(1, 7)
	53	#define CAN_TX1RTS IMX_GPIO_NR(1, 8)
	54	#define CAN_TX2RTS IMX_GPIO_NR(1, 9)
	55	#define I2C_SCL IMX_GPIO_NR(4, 16)
	56	#define I2C_SDA IMX_GPIO_NR(4, 17)
70b17268 EB	57
	58	/* USB_CTRL_1 */
	59	#define MX51_USB_CTRL_1_OFFSET 0x10
	60	#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
	61
	62	#define MX51_USB_PLLDIV_12_MHZ 0x00
	63	#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
	64	#define MX51_USB_PLL_DIV_24_MHZ 0x02
	65
8f5260c8	66	static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
70b17268 EB	67	/* UART1 */
	68	MX51_PAD_UART1_RXD__UART1_RXD,
	69	MX51_PAD_UART1_TXD__UART1_TXD,
	70	MX51_PAD_UART1_RTS__UART1_RTS,
	71	MX51_PAD_UART1_CTS__UART1_CTS,
	72
	73	/* USB HOST1 */
	74	MX51_PAD_USBH1_CLK__USBH1_CLK,
	75	MX51_PAD_USBH1_DIR__USBH1_DIR,
	76	MX51_PAD_USBH1_NXT__USBH1_NXT,
	77	MX51_PAD_USBH1_DATA0__USBH1_DATA0,
	78	MX51_PAD_USBH1_DATA1__USBH1_DATA1,
	79	MX51_PAD_USBH1_DATA2__USBH1_DATA2,
	80	MX51_PAD_USBH1_DATA3__USBH1_DATA3,
	81	MX51_PAD_USBH1_DATA4__USBH1_DATA4,
	82	MX51_PAD_USBH1_DATA5__USBH1_DATA5,
	83	MX51_PAD_USBH1_DATA6__USBH1_DATA6,
	84	MX51_PAD_USBH1_DATA7__USBH1_DATA7,
	85	MX51_PAD_USBH1_STP__USBH1_STP,
ee1ae4d7	86	MX51_PAD_EIM_CS3__GPIO2_28, /* PHY nRESET */
70b17268 EB	87
70b17268 EB	88	/* FEC */
ee1ae4d7	89	MX51_PAD_EIM_DTACK__GPIO2_31, /* PHY nRESET */
70b17268 EB	90
70b17268 EB	91	/* HSI2C */
ee1ae4d7 SH	92	MX51_PAD_I2C1_CLK__GPIO4_16,
ee1ae4d7 SH	93	MX51_PAD_I2C1_DAT__GPIO4_17,
70b17268	94
7138a7f9 EB	95	/* I2C1 */
	96	MX51_PAD_SD2_CMD__I2C1_SCL,
	97	MX51_PAD_SD2_CLK__I2C1_SDA,
	98
70b17268 EB	99	/* CAN */
	100	MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
	101	MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
	102	MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
ee1ae4d7 SH	103	MX51_PAD_CSPI1_SS0__GPIO4_24, /* nCS */
	104	MX51_PAD_CSI2_PIXCLK__GPIO4_15, /* nReset */
	105	MX51_PAD_GPIO1_1__GPIO1_1, /* IRQ */
	106	MX51_PAD_GPIO1_4__GPIO1_4, /* Control signals */
	107	MX51_PAD_GPIO1_6__GPIO1_6,
	108	MX51_PAD_GPIO1_7__GPIO1_7,
	109	MX51_PAD_GPIO1_8__GPIO1_8,
	110	MX51_PAD_GPIO1_9__GPIO1_9,
70b17268 EB	111
70b17268 EB	112	/* Touchscreen */
ee1ae4d7	113	/* IRQ */
7242e24a	114	NEW_PAD_CTRL(MX51_PAD_GPIO_NAND__GPIO_NAND, PAD_CTL_PUS_22K_UP \|
ee1ae4d7 SH	115	PAD_CTL_PKE \| PAD_CTL_SRE_FAST \|
ee1ae4d7 SH	116	PAD_CTL_DSE_HIGH \| PAD_CTL_PUE \| PAD_CTL_HYS),
7138a7f9 EB	117	NEW_PAD_CTRL(MX51_PAD_NANDF_D8__GPIO4_0, PAD_CTL_PUS_22K_UP \|
	118	PAD_CTL_PKE \| PAD_CTL_SRE_FAST \|
	119	PAD_CTL_DSE_HIGH \| PAD_CTL_PUE \| PAD_CTL_HYS),
70b17268 EB	120	};
	121
	122	static const struct imxuart_platform_data uart_pdata __initconst = {
	123	.flags = IMXUART_HAVE_RTSCTS,
	124	};
	125
7138a7f9 EB	126	static int tsc2007_get_pendown_state(void)
	127	{
	128	if (mx51_revision() < IMX_CHIP_REVISION_3_0)
	129	return !gpio_get_value(TSC2007_IRQGPIO_REV2);
	130	else
	131	return !gpio_get_value(TSC2007_IRQGPIO_REV3);
	132	}
	133
70b17268 EB	134	static struct tsc2007_platform_data tsc2007_info = {
	135	.model = 2007,
	136	.x_plate_ohms = 180,
7138a7f9	137	.get_pendown_state = tsc2007_get_pendown_state,
70b17268 EB	138	};
	139
	140	static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
	141	{
	142	I2C_BOARD_INFO("pcf8563", 0x51),
	143	}, {
	144	I2C_BOARD_INFO("tsc2007", 0x49),
70b17268	145	.platform_data = &tsc2007_info,
70b17268 EB	146	},
	147	};
	148
	149	static const struct mxc_nand_platform_data
	150	eukrea_cpuimx51sd_nand_board_info __initconst = {
	151	.width = 1,
	152	.hw_ecc = 1,
	153	.flash_bbt = 1,
	154	};
	155
	156	/* This function is board specific as the bit mask for the plldiv will also
	157	be different for other Freescale SoCs, thus a common bitmask is not
	158	possible and cannot get place in /plat-mxc/ehci.c.*/
	159	static int initialize_otg_port(struct platform_device *pdev)
	160	{
	161	u32 v;
	162	void __iomem *usb_base;
	163	void __iomem *usbother_base;
	164
7d92e8e6	165	usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
28a4f908 FE	166	if (!usb_base)
28a4f908 FE	167	return -ENOMEM;
70b17268 EB	168	usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
	169
	170	/* Set the PHY clock to 19.2MHz */
	171	v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
	172	v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
	173	v \|= MX51_USB_PLL_DIV_19_2_MHZ;
	174	__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
	175	iounmap(usb_base);
4bd597b6 SH	176
	177	mdelay(10);
	178
	179	return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
70b17268 EB	180	}
	181
	182	static int initialize_usbh1_port(struct platform_device *pdev)
	183	{
	184	u32 v;
	185	void __iomem *usb_base;
	186	void __iomem *usbother_base;
	187
7d92e8e6	188	usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
28a4f908 FE	189	if (!usb_base)
28a4f908 FE	190	return -ENOMEM;
70b17268 EB	191	usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
	192
	193	/* The clock for the USBH1 ULPI port will come from the PHY. */
	194	v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
	195	__raw_writel(v \| MX51_USB_CTRL_UH1_EXT_CLK_EN,
	196	usbother_base + MX51_USB_CTRL_1_OFFSET);
	197	iounmap(usb_base);
4bd597b6 SH	198
	199	mdelay(10);
	200
	201	return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED \|
	202	MXC_EHCI_ITC_NO_THRESHOLD);
70b17268 EB	203	}
70b17268 EB	204
7d92e8e6	205	static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
70b17268 EB	206	.init = initialize_otg_port,
70b17268 EB	207	.portsc = MXC_EHCI_UTMI_16BIT,
70b17268 EB	208	};
70b17268 EB	209
6cafe48a	210	static const struct fsl_usb2_platform_data usb_pdata __initconst = {
70b17268 EB	211	.operating_mode = FSL_USB2_DR_DEVICE,
	212	.phy_mode = FSL_USB2_PHY_UTMI_WIDE,
	213	};
	214
7d92e8e6	215	static const struct mxc_usbh_platform_data usbh1_config __initconst = {
70b17268 EB	216	.init = initialize_usbh1_port,
70b17268 EB	217	.portsc = MXC_EHCI_MODE_ULPI,
70b17268 EB	218	};
	219
	220	static int otg_mode_host;
	221
	222	static int __init eukrea_cpuimx51sd_otg_mode(char *options)
	223	{
	224	if (!strcmp(options, "host"))
	225	otg_mode_host = 1;
	226	else if (!strcmp(options, "device"))
	227	otg_mode_host = 0;
	228	else
	229	pr_info("otg_mode neither \"host\" nor \"device\". "
	230	"Defaulting to device\n");
	231	return 0;
	232	}
	233	__setup("otg_mode=", eukrea_cpuimx51sd_otg_mode);
	234
	235	static struct i2c_gpio_platform_data pdata = {
	236	.sda_pin = I2C_SDA,
	237	.sda_is_open_drain = 0,
	238	.scl_pin = I2C_SCL,
	239	.scl_is_open_drain = 0,
	240	.udelay = 2,
	241	};
	242
	243	static struct platform_device hsi2c_gpio_device = {
	244	.name = "i2c-gpio",
	245	.id = 0,
	246	.dev.platform_data = &pdata,
	247	};
	248
	249	static struct mcp251x_platform_data mcp251x_info = {
	250	.oscillator_frequency = 24E6,
	251	};
	252
	253	static struct spi_board_info cpuimx51sd_spi_device[] = {
	254	{
	255	.modalias = "mcp2515",
8c3f2d7a	256	.max_speed_hz = 10000000,
70b17268 EB	257	.bus_num = 0,
	258	.mode = SPI_MODE_0,
	259	.chip_select = 0,
	260	.platform_data = &mcp251x_info,
e309fb18	261	.irq = IMX_GPIO_TO_IRQ(CAN_IRQGPIO)
70b17268 EB	262	},
	263	};
	264
	265	static int cpuimx51sd_spi1_cs[] = {
	266	CAN_NCS,
	267	};
	268
	269	static const struct spi_imx_master cpuimx51sd_ecspi1_pdata __initconst = {
	270	.chipselect = cpuimx51sd_spi1_cs,
	271	.num_chipselect = ARRAY_SIZE(cpuimx51sd_spi1_cs),
	272	};
	273
7138a7f9	274	static struct platform_device *rev2_platform_devices[] __initdata = {
70b17268 EB	275	&hsi2c_gpio_device,
	276	};
	277
7138a7f9 EB	278	static const struct imxi2c_platform_data cpuimx51sd_i2c_data __initconst = {
	279	.bitrate = 100000,
	280	};
	281
70b17268 EB	282	static void __init eukrea_cpuimx51sd_init(void)
70b17268 EB	283	{
b78d8e59 SG	284	imx51_soc_init();
b78d8e59 SG	285
70b17268 EB	286	mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
	287	ARRAY_SIZE(eukrea_cpuimx51sd_pads));
	288
b1372146 EB	289	#if defined(CONFIG_CPU_FREQ_IMX)
	290	get_cpu_op = mx51_get_cpu_op;
	291	#endif
	292
70b17268 EB	293	imx51_add_imx_uart(0, &uart_pdata);
70b17268 EB	294	imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
f5c85d92	295	imx51_add_imx2_wdt(0, NULL);
70b17268 EB	296
	297	gpio_request(ETH_RST, "eth_rst");
	298	gpio_set_value(ETH_RST, 1);
	299	imx51_add_fec(NULL);
	300
	301	gpio_request(CAN_IRQGPIO, "can_irq");
	302	gpio_direction_input(CAN_IRQGPIO);
	303	gpio_free(CAN_IRQGPIO);
	304	gpio_request(CAN_NCS, "can_ncs");
	305	gpio_direction_output(CAN_NCS, 1);
	306	gpio_free(CAN_NCS);
	307	gpio_request(CAN_RST, "can_rst");
	308	gpio_direction_output(CAN_RST, 0);
	309	msleep(20);
	310	gpio_set_value(CAN_RST, 1);
	311	imx51_add_ecspi(0, &cpuimx51sd_ecspi1_pdata);
	312	spi_register_board_info(cpuimx51sd_spi_device,
	313	ARRAY_SIZE(cpuimx51sd_spi_device));
	314
7138a7f9 EB	315	if (mx51_revision() < IMX_CHIP_REVISION_3_0) {
	316	eukrea_cpuimx51sd_i2c_devices[1].irq =
	317	gpio_to_irq(TSC2007_IRQGPIO_REV2),
	318	platform_add_devices(rev2_platform_devices,
	319	ARRAY_SIZE(rev2_platform_devices));
	320	gpio_request(TSC2007_IRQGPIO_REV2, "tsc2007_irq");
	321	gpio_direction_input(TSC2007_IRQGPIO_REV2);
	322	gpio_free(TSC2007_IRQGPIO_REV2);
	323	} else {
	324	eukrea_cpuimx51sd_i2c_devices[1].irq =
	325	gpio_to_irq(TSC2007_IRQGPIO_REV3),
	326	imx51_add_imx_i2c(0, &cpuimx51sd_i2c_data);
	327	gpio_request(TSC2007_IRQGPIO_REV3, "tsc2007_irq");
	328	gpio_direction_input(TSC2007_IRQGPIO_REV3);
	329	gpio_free(TSC2007_IRQGPIO_REV3);
	330	}
70b17268 EB	331
	332	i2c_register_board_info(0, eukrea_cpuimx51sd_i2c_devices,
	333	ARRAY_SIZE(eukrea_cpuimx51sd_i2c_devices));
70b17268 EB	334
70b17268 EB	335	if (otg_mode_host)
7d92e8e6	336	imx51_add_mxc_ehci_otg(&dr_utmi_config);
70b17268 EB	337	else {
70b17268 EB	338	initialize_otg_port(NULL);
6cafe48a	339	imx51_add_fsl_usb2_udc(&usb_pdata);
70b17268 EB	340	}
	341
	342	gpio_request(USBH1_RST, "usb_rst");
	343	gpio_direction_output(USBH1_RST, 0);
	344	msleep(20);
	345	gpio_set_value(USBH1_RST, 1);
7d92e8e6	346	imx51_add_mxc_ehci_hs(1, &usbh1_config);
70b17268 EB	347
	348	#ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD
	349	eukrea_mbimxsd51_baseboard_init();
	350	#endif
	351	}
	352
	353	static void __init eukrea_cpuimx51sd_timer_init(void)
	354	{
	355	mx51_clocks_init(32768, 24000000, 22579200, 0);
	356	}
	357
	358	static struct sys_timer mxc_timer = {
	359	.init = eukrea_cpuimx51sd_timer_init,
	360	};
	361
	362	MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
	363	/* Maintainer: Eric Bénard <eric@eukrea.com> */
6192935c	364	.atag_offset = 0x100,
70b17268	365	.map_io = mx51_map_io,
ab130421	366	.init_early = imx51_init_early,
70b17268	367	.init_irq = mx51_init_irq,
ffa2ea3f	368	.handle_irq = imx51_handle_irq,
70b17268	369	.timer = &mxc_timer,
ab130421	370	.init_machine = eukrea_cpuimx51sd_init,
8321b758	371	.init_late = imx51_init_late,
65ea7884	372	.restart = mxc_restart,
70b17268	373	MACHINE_END