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3b161e51 JM |
1 | /* |
2 | * mach-imx27_visstrim_m10.c | |
3 | * | |
4 | * Copyright 2010 Javier Martin <javier.martin@vista-silicon.com> | |
5 | * | |
6 | * Based on mach-pcm038.c, mach-pca100.c, mach-mx27ads.c and others. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
21 | * MA 02110-1301, USA. | |
22 | */ | |
23 | ||
24 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
25 | ||
26 | #include <linux/platform_device.h> | |
27 | #include <linux/mtd/physmap.h> | |
28 | #include <linux/i2c.h> | |
29 | #include <linux/i2c/pca953x.h> | |
3b161e51 JM |
30 | #include <linux/input.h> |
31 | #include <linux/gpio.h> | |
4bd597b6 | 32 | #include <linux/delay.h> |
f52f5a55 | 33 | #include <linux/dma-mapping.h> |
acb6464c | 34 | #include <linux/leds.h> |
f52f5a55 JM |
35 | #include <linux/memblock.h> |
36 | #include <media/soc_camera.h> | |
c86566bb | 37 | #include <sound/tlv320aic32x4.h> |
3b161e51 JM |
38 | #include <asm/mach-types.h> |
39 | #include <asm/mach/arch.h> | |
40 | #include <asm/mach/time.h> | |
41 | #include <mach/common.h> | |
c0450dff | 42 | #include <mach/iomux-mx27.h> |
3b161e51 JM |
43 | |
44 | #include "devices-imx27.h" | |
3b161e51 | 45 | |
f52f5a55 JM |
46 | #define TVP5150_RSTN (GPIO_PORTC + 18) |
47 | #define TVP5150_PWDN (GPIO_PORTC + 19) | |
3b161e51 JM |
48 | #define OTG_PHY_CS_GPIO (GPIO_PORTF + 17) |
49 | #define SDHC1_IRQ IRQ_GPIOB(25) | |
50 | ||
6c80ee51 | 51 | static const int visstrim_m10_pins[] __initconst = { |
3b161e51 JM |
52 | /* UART1 (console) */ |
53 | PE12_PF_UART1_TXD, | |
54 | PE13_PF_UART1_RXD, | |
55 | PE14_PF_UART1_CTS, | |
56 | PE15_PF_UART1_RTS, | |
57 | /* FEC */ | |
58 | PD0_AIN_FEC_TXD0, | |
59 | PD1_AIN_FEC_TXD1, | |
60 | PD2_AIN_FEC_TXD2, | |
61 | PD3_AIN_FEC_TXD3, | |
62 | PD4_AOUT_FEC_RX_ER, | |
63 | PD5_AOUT_FEC_RXD1, | |
64 | PD6_AOUT_FEC_RXD2, | |
65 | PD7_AOUT_FEC_RXD3, | |
66 | PD8_AF_FEC_MDIO, | |
67 | PD9_AIN_FEC_MDC, | |
68 | PD10_AOUT_FEC_CRS, | |
69 | PD11_AOUT_FEC_TX_CLK, | |
70 | PD12_AOUT_FEC_RXD0, | |
71 | PD13_AOUT_FEC_RX_DV, | |
72 | PD14_AOUT_FEC_RX_CLK, | |
73 | PD15_AOUT_FEC_COL, | |
74 | PD16_AIN_FEC_TX_ER, | |
75 | PF23_AIN_FEC_TX_EN, | |
a5e2051b JM |
76 | /* SSI1 */ |
77 | PC20_PF_SSI1_FS, | |
78 | PC21_PF_SSI1_RXD, | |
79 | PC22_PF_SSI1_TXD, | |
80 | PC23_PF_SSI1_CLK, | |
3b161e51 JM |
81 | /* SDHC1 */ |
82 | PE18_PF_SD1_D0, | |
83 | PE19_PF_SD1_D1, | |
84 | PE20_PF_SD1_D2, | |
85 | PE21_PF_SD1_D3, | |
86 | PE22_PF_SD1_CMD, | |
87 | PE23_PF_SD1_CLK, | |
88 | /* Both I2Cs */ | |
89 | PD17_PF_I2C_DATA, | |
90 | PD18_PF_I2C_CLK, | |
91 | PC5_PF_I2C2_SDA, | |
92 | PC6_PF_I2C2_SCL, | |
93 | /* USB OTG */ | |
94 | OTG_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT, | |
95 | PC9_PF_USBOTG_DATA0, | |
96 | PC11_PF_USBOTG_DATA1, | |
97 | PC10_PF_USBOTG_DATA2, | |
98 | PC13_PF_USBOTG_DATA3, | |
99 | PC12_PF_USBOTG_DATA4, | |
100 | PC7_PF_USBOTG_DATA5, | |
101 | PC8_PF_USBOTG_DATA6, | |
102 | PE25_PF_USBOTG_DATA7, | |
103 | PE24_PF_USBOTG_CLK, | |
104 | PE2_PF_USBOTG_DIR, | |
105 | PE0_PF_USBOTG_NXT, | |
106 | PE1_PF_USBOTG_STP, | |
107 | PB23_PF_USB_PWR, | |
108 | PB24_PF_USB_OC, | |
f52f5a55 JM |
109 | /* CSI */ |
110 | PB10_PF_CSI_D0, | |
111 | PB11_PF_CSI_D1, | |
112 | PB12_PF_CSI_D2, | |
113 | PB13_PF_CSI_D3, | |
114 | PB14_PF_CSI_D4, | |
115 | PB15_PF_CSI_MCLK, | |
116 | PB16_PF_CSI_PIXCLK, | |
117 | PB17_PF_CSI_D5, | |
118 | PB18_PF_CSI_D6, | |
119 | PB19_PF_CSI_D7, | |
120 | PB20_PF_CSI_VSYNC, | |
121 | PB21_PF_CSI_HSYNC, | |
3b161e51 JM |
122 | }; |
123 | ||
f52f5a55 JM |
124 | /* Camera */ |
125 | static int visstrim_camera_power(struct device *dev, int on) | |
126 | { | |
127 | gpio_set_value(TVP5150_PWDN, on); | |
128 | ||
129 | return 0; | |
130 | }; | |
131 | ||
132 | static int visstrim_camera_reset(struct device *dev) | |
133 | { | |
134 | gpio_set_value(TVP5150_RSTN, 0); | |
135 | ndelay(500); | |
136 | gpio_set_value(TVP5150_RSTN, 1); | |
137 | ||
138 | return 0; | |
139 | }; | |
140 | ||
141 | static struct i2c_board_info visstrim_i2c_camera = { | |
142 | I2C_BOARD_INFO("tvp5150", 0x5d), | |
143 | }; | |
144 | ||
145 | static struct soc_camera_link iclink_tvp5150 = { | |
146 | .bus_id = 0, | |
147 | .board_info = &visstrim_i2c_camera, | |
148 | .i2c_adapter_id = 0, | |
149 | .power = visstrim_camera_power, | |
150 | .reset = visstrim_camera_reset, | |
151 | }; | |
152 | ||
153 | static struct mx2_camera_platform_data visstrim_camera = { | |
154 | .flags = MX2_CAMERA_CCIR | MX2_CAMERA_CCIR_INTERLACE | | |
155 | MX2_CAMERA_SWAP16 | MX2_CAMERA_PCLK_SAMPLE_RISING, | |
156 | .clk = 100000, | |
157 | }; | |
158 | ||
159 | static phys_addr_t mx2_camera_base __initdata; | |
160 | #define MX2_CAMERA_BUF_SIZE SZ_8M | |
161 | ||
162 | static void __init visstrim_camera_init(void) | |
163 | { | |
164 | struct platform_device *pdev; | |
165 | int dma; | |
166 | ||
167 | /* Initialize tvp5150 gpios */ | |
168 | mxc_gpio_mode(TVP5150_RSTN | GPIO_GPIO | GPIO_OUT); | |
169 | mxc_gpio_mode(TVP5150_PWDN | GPIO_GPIO | GPIO_OUT); | |
170 | gpio_set_value(TVP5150_RSTN, 1); | |
171 | gpio_set_value(TVP5150_PWDN, 0); | |
172 | ndelay(1); | |
173 | ||
174 | gpio_set_value(TVP5150_PWDN, 1); | |
175 | ndelay(1); | |
176 | gpio_set_value(TVP5150_RSTN, 0); | |
177 | ndelay(500); | |
178 | gpio_set_value(TVP5150_RSTN, 1); | |
179 | ndelay(200000); | |
180 | ||
181 | pdev = imx27_add_mx2_camera(&visstrim_camera); | |
182 | if (IS_ERR(pdev)) | |
183 | return; | |
184 | ||
185 | dma = dma_declare_coherent_memory(&pdev->dev, | |
186 | mx2_camera_base, mx2_camera_base, | |
187 | MX2_CAMERA_BUF_SIZE, | |
188 | DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); | |
189 | if (!(dma & DMA_MEMORY_MAP)) | |
190 | return; | |
191 | } | |
192 | ||
193 | static void __init visstrim_reserve(void) | |
194 | { | |
195 | /* reserve 4 MiB for mx2-camera */ | |
196 | mx2_camera_base = memblock_alloc(MX2_CAMERA_BUF_SIZE, | |
197 | MX2_CAMERA_BUF_SIZE); | |
198 | memblock_free(mx2_camera_base, MX2_CAMERA_BUF_SIZE); | |
199 | memblock_remove(mx2_camera_base, MX2_CAMERA_BUF_SIZE); | |
200 | } | |
201 | ||
3b161e51 JM |
202 | /* GPIOs used as events for applications */ |
203 | static struct gpio_keys_button visstrim_gpio_keys[] = { | |
204 | { | |
205 | .type = EV_KEY, | |
206 | .code = KEY_RESTART, | |
207 | .gpio = (GPIO_PORTC + 15), | |
208 | .desc = "Default config", | |
209 | .active_low = 0, | |
210 | .wakeup = 1, | |
211 | }, | |
212 | { | |
213 | .type = EV_KEY, | |
214 | .code = KEY_RECORD, | |
215 | .gpio = (GPIO_PORTF + 14), | |
216 | .desc = "Record", | |
217 | .active_low = 0, | |
218 | .wakeup = 1, | |
219 | }, | |
220 | { | |
221 | .type = EV_KEY, | |
222 | .code = KEY_STOP, | |
223 | .gpio = (GPIO_PORTF + 13), | |
224 | .desc = "Stop", | |
225 | .active_low = 0, | |
226 | .wakeup = 1, | |
227 | } | |
228 | }; | |
229 | ||
5309498a UKK |
230 | static const struct gpio_keys_platform_data |
231 | visstrim_gpio_keys_platform_data __initconst = { | |
3b161e51 JM |
232 | .buttons = visstrim_gpio_keys, |
233 | .nbuttons = ARRAY_SIZE(visstrim_gpio_keys), | |
234 | }; | |
235 | ||
acb6464c JM |
236 | /* led */ |
237 | static const struct gpio_led visstrim_m10_leds[] __initconst = { | |
238 | { | |
239 | .name = "visstrim:ld0", | |
240 | .default_trigger = "nand-disk", | |
241 | .gpio = (GPIO_PORTC + 29), | |
242 | }, | |
243 | { | |
244 | .name = "visstrim:ld1", | |
245 | .default_trigger = "nand-disk", | |
246 | .gpio = (GPIO_PORTC + 24), | |
247 | }, | |
248 | { | |
249 | .name = "visstrim:ld2", | |
250 | .default_trigger = "nand-disk", | |
251 | .gpio = (GPIO_PORTC + 28), | |
252 | }, | |
253 | { | |
254 | .name = "visstrim:ld3", | |
255 | .default_trigger = "nand-disk", | |
256 | .gpio = (GPIO_PORTC + 25), | |
257 | }, | |
258 | }; | |
259 | ||
260 | static const struct gpio_led_platform_data visstrim_m10_led_data __initconst = { | |
261 | .leds = visstrim_m10_leds, | |
262 | .num_leds = ARRAY_SIZE(visstrim_m10_leds), | |
263 | }; | |
264 | ||
3b161e51 JM |
265 | /* Visstrim_SM10 has a microSD slot connected to sdhc1 */ |
266 | static int visstrim_m10_sdhc1_init(struct device *dev, | |
267 | irq_handler_t detect_irq, void *data) | |
268 | { | |
269 | int ret; | |
270 | ||
271 | ret = request_irq(SDHC1_IRQ, detect_irq, IRQF_TRIGGER_FALLING, | |
272 | "mmc-detect", data); | |
273 | return ret; | |
274 | } | |
275 | ||
276 | static void visstrim_m10_sdhc1_exit(struct device *dev, void *data) | |
277 | { | |
278 | free_irq(SDHC1_IRQ, data); | |
279 | } | |
280 | ||
9d3d945a | 281 | static const struct imxmmc_platform_data visstrim_m10_sdhc_pdata __initconst = { |
3b161e51 JM |
282 | .init = visstrim_m10_sdhc1_init, |
283 | .exit = visstrim_m10_sdhc1_exit, | |
284 | }; | |
285 | ||
286 | /* Visstrim_SM10 NOR flash */ | |
287 | static struct physmap_flash_data visstrim_m10_flash_data = { | |
288 | .width = 2, | |
289 | }; | |
290 | ||
291 | static struct resource visstrim_m10_flash_resource = { | |
292 | .start = 0xc0000000, | |
293 | .end = 0xc0000000 + SZ_64M - 1, | |
294 | .flags = IORESOURCE_MEM, | |
295 | }; | |
296 | ||
297 | static struct platform_device visstrim_m10_nor_mtd_device = { | |
298 | .name = "physmap-flash", | |
299 | .id = 0, | |
300 | .dev = { | |
301 | .platform_data = &visstrim_m10_flash_data, | |
302 | }, | |
303 | .num_resources = 1, | |
304 | .resource = &visstrim_m10_flash_resource, | |
305 | }; | |
306 | ||
307 | static struct platform_device *platform_devices[] __initdata = { | |
3b161e51 | 308 | &visstrim_m10_nor_mtd_device, |
3b161e51 JM |
309 | }; |
310 | ||
311 | /* Visstrim_M10 uses UART0 as console */ | |
312 | static const struct imxuart_platform_data uart_pdata __initconst = { | |
313 | .flags = IMXUART_HAVE_RTSCTS, | |
314 | }; | |
315 | ||
316 | /* I2C */ | |
317 | static const struct imxi2c_platform_data visstrim_m10_i2c_data __initconst = { | |
318 | .bitrate = 100000, | |
319 | }; | |
320 | ||
321 | static struct pca953x_platform_data visstrim_m10_pca9555_pdata = { | |
322 | .gpio_base = 240, /* After MX27 internal GPIOs */ | |
323 | .invert = 0, | |
324 | }; | |
325 | ||
c86566bb JM |
326 | static struct aic32x4_pdata visstrim_m10_aic32x4_pdata = { |
327 | .power_cfg = AIC32X4_PWR_MICBIAS_2075_LDOIN | | |
328 | AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE | | |
329 | AIC32X4_PWR_AIC32X4_LDO_ENABLE | | |
330 | AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36 | | |
331 | AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED, | |
332 | .micpga_routing = AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K | | |
333 | AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K, | |
334 | .swapdacs = false, | |
335 | }; | |
336 | ||
3b161e51 JM |
337 | static struct i2c_board_info visstrim_m10_i2c_devices[] = { |
338 | { | |
339 | I2C_BOARD_INFO("pca9555", 0x20), | |
340 | .platform_data = &visstrim_m10_pca9555_pdata, | |
341 | }, | |
a5e2051b JM |
342 | { |
343 | I2C_BOARD_INFO("tlv320aic32x4", 0x18), | |
c86566bb | 344 | .platform_data = &visstrim_m10_aic32x4_pdata, |
257b49c3 JM |
345 | }, |
346 | { | |
347 | I2C_BOARD_INFO("m41t00", 0x68), | |
a5e2051b | 348 | } |
3b161e51 JM |
349 | }; |
350 | ||
351 | /* USB OTG */ | |
352 | static int otg_phy_init(struct platform_device *pdev) | |
353 | { | |
354 | gpio_set_value(OTG_PHY_CS_GPIO, 0); | |
4bd597b6 SH |
355 | |
356 | mdelay(10); | |
357 | ||
358 | return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); | |
3b161e51 JM |
359 | } |
360 | ||
2eb42d5c UKK |
361 | static const struct mxc_usbh_platform_data |
362 | visstrim_m10_usbotg_pdata __initconst = { | |
3b161e51 JM |
363 | .init = otg_phy_init, |
364 | .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, | |
3b161e51 JM |
365 | }; |
366 | ||
a5e2051b JM |
367 | /* SSI */ |
368 | static const struct imx_ssi_platform_data visstrim_m10_ssi_pdata __initconst = { | |
369 | .flags = IMX_SSI_DMA | IMX_SSI_SYN, | |
370 | }; | |
371 | ||
3b161e51 JM |
372 | static void __init visstrim_m10_board_init(void) |
373 | { | |
374 | int ret; | |
375 | ||
b78d8e59 SG |
376 | imx27_soc_init(); |
377 | ||
3b161e51 JM |
378 | ret = mxc_gpio_setup_multiple_pins(visstrim_m10_pins, |
379 | ARRAY_SIZE(visstrim_m10_pins), "VISSTRIM_M10"); | |
380 | if (ret) | |
381 | pr_err("Failed to setup pins (%d)\n", ret); | |
382 | ||
a5e2051b | 383 | imx27_add_imx_ssi(0, &visstrim_m10_ssi_pdata); |
3b161e51 JM |
384 | imx27_add_imx_uart0(&uart_pdata); |
385 | ||
77a406da UKK |
386 | imx27_add_imx_i2c(0, &visstrim_m10_i2c_data); |
387 | imx27_add_imx_i2c(1, &visstrim_m10_i2c_data); | |
baa1dee1 JM |
388 | i2c_register_board_info(0, visstrim_m10_i2c_devices, |
389 | ARRAY_SIZE(visstrim_m10_i2c_devices)); | |
390 | ||
9d3d945a | 391 | imx27_add_mxc_mmc(0, &visstrim_m10_sdhc_pdata); |
2eb42d5c | 392 | imx27_add_mxc_ehci_otg(&visstrim_m10_usbotg_pdata); |
6bd96f3c | 393 | imx27_add_fec(NULL); |
5309498a | 394 | imx_add_gpio_keys(&visstrim_gpio_keys_platform_data); |
3b161e51 | 395 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); |
5ec65ee5 | 396 | imx_add_platform_device("mx27vis", 0, NULL, 0, NULL, 0); |
f52f5a55 JM |
397 | platform_device_register_resndata(NULL, "soc-camera-pdrv", 0, NULL, 0, |
398 | &iclink_tvp5150, sizeof(iclink_tvp5150)); | |
acb6464c | 399 | gpio_led_register_device(0, &visstrim_m10_led_data); |
f52f5a55 | 400 | visstrim_camera_init(); |
3b161e51 JM |
401 | } |
402 | ||
403 | static void __init visstrim_m10_timer_init(void) | |
404 | { | |
405 | mx27_clocks_init((unsigned long)25000000); | |
406 | } | |
407 | ||
408 | static struct sys_timer visstrim_m10_timer = { | |
409 | .init = visstrim_m10_timer_init, | |
410 | }; | |
411 | ||
412 | MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10") | |
dc8f1907 | 413 | .atag_offset = 0x100, |
f52f5a55 | 414 | .reserve = visstrim_reserve, |
3dac2196 UKK |
415 | .map_io = mx27_map_io, |
416 | .init_early = imx27_init_early, | |
417 | .init_irq = mx27_init_irq, | |
ffa2ea3f | 418 | .handle_irq = imx27_handle_irq, |
3dac2196 UKK |
419 | .timer = &visstrim_m10_timer, |
420 | .init_machine = visstrim_m10_board_init, | |
65ea7884 | 421 | .restart = mxc_restart, |
3b161e51 | 422 | MACHINE_END |