[deliverable/linux.git] / arch / arm / mach-imx / mach-imx6q.c

/*
 * Copyright 2011 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/cpu.h>
#include <linux/delay.h>
#include <linux/export.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/opp.h>
#include <linux/phy.h>
#include <linux/regmap.h>
#include <linux/micrel_phy.h>
#include <linux/mfd/syscon.h>
#include <asm/smp_twd.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/system_misc.h>

#include "common.h"
#include "cpuidle.h"
#include "hardware.h"

#define IMX6Q_ANALOG_DIGPROG	0x260

static int imx6q_revision(void)
{
	struct device_node *np;
	void __iomem *base;
	static u32 rev;

	if (!rev) {
		np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
		if (!np)
			return IMX_CHIP_REVISION_UNKNOWN;
		base = of_iomap(np, 0);
		if (!base) {
			of_node_put(np);
			return IMX_CHIP_REVISION_UNKNOWN;
		}
		rev =  readl_relaxed(base + IMX6Q_ANALOG_DIGPROG);
		iounmap(base);
		of_node_put(np);
	}

	switch (rev & 0xff) {
	case 0:
		return IMX_CHIP_REVISION_1_0;
	case 1:
		return IMX_CHIP_REVISION_1_1;
	case 2:
		return IMX_CHIP_REVISION_1_2;
	default:
		return IMX_CHIP_REVISION_UNKNOWN;
	}
}

void imx6q_restart(char mode, const char *cmd)
{
	struct device_node *np;
	void __iomem *wdog_base;

	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt");
	wdog_base = of_iomap(np, 0);
	if (!wdog_base)
		goto soft;

	imx_src_prepare_restart();

	/* enable wdog */
	writew_relaxed(1 << 2, wdog_base);
	/* write twice to ensure the request will not get ignored */
	writew_relaxed(1 << 2, wdog_base);

	/* wait for reset to assert ... */
	mdelay(500);

	pr_err("Watchdog reset failed to assert reset\n");

	/* delay to allow the serial port to show the message */
	mdelay(50);

soft:
	/* we'll take a jump through zero as a poor second */
	soft_restart(0);
}

/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
static int ksz9021rn_phy_fixup(struct phy_device *phydev)
{
	if (IS_BUILTIN(CONFIG_PHYLIB)) {
		/* min rx data delay */
		phy_write(phydev, 0x0b, 0x8105);
		phy_write(phydev, 0x0c, 0x0000);

		/* max rx/tx clock delay, min rx/tx control delay */
		phy_write(phydev, 0x0b, 0x8104);
		phy_write(phydev, 0x0c, 0xf0f0);
		phy_write(phydev, 0x0b, 0x104);
	}

	return 0;
}

static void __init imx6q_sabrelite_cko1_setup(void)
{
	struct clk *cko1_sel, *ahb, *cko1;
	unsigned long rate;

	cko1_sel = clk_get_sys(NULL, "cko1_sel");
	ahb = clk_get_sys(NULL, "ahb");
	cko1 = clk_get_sys(NULL, "cko1");
	if (IS_ERR(cko1_sel) || IS_ERR(ahb) || IS_ERR(cko1)) {
		pr_err("cko1 setup failed!\n");
		goto put_clk;
	}
	clk_set_parent(cko1_sel, ahb);
	rate = clk_round_rate(cko1, 16000000);
	clk_set_rate(cko1, rate);
put_clk:
	if (!IS_ERR(cko1_sel))
		clk_put(cko1_sel);
	if (!IS_ERR(ahb))
		clk_put(ahb);
	if (!IS_ERR(cko1))
		clk_put(cko1);
}

static void __init imx6q_sabrelite_init(void)
{
	if (IS_BUILTIN(CONFIG_PHYLIB))
		phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
				ksz9021rn_phy_fixup);
	imx6q_sabrelite_cko1_setup();
}

static void __init imx6q_1588_init(void)
{
	struct regmap *gpr;

	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	if (!IS_ERR(gpr))
		regmap_update_bits(gpr, 0x4, 1 << 21, 1 << 21);
	else
		pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");

}
static void __init imx6q_usb_init(void)
{
	struct regmap *anatop;

#define HW_ANADIG_USB1_CHRG_DETECT		0x000001b0
#define HW_ANADIG_USB2_CHRG_DETECT		0x00000210

#define BM_ANADIG_USB_CHRG_DETECT_EN_B		0x00100000
#define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B	0x00080000

	anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop");
	if (!IS_ERR(anatop)) {
		/*
		 * The external charger detector needs to be disabled,
		 * or the signal at DP will be poor
		 */
		regmap_write(anatop, HW_ANADIG_USB1_CHRG_DETECT,
				BM_ANADIG_USB_CHRG_DETECT_EN_B
				| BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
		regmap_write(anatop, HW_ANADIG_USB2_CHRG_DETECT,
				BM_ANADIG_USB_CHRG_DETECT_EN_B |
				BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
	} else {
		pr_warn("failed to find fsl,imx6q-anatop regmap\n");
	}
}

static void __init imx6q_init_machine(void)
{
	if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
		imx6q_sabrelite_init();

	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);

	imx6q_pm_init();
	imx6q_usb_init();
	imx6q_1588_init();
}

#define OCOTP_CFG3			0x440
#define OCOTP_CFG3_SPEED_SHIFT		16
#define OCOTP_CFG3_SPEED_1P2GHZ		0x3

static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
{
	struct device_node *np;
	void __iomem *base;
	u32 val;

	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
	if (!np) {
		pr_warn("failed to find ocotp node\n");
		return;
	}

	base = of_iomap(np, 0);
	if (!base) {
		pr_warn("failed to map ocotp\n");
		goto put_node;
	}

	val = readl_relaxed(base + OCOTP_CFG3);
	val >>= OCOTP_CFG3_SPEED_SHIFT;
	if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ)
		if (opp_disable(cpu_dev, 1200000000))
			pr_warn("failed to disable 1.2 GHz OPP\n");

put_node:
	of_node_put(np);
}

static void __init imx6q_opp_init(struct device *cpu_dev)
{
	struct device_node *np;

	np = of_find_node_by_path("/cpus/cpu@0");
	if (!np) {
		pr_warn("failed to find cpu0 node\n");
		return;
	}

	cpu_dev->of_node = np;
	if (of_init_opp_table(cpu_dev)) {
		pr_warn("failed to init OPP table\n");
		goto put_node;
	}

	imx6q_opp_check_1p2ghz(cpu_dev);

put_node:
	of_node_put(np);
}

struct platform_device imx6q_cpufreq_pdev = {
	.name = "imx6q-cpufreq",
};

static void __init imx6q_init_late(void)
{
	/*
	 * WAIT mode is broken on TO 1.0 and 1.1, so there is no point
	 * to run cpuidle on them.
	 */
	if (imx6q_revision() > IMX_CHIP_REVISION_1_1)
		imx6q_cpuidle_init();

	if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
		imx6q_opp_init(&imx6q_cpufreq_pdev.dev);
		platform_device_register(&imx6q_cpufreq_pdev);
	}
}

static void __init imx6q_map_io(void)
{
	debug_ll_io_init();
	imx_scu_map_io();
}

static void __init imx6q_init_irq(void)
{
	l2x0_of_init(0, ~0UL);
	imx_src_init();
	imx_gpc_init();
	irqchip_init();
}

static void __init imx6q_timer_init(void)
{
	mx6q_clocks_init();
	twd_local_timer_of_register();
	imx_print_silicon_rev("i.MX6Q", imx6q_revision());
}

static const char *imx6q_dt_compat[] __initdata = {
	"fsl,imx6q",
	NULL,
};

DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad (Device Tree)")
	.smp		= smp_ops(imx_smp_ops),
	.map_io		= imx6q_map_io,
	.init_irq	= imx6q_init_irq,
	.init_time	= imx6q_timer_init,
	.init_machine	= imx6q_init_machine,
	.init_late      = imx6q_init_late,
	.dt_compat	= imx6q_dt_compat,
	.restart	= imx6q_restart,
MACHINE_END
Commit	Line	Data
13eed989 SG	1	/*
	2	* Copyright 2011 Freescale Semiconductor, Inc.
	3	* Copyright 2011 Linaro Ltd.
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
a258561d RZ	13	#include <linux/clk.h>
a258561d RZ	14	#include <linux/clkdev.h>
96574a6d	15	#include <linux/cpu.h>
0575fb75	16	#include <linux/delay.h>
b9d18dc3	17	#include <linux/export.h>
13eed989	18	#include <linux/init.h>
0575fb75	19	#include <linux/io.h>
13eed989	20	#include <linux/irq.h>
0529e315	21	#include <linux/irqchip.h>
13eed989	22	#include <linux/of.h>
0575fb75	23	#include <linux/of_address.h>
13eed989 SG	24	#include <linux/of_irq.h>
13eed989 SG	25	#include <linux/of_platform.h>
96574a6d	26	#include <linux/opp.h>
477fce49	27	#include <linux/phy.h>
baa64151	28	#include <linux/regmap.h>
477fce49	29	#include <linux/micrel_phy.h>
baa64151	30	#include <linux/mfd/syscon.h>
58458e03	31	#include <asm/smp_twd.h>
13eed989	32	#include <asm/hardware/cache-l2x0.h>
13eed989	33	#include <asm/mach/arch.h>
3e549a69	34	#include <asm/mach/map.h>
13eed989	35	#include <asm/mach/time.h>
9f97da78	36	#include <asm/system_misc.h>
13eed989	37
e3372474	38	#include "common.h"
e29248c9	39	#include "cpuidle.h"
50f2de61	40	#include "hardware.h"
b9d18dc3	41
b29b3e6f SG	42	#define IMX6Q_ANALOG_DIGPROG 0x260
	43
	44	static int imx6q_revision(void)
	45	{
	46	struct device_node *np;
	47	void __iomem *base;
	48	static u32 rev;
	49
	50	if (!rev) {
	51	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
	52	if (!np)
	53	return IMX_CHIP_REVISION_UNKNOWN;
	54	base = of_iomap(np, 0);
	55	if (!base) {
	56	of_node_put(np);
	57	return IMX_CHIP_REVISION_UNKNOWN;
	58	}
	59	rev = readl_relaxed(base + IMX6Q_ANALOG_DIGPROG);
	60	iounmap(base);
	61	of_node_put(np);
	62	}
	63
	64	switch (rev & 0xff) {
	65	case 0:
	66	return IMX_CHIP_REVISION_1_0;
	67	case 1:
	68	return IMX_CHIP_REVISION_1_1;
	69	case 2:
	70	return IMX_CHIP_REVISION_1_2;
	71	default:
	72	return IMX_CHIP_REVISION_UNKNOWN;
	73	}
	74	}
	75
0575fb75 SG	76	void imx6q_restart(char mode, const char *cmd)
	77	{
	78	struct device_node *np;
	79	void __iomem *wdog_base;
	80
	81	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt");
	82	wdog_base = of_iomap(np, 0);
	83	if (!wdog_base)
	84	goto soft;
	85
	86	imx_src_prepare_restart();
	87
	88	/* enable wdog */
	89	writew_relaxed(1 << 2, wdog_base);
	90	/* write twice to ensure the request will not get ignored */
	91	writew_relaxed(1 << 2, wdog_base);
	92
	93	/* wait for reset to assert ... */
	94	mdelay(500);
	95
	96	pr_err("Watchdog reset failed to assert reset\n");
	97
	98	/* delay to allow the serial port to show the message */
	99	mdelay(50);
	100
	101	soft:
	102	/* we'll take a jump through zero as a poor second */
	103	soft_restart(0);
	104	}
	105
477fce49 RZ	106	/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
	107	static int ksz9021rn_phy_fixup(struct phy_device *phydev)
	108	{
9f9ba0fd	109	if (IS_BUILTIN(CONFIG_PHYLIB)) {
ef441806 SG	110	/* min rx data delay */
	111	phy_write(phydev, 0x0b, 0x8105);
	112	phy_write(phydev, 0x0c, 0x0000);
477fce49	113
ef441806 SG	114	/* max rx/tx clock delay, min rx/tx control delay */
	115	phy_write(phydev, 0x0b, 0x8104);
	116	phy_write(phydev, 0x0c, 0xf0f0);
	117	phy_write(phydev, 0x0b, 0x104);
	118	}
477fce49 RZ	119
	120	return 0;
	121	}
	122
a258561d RZ	123	static void __init imx6q_sabrelite_cko1_setup(void)
	124	{
	125	struct clk cko1_sel, ahb, *cko1;
	126	unsigned long rate;
	127
	128	cko1_sel = clk_get_sys(NULL, "cko1_sel");
	129	ahb = clk_get_sys(NULL, "ahb");
	130	cko1 = clk_get_sys(NULL, "cko1");
	131	if (IS_ERR(cko1_sel) \|\| IS_ERR(ahb) \|\| IS_ERR(cko1)) {
	132	pr_err("cko1 setup failed!\n");
	133	goto put_clk;
	134	}
	135	clk_set_parent(cko1_sel, ahb);
	136	rate = clk_round_rate(cko1, 16000000);
	137	clk_set_rate(cko1, rate);
a258561d RZ	138	put_clk:
	139	if (!IS_ERR(cko1_sel))
	140	clk_put(cko1_sel);
	141	if (!IS_ERR(ahb))
	142	clk_put(ahb);
	143	if (!IS_ERR(cko1))
	144	clk_put(cko1);
	145	}
	146
071dea50 RZ	147	static void __init imx6q_sabrelite_init(void)
071dea50 RZ	148	{
9f9ba0fd	149	if (IS_BUILTIN(CONFIG_PHYLIB))
ef441806	150	phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
071dea50	151	ksz9021rn_phy_fixup);
a258561d	152	imx6q_sabrelite_cko1_setup();
071dea50 RZ	153	}
071dea50 RZ	154
d6e0d9fc FL	155	static void __init imx6q_1588_init(void)
	156	{
	157	struct regmap *gpr;
	158
	159	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	160	if (!IS_ERR(gpr))
	161	regmap_update_bits(gpr, 0x4, 1 << 21, 1 << 21);
	162	else
	163	pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
	164
	165	}
396bf1c2 RZ	166	static void __init imx6q_usb_init(void)
396bf1c2 RZ	167	{
baa64151	168	struct regmap *anatop;
396bf1c2 RZ	169
	170	#define HW_ANADIG_USB1_CHRG_DETECT 0x000001b0
	171	#define HW_ANADIG_USB2_CHRG_DETECT 0x00000210
	172
	173	#define BM_ANADIG_USB_CHRG_DETECT_EN_B 0x00100000
	174	#define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B 0x00080000
	175
baa64151 DA	176	anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop");
	177	if (!IS_ERR(anatop)) {
	178	/*
	179	* The external charger detector needs to be disabled,
	180	* or the signal at DP will be poor
	181	*/
	182	regmap_write(anatop, HW_ANADIG_USB1_CHRG_DETECT,
	183	BM_ANADIG_USB_CHRG_DETECT_EN_B
	184	\| BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
	185	regmap_write(anatop, HW_ANADIG_USB2_CHRG_DETECT,
	186	BM_ANADIG_USB_CHRG_DETECT_EN_B \|
	187	BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
	188	} else {
	189	pr_warn("failed to find fsl,imx6q-anatop regmap\n");
	190	}
396bf1c2 RZ	191	}
396bf1c2 RZ	192
13eed989 SG	193	static void __init imx6q_init_machine(void)
13eed989 SG	194	{
477fce49	195	if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
071dea50	196	imx6q_sabrelite_init();
477fce49	197
13eed989 SG	198	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
	199
	200	imx6q_pm_init();
396bf1c2	201	imx6q_usb_init();
d6e0d9fc	202	imx6q_1588_init();
13eed989 SG	203	}
13eed989 SG	204
96574a6d SG	205	#define OCOTP_CFG3 0x440
	206	#define OCOTP_CFG3_SPEED_SHIFT 16
	207	#define OCOTP_CFG3_SPEED_1P2GHZ 0x3
	208
	209	static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
	210	{
	211	struct device_node *np;
	212	void __iomem *base;
	213	u32 val;
	214
	215	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
	216	if (!np) {
	217	pr_warn("failed to find ocotp node\n");
	218	return;
	219	}
	220
	221	base = of_iomap(np, 0);
	222	if (!base) {
	223	pr_warn("failed to map ocotp\n");
	224	goto put_node;
	225	}
	226
	227	val = readl_relaxed(base + OCOTP_CFG3);
	228	val >>= OCOTP_CFG3_SPEED_SHIFT;
	229	if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ)
	230	if (opp_disable(cpu_dev, 1200000000))
	231	pr_warn("failed to disable 1.2 GHz OPP\n");
	232
	233	put_node:
	234	of_node_put(np);
	235	}
	236
	237	static void __init imx6q_opp_init(struct device *cpu_dev)
	238	{
	239	struct device_node *np;
	240
	241	np = of_find_node_by_path("/cpus/cpu@0");
	242	if (!np) {
	243	pr_warn("failed to find cpu0 node\n");
	244	return;
	245	}
	246
	247	cpu_dev->of_node = np;
	248	if (of_init_opp_table(cpu_dev)) {
	249	pr_warn("failed to init OPP table\n");
	250	goto put_node;
	251	}
	252
	253	imx6q_opp_check_1p2ghz(cpu_dev);
	254
	255	put_node:
	256	of_node_put(np);
	257	}
	258
	259	struct platform_device imx6q_cpufreq_pdev = {
	260	.name = "imx6q-cpufreq",
	261	};
	262
b9d18dc3 RL	263	static void __init imx6q_init_late(void)
b9d18dc3 RL	264	{
e5f9dec8 SG	265	/*
	266	* WAIT mode is broken on TO 1.0 and 1.1, so there is no point
	267	* to run cpuidle on them.
	268	*/
	269	if (imx6q_revision() > IMX_CHIP_REVISION_1_1)
	270	imx6q_cpuidle_init();
96574a6d SG	271
	272	if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
	273	imx6q_opp_init(&imx6q_cpufreq_pdev.dev);
	274	platform_device_register(&imx6q_cpufreq_pdev);
	275	}
b9d18dc3 RL	276	}
b9d18dc3 RL	277
13eed989 SG	278	static void __init imx6q_map_io(void)
13eed989 SG	279	{
3e549a69	280	debug_ll_io_init();
13eed989 SG	281	imx_scu_map_io();
	282	}
	283
13eed989 SG	284	static void __init imx6q_init_irq(void)
	285	{
	286	l2x0_of_init(0, ~0UL);
	287	imx_src_init();
	288	imx_gpc_init();
0529e315	289	irqchip_init();
13eed989 SG	290	}
	291
	292	static void __init imx6q_timer_init(void)
	293	{
	294	mx6q_clocks_init();
58458e03	295	twd_local_timer_of_register();
b29b3e6f	296	imx_print_silicon_rev("i.MX6Q", imx6q_revision());
13eed989 SG	297	}
13eed989 SG	298
13eed989	299	static const char *imx6q_dt_compat[] __initdata = {
3f8976d9	300	"fsl,imx6q",
13eed989 SG	301	NULL,
	302	};
	303
	304	DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad (Device Tree)")
e4f2d979	305	.smp = smp_ops(imx_smp_ops),
13eed989 SG	306	.map_io = imx6q_map_io,
13eed989 SG	307	.init_irq = imx6q_init_irq,
6bb27d73	308	.init_time = imx6q_timer_init,
13eed989	309	.init_machine = imx6q_init_machine,
b9d18dc3	310	.init_late = imx6q_init_late,
13eed989	311	.dt_compat = imx6q_dt_compat,
0575fb75	312	.restart = imx6q_restart,
13eed989	313	MACHINE_END