[deliverable/linux.git] / arch / arm / mach-imx / mach-imx6q.c

/*
 * Copyright 2011-2013 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/clocksource.h>
#include <linux/cpu.h>
#include <linux/delay.h>
#include <linux/export.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/opp.h>
#include <linux/phy.h>
#include <linux/regmap.h>
#include <linux/micrel_phy.h>
#include <linux/mfd/syscon.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h>

#include "common.h"
#include "cpuidle.h"
#include "hardware.h"

static u32 chip_revision;

int imx6q_revision(void)
{
	return chip_revision;
}

static void __init imx6q_init_revision(void)
{
	u32 rev = imx_anatop_get_digprog();

	switch (rev & 0xff) {
	case 0:
		chip_revision = IMX_CHIP_REVISION_1_0;
		break;
	case 1:
		chip_revision = IMX_CHIP_REVISION_1_1;
		break;
	case 2:
		chip_revision = IMX_CHIP_REVISION_1_2;
		break;
	default:
		chip_revision = IMX_CHIP_REVISION_UNKNOWN;
	}

	mxc_set_cpu_type(rev >> 16 & 0xff);
}

static void imx6q_restart(char mode, const char *cmd)
{
	struct device_node *np;
	void __iomem *wdog_base;

	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt");
	wdog_base = of_iomap(np, 0);
	if (!wdog_base)
		goto soft;

	imx_src_prepare_restart();

	/* enable wdog */
	writew_relaxed(1 << 2, wdog_base);
	/* write twice to ensure the request will not get ignored */
	writew_relaxed(1 << 2, wdog_base);

	/* wait for reset to assert ... */
	mdelay(500);

	pr_err("Watchdog reset failed to assert reset\n");

	/* delay to allow the serial port to show the message */
	mdelay(50);

soft:
	/* we'll take a jump through zero as a poor second */
	soft_restart(0);
}

/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
static int ksz9021rn_phy_fixup(struct phy_device *phydev)
{
	if (IS_BUILTIN(CONFIG_PHYLIB)) {
		/* min rx data delay */
		phy_write(phydev, 0x0b, 0x8105);
		phy_write(phydev, 0x0c, 0x0000);

		/* max rx/tx clock delay, min rx/tx control delay */
		phy_write(phydev, 0x0b, 0x8104);
		phy_write(phydev, 0x0c, 0xf0f0);
		phy_write(phydev, 0x0b, 0x104);
	}

	return 0;
}

static void __init imx6q_sabrelite_cko1_setup(void)
{
	struct clk *cko1_sel, *ahb, *cko1;
	unsigned long rate;

	cko1_sel = clk_get_sys(NULL, "cko1_sel");
	ahb = clk_get_sys(NULL, "ahb");
	cko1 = clk_get_sys(NULL, "cko1");
	if (IS_ERR(cko1_sel) || IS_ERR(ahb) || IS_ERR(cko1)) {
		pr_err("cko1 setup failed!\n");
		goto put_clk;
	}
	clk_set_parent(cko1_sel, ahb);
	rate = clk_round_rate(cko1, 16000000);
	clk_set_rate(cko1, rate);
put_clk:
	if (!IS_ERR(cko1_sel))
		clk_put(cko1_sel);
	if (!IS_ERR(ahb))
		clk_put(ahb);
	if (!IS_ERR(cko1))
		clk_put(cko1);
}

static void __init imx6q_sabrelite_init(void)
{
	if (IS_BUILTIN(CONFIG_PHYLIB))
		phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
				ksz9021rn_phy_fixup);
	imx6q_sabrelite_cko1_setup();
}

static void __init imx6q_sabresd_cko1_setup(void)
{
	struct clk *cko1_sel, *pll4, *pll4_post, *cko1;
	unsigned long rate;

	cko1_sel = clk_get_sys(NULL, "cko1_sel");
	pll4 = clk_get_sys(NULL, "pll4_audio");
	pll4_post = clk_get_sys(NULL, "pll4_post_div");
	cko1 = clk_get_sys(NULL, "cko1");
	if (IS_ERR(cko1_sel) || IS_ERR(pll4)
			|| IS_ERR(pll4_post) || IS_ERR(cko1)) {
		pr_err("cko1 setup failed!\n");
		goto put_clk;
	}
	/*
	 * Setting pll4 at 768MHz (24MHz * 32)
	 * So its child clock can get 24MHz easily
	 */
	clk_set_rate(pll4, 768000000);

	clk_set_parent(cko1_sel, pll4_post);
	rate = clk_round_rate(cko1, 24000000);
	clk_set_rate(cko1, rate);
put_clk:
	if (!IS_ERR(cko1_sel))
		clk_put(cko1_sel);
	if (!IS_ERR(pll4_post))
		clk_put(pll4_post);
	if (!IS_ERR(pll4))
		clk_put(pll4);
	if (!IS_ERR(cko1))
		clk_put(cko1);
}

static void __init imx6q_sabresd_init(void)
{
	imx6q_sabresd_cko1_setup();
}

static void __init imx6q_1588_init(void)
{
	struct regmap *gpr;

	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	if (!IS_ERR(gpr))
		regmap_update_bits(gpr, 0x4, 1 << 21, 1 << 21);
	else
		pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");

}
static void __init imx6q_usb_init(void)
{
	imx_anatop_usb_chrg_detect_disable();
}

static void __init imx6q_init_machine(void)
{
	if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
		imx6q_sabrelite_init();
	else if (of_machine_is_compatible("fsl,imx6q-sabresd") ||
			of_machine_is_compatible("fsl,imx6dl-sabresd"))
		imx6q_sabresd_init();

	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);

	imx_anatop_init();
	imx6q_pm_init();
	imx6q_usb_init();
	imx6q_1588_init();
}

#define OCOTP_CFG3			0x440
#define OCOTP_CFG3_SPEED_SHIFT		16
#define OCOTP_CFG3_SPEED_1P2GHZ		0x3

static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
{
	struct device_node *np;
	void __iomem *base;
	u32 val;

	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
	if (!np) {
		pr_warn("failed to find ocotp node\n");
		return;
	}

	base = of_iomap(np, 0);
	if (!base) {
		pr_warn("failed to map ocotp\n");
		goto put_node;
	}

	val = readl_relaxed(base + OCOTP_CFG3);
	val >>= OCOTP_CFG3_SPEED_SHIFT;
	if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ)
		if (opp_disable(cpu_dev, 1200000000))
			pr_warn("failed to disable 1.2 GHz OPP\n");

put_node:
	of_node_put(np);
}

static void __init imx6q_opp_init(struct device *cpu_dev)
{
	struct device_node *np;

	np = of_find_node_by_path("/cpus/cpu@0");
	if (!np) {
		pr_warn("failed to find cpu0 node\n");
		return;
	}

	cpu_dev->of_node = np;
	if (of_init_opp_table(cpu_dev)) {
		pr_warn("failed to init OPP table\n");
		goto put_node;
	}

	imx6q_opp_check_1p2ghz(cpu_dev);

put_node:
	of_node_put(np);
}

static struct platform_device imx6q_cpufreq_pdev = {
	.name = "imx6q-cpufreq",
};

static void __init imx6q_init_late(void)
{
	/*
	 * WAIT mode is broken on TO 1.0 and 1.1, so there is no point
	 * to run cpuidle on them.
	 */
	if (imx6q_revision() > IMX_CHIP_REVISION_1_1)
		imx6q_cpuidle_init();

	if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
		imx6q_opp_init(&imx6q_cpufreq_pdev.dev);
		platform_device_register(&imx6q_cpufreq_pdev);
	}
}

static void __init imx6q_map_io(void)
{
	debug_ll_io_init();
	imx_scu_map_io();
}

#ifdef CONFIG_CACHE_L2X0
static void __init imx6q_init_l2cache(void)
{
	void __iomem *l2x0_base;
	struct device_node *np;
	unsigned int val;

	np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
	if (!np)
		goto out;

	l2x0_base = of_iomap(np, 0);
	if (!l2x0_base) {
		of_node_put(np);
		goto out;
	}

	/* Configure the L2 PREFETCH and POWER registers */
	val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
	val |= 0x70800000;
	writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL);
	val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;
	writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL);

	iounmap(l2x0_base);
	of_node_put(np);

out:
	l2x0_of_init(0, ~0UL);
}
#else
static inline void imx6q_init_l2cache(void) {}
#endif

static void __init imx6q_init_irq(void)
{
	imx6q_init_revision();
	imx6q_init_l2cache();
	imx_src_init();
	imx_gpc_init();
	irqchip_init();
}

static void __init imx6q_timer_init(void)
{
	of_clk_init(NULL);
	clocksource_of_init();
	imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
			      imx6q_revision());
}

static const char *imx6q_dt_compat[] __initdata = {
	"fsl,imx6dl",
	"fsl,imx6q",
	NULL,
};

DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
	.smp		= smp_ops(imx_smp_ops),
	.map_io		= imx6q_map_io,
	.init_irq	= imx6q_init_irq,
	.init_time	= imx6q_timer_init,
	.init_machine	= imx6q_init_machine,
	.init_late      = imx6q_init_late,
	.dt_compat	= imx6q_dt_compat,
	.restart	= imx6q_restart,
MACHINE_END
Commit	Line	Data
13eed989	1	/*
e95dddb3	2	* Copyright 2011-2013 Freescale Semiconductor, Inc.
13eed989 SG	3	* Copyright 2011 Linaro Ltd.
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
a258561d	13	#include <linux/clk.h>
53bb71da	14	#include <linux/clk-provider.h>
a258561d	15	#include <linux/clkdev.h>
da4a686a	16	#include <linux/clocksource.h>
96574a6d	17	#include <linux/cpu.h>
0575fb75	18	#include <linux/delay.h>
b9d18dc3	19	#include <linux/export.h>
13eed989	20	#include <linux/init.h>
0575fb75	21	#include <linux/io.h>
13eed989	22	#include <linux/irq.h>
0529e315	23	#include <linux/irqchip.h>
13eed989	24	#include <linux/of.h>
0575fb75	25	#include <linux/of_address.h>
13eed989 SG	26	#include <linux/of_irq.h>
13eed989 SG	27	#include <linux/of_platform.h>
96574a6d	28	#include <linux/opp.h>
477fce49	29	#include <linux/phy.h>
baa64151	30	#include <linux/regmap.h>
477fce49	31	#include <linux/micrel_phy.h>
baa64151	32	#include <linux/mfd/syscon.h>
13eed989	33	#include <asm/hardware/cache-l2x0.h>
13eed989	34	#include <asm/mach/arch.h>
3e549a69	35	#include <asm/mach/map.h>
9f97da78	36	#include <asm/system_misc.h>
13eed989	37
e3372474	38	#include "common.h"
e29248c9	39	#include "cpuidle.h"
50f2de61	40	#include "hardware.h"
b9d18dc3	41
3c03a2fe	42	static u32 chip_revision;
b29b3e6f	43
b1a3582d	44	int imx6q_revision(void)
b29b3e6f	45	{
3c03a2fe SG	46	return chip_revision;
3c03a2fe SG	47	}
b29b3e6f	48
3c03a2fe SG	49	static void __init imx6q_init_revision(void)
	50	{
	51	u32 rev = imx_anatop_get_digprog();
b29b3e6f SG	52
	53	switch (rev & 0xff) {
	54	case 0:
3c03a2fe SG	55	chip_revision = IMX_CHIP_REVISION_1_0;
3c03a2fe SG	56	break;
b29b3e6f	57	case 1:
3c03a2fe SG	58	chip_revision = IMX_CHIP_REVISION_1_1;
3c03a2fe SG	59	break;
b29b3e6f	60	case 2:
3c03a2fe SG	61	chip_revision = IMX_CHIP_REVISION_1_2;
3c03a2fe SG	62	break;
b29b3e6f	63	default:
3c03a2fe	64	chip_revision = IMX_CHIP_REVISION_UNKNOWN;
b29b3e6f	65	}
3c03a2fe SG	66
3c03a2fe SG	67	mxc_set_cpu_type(rev >> 16 & 0xff);
b29b3e6f SG	68	}
b29b3e6f SG	69
f8c11b2b	70	static void imx6q_restart(char mode, const char *cmd)
0575fb75 SG	71	{
	72	struct device_node *np;
	73	void __iomem *wdog_base;
	74
	75	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt");
	76	wdog_base = of_iomap(np, 0);
	77	if (!wdog_base)
	78	goto soft;
	79
	80	imx_src_prepare_restart();
	81
	82	/* enable wdog */
	83	writew_relaxed(1 << 2, wdog_base);
	84	/* write twice to ensure the request will not get ignored */
	85	writew_relaxed(1 << 2, wdog_base);
	86
	87	/* wait for reset to assert ... */
	88	mdelay(500);
	89
	90	pr_err("Watchdog reset failed to assert reset\n");
	91
	92	/* delay to allow the serial port to show the message */
	93	mdelay(50);
	94
	95	soft:
	96	/* we'll take a jump through zero as a poor second */
	97	soft_restart(0);
	98	}
	99
477fce49 RZ	100	/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
	101	static int ksz9021rn_phy_fixup(struct phy_device *phydev)
	102	{
9f9ba0fd	103	if (IS_BUILTIN(CONFIG_PHYLIB)) {
ef441806 SG	104	/* min rx data delay */
	105	phy_write(phydev, 0x0b, 0x8105);
	106	phy_write(phydev, 0x0c, 0x0000);
477fce49	107
ef441806 SG	108	/* max rx/tx clock delay, min rx/tx control delay */
	109	phy_write(phydev, 0x0b, 0x8104);
	110	phy_write(phydev, 0x0c, 0xf0f0);
	111	phy_write(phydev, 0x0b, 0x104);
	112	}
477fce49 RZ	113
	114	return 0;
	115	}
	116
a258561d RZ	117	static void __init imx6q_sabrelite_cko1_setup(void)
	118	{
	119	struct clk cko1_sel, ahb, *cko1;
	120	unsigned long rate;
	121
	122	cko1_sel = clk_get_sys(NULL, "cko1_sel");
	123	ahb = clk_get_sys(NULL, "ahb");
	124	cko1 = clk_get_sys(NULL, "cko1");
	125	if (IS_ERR(cko1_sel) \|\| IS_ERR(ahb) \|\| IS_ERR(cko1)) {
	126	pr_err("cko1 setup failed!\n");
	127	goto put_clk;
	128	}
	129	clk_set_parent(cko1_sel, ahb);
	130	rate = clk_round_rate(cko1, 16000000);
	131	clk_set_rate(cko1, rate);
a258561d RZ	132	put_clk:
	133	if (!IS_ERR(cko1_sel))
	134	clk_put(cko1_sel);
	135	if (!IS_ERR(ahb))
	136	clk_put(ahb);
	137	if (!IS_ERR(cko1))
	138	clk_put(cko1);
	139	}
	140
071dea50 RZ	141	static void __init imx6q_sabrelite_init(void)
071dea50 RZ	142	{
9f9ba0fd	143	if (IS_BUILTIN(CONFIG_PHYLIB))
ef441806	144	phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
071dea50	145	ksz9021rn_phy_fixup);
a258561d	146	imx6q_sabrelite_cko1_setup();
071dea50 RZ	147	}
071dea50 RZ	148
e7eccc7e NC	149	static void __init imx6q_sabresd_cko1_setup(void)
	150	{
	151	struct clk cko1_sel, pll4, pll4_post, cko1;
	152	unsigned long rate;
	153
	154	cko1_sel = clk_get_sys(NULL, "cko1_sel");
	155	pll4 = clk_get_sys(NULL, "pll4_audio");
	156	pll4_post = clk_get_sys(NULL, "pll4_post_div");
	157	cko1 = clk_get_sys(NULL, "cko1");
	158	if (IS_ERR(cko1_sel) \|\| IS_ERR(pll4)
	159	\|\| IS_ERR(pll4_post) \|\| IS_ERR(cko1)) {
	160	pr_err("cko1 setup failed!\n");
	161	goto put_clk;
	162	}
	163	/*
	164	* Setting pll4 at 768MHz (24MHz * 32)
	165	* So its child clock can get 24MHz easily
	166	*/
	167	clk_set_rate(pll4, 768000000);
	168
	169	clk_set_parent(cko1_sel, pll4_post);
	170	rate = clk_round_rate(cko1, 24000000);
	171	clk_set_rate(cko1, rate);
	172	put_clk:
	173	if (!IS_ERR(cko1_sel))
	174	clk_put(cko1_sel);
	175	if (!IS_ERR(pll4_post))
	176	clk_put(pll4_post);
	177	if (!IS_ERR(pll4))
	178	clk_put(pll4);
	179	if (!IS_ERR(cko1))
	180	clk_put(cko1);
	181	}
	182
	183	static void __init imx6q_sabresd_init(void)
	184	{
	185	imx6q_sabresd_cko1_setup();
	186	}
	187
d6e0d9fc FL	188	static void __init imx6q_1588_init(void)
	189	{
	190	struct regmap *gpr;
	191
	192	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	193	if (!IS_ERR(gpr))
	194	regmap_update_bits(gpr, 0x4, 1 << 21, 1 << 21);
	195	else
	196	pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
	197
	198	}
396bf1c2 RZ	199	static void __init imx6q_usb_init(void)
396bf1c2 RZ	200	{
e95dddb3	201	imx_anatop_usb_chrg_detect_disable();
396bf1c2 RZ	202	}
396bf1c2 RZ	203
13eed989 SG	204	static void __init imx6q_init_machine(void)
13eed989 SG	205	{
477fce49	206	if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
071dea50	207	imx6q_sabrelite_init();
e7eccc7e NC	208	else if (of_machine_is_compatible("fsl,imx6q-sabresd") \|\|
	209	of_machine_is_compatible("fsl,imx6dl-sabresd"))
	210	imx6q_sabresd_init();
477fce49	211
13eed989 SG	212	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
13eed989 SG	213
e95dddb3	214	imx_anatop_init();
13eed989	215	imx6q_pm_init();
396bf1c2	216	imx6q_usb_init();
d6e0d9fc	217	imx6q_1588_init();
13eed989 SG	218	}
13eed989 SG	219
96574a6d SG	220	#define OCOTP_CFG3 0x440
	221	#define OCOTP_CFG3_SPEED_SHIFT 16
	222	#define OCOTP_CFG3_SPEED_1P2GHZ 0x3
	223
	224	static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
	225	{
	226	struct device_node *np;
	227	void __iomem *base;
	228	u32 val;
	229
	230	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
	231	if (!np) {
	232	pr_warn("failed to find ocotp node\n");
	233	return;
	234	}
	235
	236	base = of_iomap(np, 0);
	237	if (!base) {
	238	pr_warn("failed to map ocotp\n");
	239	goto put_node;
	240	}
	241
	242	val = readl_relaxed(base + OCOTP_CFG3);
	243	val >>= OCOTP_CFG3_SPEED_SHIFT;
	244	if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ)
	245	if (opp_disable(cpu_dev, 1200000000))
	246	pr_warn("failed to disable 1.2 GHz OPP\n");
	247
	248	put_node:
	249	of_node_put(np);
	250	}
	251
	252	static void __init imx6q_opp_init(struct device *cpu_dev)
	253	{
	254	struct device_node *np;
	255
	256	np = of_find_node_by_path("/cpus/cpu@0");
	257	if (!np) {
	258	pr_warn("failed to find cpu0 node\n");
	259	return;
	260	}
	261
	262	cpu_dev->of_node = np;
	263	if (of_init_opp_table(cpu_dev)) {
	264	pr_warn("failed to init OPP table\n");
	265	goto put_node;
	266	}
	267
	268	imx6q_opp_check_1p2ghz(cpu_dev);
	269
	270	put_node:
	271	of_node_put(np);
	272	}
	273
f8c11b2b	274	static struct platform_device imx6q_cpufreq_pdev = {
96574a6d SG	275	.name = "imx6q-cpufreq",
	276	};
	277
b9d18dc3 RL	278	static void __init imx6q_init_late(void)
b9d18dc3 RL	279	{
e5f9dec8 SG	280	/*
	281	* WAIT mode is broken on TO 1.0 and 1.1, so there is no point
	282	* to run cpuidle on them.
	283	*/
	284	if (imx6q_revision() > IMX_CHIP_REVISION_1_1)
	285	imx6q_cpuidle_init();
96574a6d SG	286
	287	if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
	288	imx6q_opp_init(&imx6q_cpufreq_pdev.dev);
	289	platform_device_register(&imx6q_cpufreq_pdev);
	290	}
b9d18dc3 RL	291	}
b9d18dc3 RL	292
13eed989 SG	293	static void __init imx6q_map_io(void)
13eed989 SG	294	{
3e549a69	295	debug_ll_io_init();
13eed989 SG	296	imx_scu_map_io();
	297	}
	298
b3a9c315 DB	299	#ifdef CONFIG_CACHE_L2X0
	300	static void __init imx6q_init_l2cache(void)
	301	{
	302	void __iomem *l2x0_base;
	303	struct device_node *np;
	304	unsigned int val;
	305
	306	np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
	307	if (!np)
	308	goto out;
	309
	310	l2x0_base = of_iomap(np, 0);
	311	if (!l2x0_base) {
	312	of_node_put(np);
	313	goto out;
	314	}
	315
	316	/* Configure the L2 PREFETCH and POWER registers */
	317	val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
	318	val \|= 0x70800000;
	319	writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL);
	320	val = L2X0_DYNAMIC_CLK_GATING_EN \| L2X0_STNDBY_MODE_EN;
	321	writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL);
	322
	323	iounmap(l2x0_base);
	324	of_node_put(np);
	325
	326	out:
	327	l2x0_of_init(0, ~0UL);
	328	}
	329	#else
	330	static inline void imx6q_init_l2cache(void) {}
	331	#endif
	332
13eed989 SG	333	static void __init imx6q_init_irq(void)
13eed989 SG	334	{
3c03a2fe	335	imx6q_init_revision();
b3a9c315	336	imx6q_init_l2cache();
13eed989 SG	337	imx_src_init();
13eed989 SG	338	imx_gpc_init();
0529e315	339	irqchip_init();
13eed989 SG	340	}
	341
	342	static void __init imx6q_timer_init(void)
	343	{
53bb71da	344	of_clk_init(NULL);
da4a686a	345	clocksource_of_init();
3c03a2fe SG	346	imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
3c03a2fe SG	347	imx6q_revision());
13eed989 SG	348	}
13eed989 SG	349
13eed989	350	static const char *imx6q_dt_compat[] __initdata = {
3c03a2fe	351	"fsl,imx6dl",
3f8976d9	352	"fsl,imx6q",
13eed989 SG	353	NULL,
	354	};
	355
3c03a2fe	356	DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
e4f2d979	357	.smp = smp_ops(imx_smp_ops),
13eed989 SG	358	.map_io = imx6q_map_io,
13eed989 SG	359	.init_irq = imx6q_init_irq,
6bb27d73	360	.init_time = imx6q_timer_init,
13eed989	361	.init_machine = imx6q_init_machine,
b9d18dc3	362	.init_late = imx6q_init_late,
13eed989	363	.dt_compat = imx6q_dt_compat,
0575fb75	364	.restart = imx6q_restart,
13eed989	365	MACHINE_END