[deliverable/linux.git] / arch / arm / mach-imx / mach-imx6q.c

/*
 * Copyright 2011-2013 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/clocksource.h>
#include <linux/cpu.h>
#include <linux/delay.h>
#include <linux/export.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/opp.h>
#include <linux/phy.h>
#include <linux/reboot.h>
#include <linux/regmap.h>
#include <linux/micrel_phy.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h>

#include "common.h"
#include "cpuidle.h"
#include "hardware.h"

static u32 chip_revision;

int imx6q_revision(void)
{
	return chip_revision;
}

static void __init imx6q_init_revision(void)
{
	u32 rev = imx_anatop_get_digprog();

	switch (rev & 0xff) {
	case 0:
		chip_revision = IMX_CHIP_REVISION_1_0;
		break;
	case 1:
		chip_revision = IMX_CHIP_REVISION_1_1;
		break;
	case 2:
		chip_revision = IMX_CHIP_REVISION_1_2;
		break;
	default:
		chip_revision = IMX_CHIP_REVISION_UNKNOWN;
	}

	mxc_set_cpu_type(rev >> 16 & 0xff);
}

static void imx6q_restart(enum reboot_mode mode, const char *cmd)
{
	struct device_node *np;
	void __iomem *wdog_base;

	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt");
	wdog_base = of_iomap(np, 0);
	if (!wdog_base)
		goto soft;

	imx_src_prepare_restart();

	/* enable wdog */
	writew_relaxed(1 << 2, wdog_base);
	/* write twice to ensure the request will not get ignored */
	writew_relaxed(1 << 2, wdog_base);

	/* wait for reset to assert ... */
	mdelay(500);

	pr_err("Watchdog reset failed to assert reset\n");

	/* delay to allow the serial port to show the message */
	mdelay(50);

soft:
	/* we'll take a jump through zero as a poor second */
	soft_restart(0);
}

/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
static int ksz9021rn_phy_fixup(struct phy_device *phydev)
{
	if (IS_BUILTIN(CONFIG_PHYLIB)) {
		/* min rx data delay */
		phy_write(phydev, 0x0b, 0x8105);
		phy_write(phydev, 0x0c, 0x0000);

		/* max rx/tx clock delay, min rx/tx control delay */
		phy_write(phydev, 0x0b, 0x8104);
		phy_write(phydev, 0x0c, 0xf0f0);
		phy_write(phydev, 0x0b, 0x104);
	}

	return 0;
}

static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
{
	phy_write(dev, 0x0d, device);
	phy_write(dev, 0x0e, reg);
	phy_write(dev, 0x0d, (1 << 14) | device);
	phy_write(dev, 0x0e, val);
}

static int ksz9031rn_phy_fixup(struct phy_device *dev)
{
	/*
	 * min rx data delay, max rx/tx clock delay,
	 * min rx/tx control delay
	 */
	mmd_write_reg(dev, 2, 4, 0);
	mmd_write_reg(dev, 2, 5, 0);
	mmd_write_reg(dev, 2, 8, 0x003ff);

	return 0;
}

static int ar8031_phy_fixup(struct phy_device *dev)
{
	u16 val;

	/* To enable AR8031 output a 125MHz clk from CLK_25M */
	phy_write(dev, 0xd, 0x7);
	phy_write(dev, 0xe, 0x8016);
	phy_write(dev, 0xd, 0x4007);

	val = phy_read(dev, 0xe);
	val &= 0xffe3;
	val |= 0x18;
	phy_write(dev, 0xe, val);

	/* introduce tx clock delay */
	phy_write(dev, 0x1d, 0x5);
	val = phy_read(dev, 0x1e);
	val |= 0x0100;
	phy_write(dev, 0x1e, val);

	return 0;
}

static void __init imx6q_sabrelite_cko1_setup(void)
{
	struct clk *cko1_sel, *ahb, *cko1;
	unsigned long rate;

	cko1_sel = clk_get_sys(NULL, "cko1_sel");
	ahb = clk_get_sys(NULL, "ahb");
	cko1 = clk_get_sys(NULL, "cko1");
	if (IS_ERR(cko1_sel) || IS_ERR(ahb) || IS_ERR(cko1)) {
		pr_err("cko1 setup failed!\n");
		goto put_clk;
	}
	clk_set_parent(cko1_sel, ahb);
	rate = clk_round_rate(cko1, 16000000);
	clk_set_rate(cko1, rate);
put_clk:
	if (!IS_ERR(cko1_sel))
		clk_put(cko1_sel);
	if (!IS_ERR(ahb))
		clk_put(ahb);
	if (!IS_ERR(cko1))
		clk_put(cko1);
}

#define PHY_ID_AR8031	0x004dd074

static void __init imx6q_enet_phy_init(void)
{
	if (IS_BUILTIN(CONFIG_PHYLIB)) {
		phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
				ksz9021rn_phy_fixup);
		phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
				ksz9031rn_phy_fixup);
		phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
				ar8031_phy_fixup);
	}
}

static void __init imx6q_sabresd_cko1_setup(void)
{
	struct clk *cko1_sel, *pll4, *pll4_post, *cko1;
	unsigned long rate;

	cko1_sel = clk_get_sys(NULL, "cko1_sel");
	pll4 = clk_get_sys(NULL, "pll4_audio");
	pll4_post = clk_get_sys(NULL, "pll4_post_div");
	cko1 = clk_get_sys(NULL, "cko1");
	if (IS_ERR(cko1_sel) || IS_ERR(pll4)
			|| IS_ERR(pll4_post) || IS_ERR(cko1)) {
		pr_err("cko1 setup failed!\n");
		goto put_clk;
	}
	/*
	 * Setting pll4 at 768MHz (24MHz * 32)
	 * So its child clock can get 24MHz easily
	 */
	clk_set_rate(pll4, 768000000);

	clk_set_parent(cko1_sel, pll4_post);
	rate = clk_round_rate(cko1, 24000000);
	clk_set_rate(cko1, rate);
put_clk:
	if (!IS_ERR(cko1_sel))
		clk_put(cko1_sel);
	if (!IS_ERR(pll4_post))
		clk_put(pll4_post);
	if (!IS_ERR(pll4))
		clk_put(pll4);
	if (!IS_ERR(cko1))
		clk_put(cko1);
}

static void __init imx6q_sabresd_init(void)
{
	imx6q_sabresd_cko1_setup();
}

static void __init imx6q_1588_init(void)
{
	struct regmap *gpr;

	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	if (!IS_ERR(gpr))
		regmap_update_bits(gpr, IOMUXC_GPR1,
				IMX6Q_GPR1_ENET_CLK_SEL_MASK,
				IMX6Q_GPR1_ENET_CLK_SEL_ANATOP);
	else
		pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");

}
static void __init imx6q_usb_init(void)
{
	imx_anatop_usb_chrg_detect_disable();
}

static void __init imx6q_init_machine(void)
{
	if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
		imx6q_sabrelite_cko1_setup();
	else if (of_machine_is_compatible("fsl,imx6q-sabresd") ||
			of_machine_is_compatible("fsl,imx6dl-sabresd"))
		imx6q_sabresd_init();

	imx6q_enet_phy_init();

	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);

	imx_anatop_init();
	imx6q_pm_init();
	imx6q_usb_init();
	imx6q_1588_init();
}

#define OCOTP_CFG3			0x440
#define OCOTP_CFG3_SPEED_SHIFT		16
#define OCOTP_CFG3_SPEED_1P2GHZ		0x3

static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
{
	struct device_node *np;
	void __iomem *base;
	u32 val;

	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
	if (!np) {
		pr_warn("failed to find ocotp node\n");
		return;
	}

	base = of_iomap(np, 0);
	if (!base) {
		pr_warn("failed to map ocotp\n");
		goto put_node;
	}

	val = readl_relaxed(base + OCOTP_CFG3);
	val >>= OCOTP_CFG3_SPEED_SHIFT;
	if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ)
		if (opp_disable(cpu_dev, 1200000000))
			pr_warn("failed to disable 1.2 GHz OPP\n");

put_node:
	of_node_put(np);
}

static void __init imx6q_opp_init(struct device *cpu_dev)
{
	struct device_node *np;

	np = of_find_node_by_path("/cpus/cpu@0");
	if (!np) {
		pr_warn("failed to find cpu0 node\n");
		return;
	}

	cpu_dev->of_node = np;
	if (of_init_opp_table(cpu_dev)) {
		pr_warn("failed to init OPP table\n");
		goto put_node;
	}

	imx6q_opp_check_1p2ghz(cpu_dev);

put_node:
	of_node_put(np);
}

static struct platform_device imx6q_cpufreq_pdev = {
	.name = "imx6q-cpufreq",
};

static void __init imx6q_init_late(void)
{
	/*
	 * WAIT mode is broken on TO 1.0 and 1.1, so there is no point
	 * to run cpuidle on them.
	 */
	if (imx6q_revision() > IMX_CHIP_REVISION_1_1)
		imx6q_cpuidle_init();

	if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
		imx6q_opp_init(&imx6q_cpufreq_pdev.dev);
		platform_device_register(&imx6q_cpufreq_pdev);
	}
}

static void __init imx6q_map_io(void)
{
	debug_ll_io_init();
	imx_scu_map_io();
}

#ifdef CONFIG_CACHE_L2X0
static void __init imx6q_init_l2cache(void)
{
	void __iomem *l2x0_base;
	struct device_node *np;
	unsigned int val;

	np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
	if (!np)
		goto out;

	l2x0_base = of_iomap(np, 0);
	if (!l2x0_base) {
		of_node_put(np);
		goto out;
	}

	/* Configure the L2 PREFETCH and POWER registers */
	val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
	val |= 0x70800000;
	writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL);
	val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;
	writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL);

	iounmap(l2x0_base);
	of_node_put(np);

out:
	l2x0_of_init(0, ~0UL);
}
#else
static inline void imx6q_init_l2cache(void) {}
#endif

static void __init imx6q_init_irq(void)
{
	imx6q_init_revision();
	imx6q_init_l2cache();
	imx_src_init();
	imx_gpc_init();
	irqchip_init();
}

static void __init imx6q_timer_init(void)
{
	of_clk_init(NULL);
	clocksource_of_init();
	imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
			      imx6q_revision());
}

static const char *imx6q_dt_compat[] __initdata = {
	"fsl,imx6dl",
	"fsl,imx6q",
	NULL,
};

DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
	.smp		= smp_ops(imx_smp_ops),
	.map_io		= imx6q_map_io,
	.init_irq	= imx6q_init_irq,
	.init_time	= imx6q_timer_init,
	.init_machine	= imx6q_init_machine,
	.init_late      = imx6q_init_late,
	.dt_compat	= imx6q_dt_compat,
	.restart	= imx6q_restart,
MACHINE_END
Commit	Line	Data
13eed989	1	/*
e95dddb3	2	* Copyright 2011-2013 Freescale Semiconductor, Inc.
13eed989 SG	3	* Copyright 2011 Linaro Ltd.
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
a258561d	13	#include <linux/clk.h>
53bb71da	14	#include <linux/clk-provider.h>
a258561d	15	#include <linux/clkdev.h>
da4a686a	16	#include <linux/clocksource.h>
96574a6d	17	#include <linux/cpu.h>
0575fb75	18	#include <linux/delay.h>
b9d18dc3	19	#include <linux/export.h>
13eed989	20	#include <linux/init.h>
0575fb75	21	#include <linux/io.h>
13eed989	22	#include <linux/irq.h>
0529e315	23	#include <linux/irqchip.h>
13eed989	24	#include <linux/of.h>
0575fb75	25	#include <linux/of_address.h>
13eed989 SG	26	#include <linux/of_irq.h>
13eed989 SG	27	#include <linux/of_platform.h>
96574a6d	28	#include <linux/opp.h>
477fce49	29	#include <linux/phy.h>
7b6d864b	30	#include <linux/reboot.h>
baa64151	31	#include <linux/regmap.h>
477fce49	32	#include <linux/micrel_phy.h>
baa64151	33	#include <linux/mfd/syscon.h>
6d6fc501	34	#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
13eed989	35	#include <asm/hardware/cache-l2x0.h>
13eed989	36	#include <asm/mach/arch.h>
3e549a69	37	#include <asm/mach/map.h>
9f97da78	38	#include <asm/system_misc.h>
13eed989	39
e3372474	40	#include "common.h"
e29248c9	41	#include "cpuidle.h"
50f2de61	42	#include "hardware.h"
b9d18dc3	43
3c03a2fe	44	static u32 chip_revision;
b29b3e6f	45
b1a3582d	46	int imx6q_revision(void)
b29b3e6f	47	{
3c03a2fe SG	48	return chip_revision;
3c03a2fe SG	49	}
b29b3e6f	50
3c03a2fe SG	51	static void __init imx6q_init_revision(void)
	52	{
	53	u32 rev = imx_anatop_get_digprog();
b29b3e6f SG	54
	55	switch (rev & 0xff) {
	56	case 0:
3c03a2fe SG	57	chip_revision = IMX_CHIP_REVISION_1_0;
3c03a2fe SG	58	break;
b29b3e6f	59	case 1:
3c03a2fe SG	60	chip_revision = IMX_CHIP_REVISION_1_1;
3c03a2fe SG	61	break;
b29b3e6f	62	case 2:
3c03a2fe SG	63	chip_revision = IMX_CHIP_REVISION_1_2;
3c03a2fe SG	64	break;
b29b3e6f	65	default:
3c03a2fe	66	chip_revision = IMX_CHIP_REVISION_UNKNOWN;
b29b3e6f	67	}
3c03a2fe SG	68
3c03a2fe SG	69	mxc_set_cpu_type(rev >> 16 & 0xff);
b29b3e6f SG	70	}
b29b3e6f SG	71
7b6d864b	72	static void imx6q_restart(enum reboot_mode mode, const char *cmd)
0575fb75 SG	73	{
	74	struct device_node *np;
	75	void __iomem *wdog_base;
	76
	77	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt");
	78	wdog_base = of_iomap(np, 0);
	79	if (!wdog_base)
	80	goto soft;
	81
	82	imx_src_prepare_restart();
	83
	84	/* enable wdog */
	85	writew_relaxed(1 << 2, wdog_base);
	86	/* write twice to ensure the request will not get ignored */
	87	writew_relaxed(1 << 2, wdog_base);
	88
	89	/* wait for reset to assert ... */
	90	mdelay(500);
	91
	92	pr_err("Watchdog reset failed to assert reset\n");
	93
	94	/* delay to allow the serial port to show the message */
	95	mdelay(50);
	96
	97	soft:
	98	/* we'll take a jump through zero as a poor second */
	99	soft_restart(0);
	100	}
	101
477fce49 RZ	102	/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
	103	static int ksz9021rn_phy_fixup(struct phy_device *phydev)
	104	{
9f9ba0fd	105	if (IS_BUILTIN(CONFIG_PHYLIB)) {
ef441806 SG	106	/* min rx data delay */
	107	phy_write(phydev, 0x0b, 0x8105);
	108	phy_write(phydev, 0x0c, 0x0000);
477fce49	109
ef441806 SG	110	/* max rx/tx clock delay, min rx/tx control delay */
	111	phy_write(phydev, 0x0b, 0x8104);
	112	phy_write(phydev, 0x0c, 0xf0f0);
	113	phy_write(phydev, 0x0b, 0x104);
	114	}
477fce49 RZ	115
	116	return 0;
	117	}
	118
dbf6719a SH	119	static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
	120	{
	121	phy_write(dev, 0x0d, device);
	122	phy_write(dev, 0x0e, reg);
	123	phy_write(dev, 0x0d, (1 << 14) \| device);
	124	phy_write(dev, 0x0e, val);
	125	}
	126
	127	static int ksz9031rn_phy_fixup(struct phy_device *dev)
	128	{
	129	/*
	130	* min rx data delay, max rx/tx clock delay,
	131	* min rx/tx control delay
	132	*/
	133	mmd_write_reg(dev, 2, 4, 0);
	134	mmd_write_reg(dev, 2, 5, 0);
	135	mmd_write_reg(dev, 2, 8, 0x003ff);
	136
	137	return 0;
	138	}
	139
12da4844 SH	140	static int ar8031_phy_fixup(struct phy_device *dev)
	141	{
	142	u16 val;
	143
	144	/* To enable AR8031 output a 125MHz clk from CLK_25M */
	145	phy_write(dev, 0xd, 0x7);
	146	phy_write(dev, 0xe, 0x8016);
	147	phy_write(dev, 0xd, 0x4007);
	148
	149	val = phy_read(dev, 0xe);
	150	val &= 0xffe3;
	151	val \|= 0x18;
	152	phy_write(dev, 0xe, val);
	153
	154	/* introduce tx clock delay */
	155	phy_write(dev, 0x1d, 0x5);
	156	val = phy_read(dev, 0x1e);
	157	val \|= 0x0100;
	158	phy_write(dev, 0x1e, val);
	159
	160	return 0;
	161	}
	162
a258561d RZ	163	static void __init imx6q_sabrelite_cko1_setup(void)
	164	{
	165	struct clk cko1_sel, ahb, *cko1;
	166	unsigned long rate;
	167
	168	cko1_sel = clk_get_sys(NULL, "cko1_sel");
	169	ahb = clk_get_sys(NULL, "ahb");
	170	cko1 = clk_get_sys(NULL, "cko1");
	171	if (IS_ERR(cko1_sel) \|\| IS_ERR(ahb) \|\| IS_ERR(cko1)) {
	172	pr_err("cko1 setup failed!\n");
	173	goto put_clk;
	174	}
	175	clk_set_parent(cko1_sel, ahb);
	176	rate = clk_round_rate(cko1, 16000000);
	177	clk_set_rate(cko1, rate);
a258561d RZ	178	put_clk:
	179	if (!IS_ERR(cko1_sel))
	180	clk_put(cko1_sel);
	181	if (!IS_ERR(ahb))
	182	clk_put(ahb);
	183	if (!IS_ERR(cko1))
	184	clk_put(cko1);
	185	}
	186
12da4844 SH	187	#define PHY_ID_AR8031 0x004dd074
12da4844 SH	188
14078291	189	static void __init imx6q_enet_phy_init(void)
071dea50	190	{
14078291	191	if (IS_BUILTIN(CONFIG_PHYLIB)) {
ef441806	192	phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
071dea50	193	ksz9021rn_phy_fixup);
dbf6719a SH	194	phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
dbf6719a SH	195	ksz9031rn_phy_fixup);
12da4844 SH	196	phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
12da4844 SH	197	ar8031_phy_fixup);
14078291	198	}
071dea50 RZ	199	}
071dea50 RZ	200
e7eccc7e NC	201	static void __init imx6q_sabresd_cko1_setup(void)
	202	{
	203	struct clk cko1_sel, pll4, pll4_post, cko1;
	204	unsigned long rate;
	205
	206	cko1_sel = clk_get_sys(NULL, "cko1_sel");
	207	pll4 = clk_get_sys(NULL, "pll4_audio");
	208	pll4_post = clk_get_sys(NULL, "pll4_post_div");
	209	cko1 = clk_get_sys(NULL, "cko1");
	210	if (IS_ERR(cko1_sel) \|\| IS_ERR(pll4)
	211	\|\| IS_ERR(pll4_post) \|\| IS_ERR(cko1)) {
	212	pr_err("cko1 setup failed!\n");
	213	goto put_clk;
	214	}
	215	/*
	216	* Setting pll4 at 768MHz (24MHz * 32)
	217	* So its child clock can get 24MHz easily
	218	*/
	219	clk_set_rate(pll4, 768000000);
	220
	221	clk_set_parent(cko1_sel, pll4_post);
	222	rate = clk_round_rate(cko1, 24000000);
	223	clk_set_rate(cko1, rate);
	224	put_clk:
	225	if (!IS_ERR(cko1_sel))
	226	clk_put(cko1_sel);
	227	if (!IS_ERR(pll4_post))
	228	clk_put(pll4_post);
	229	if (!IS_ERR(pll4))
	230	clk_put(pll4);
	231	if (!IS_ERR(cko1))
	232	clk_put(cko1);
	233	}
	234
	235	static void __init imx6q_sabresd_init(void)
	236	{
	237	imx6q_sabresd_cko1_setup();
	238	}
	239
d6e0d9fc FL	240	static void __init imx6q_1588_init(void)
	241	{
	242	struct regmap *gpr;
	243
	244	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	245	if (!IS_ERR(gpr))
6d6fc501 PZ	246	regmap_update_bits(gpr, IOMUXC_GPR1,
	247	IMX6Q_GPR1_ENET_CLK_SEL_MASK,
	248	IMX6Q_GPR1_ENET_CLK_SEL_ANATOP);
d6e0d9fc FL	249	else
	250	pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
	251
	252	}
396bf1c2 RZ	253	static void __init imx6q_usb_init(void)
396bf1c2 RZ	254	{
e95dddb3	255	imx_anatop_usb_chrg_detect_disable();
396bf1c2 RZ	256	}
396bf1c2 RZ	257
13eed989 SG	258	static void __init imx6q_init_machine(void)
13eed989 SG	259	{
477fce49	260	if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
14078291	261	imx6q_sabrelite_cko1_setup();
e7eccc7e NC	262	else if (of_machine_is_compatible("fsl,imx6q-sabresd") \|\|
	263	of_machine_is_compatible("fsl,imx6dl-sabresd"))
	264	imx6q_sabresd_init();
477fce49	265
14078291 SH	266	imx6q_enet_phy_init();
14078291 SH	267
13eed989 SG	268	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
13eed989 SG	269
e95dddb3	270	imx_anatop_init();
13eed989	271	imx6q_pm_init();
396bf1c2	272	imx6q_usb_init();
d6e0d9fc	273	imx6q_1588_init();
13eed989 SG	274	}
13eed989 SG	275
96574a6d SG	276	#define OCOTP_CFG3 0x440
	277	#define OCOTP_CFG3_SPEED_SHIFT 16
	278	#define OCOTP_CFG3_SPEED_1P2GHZ 0x3
	279
	280	static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
	281	{
	282	struct device_node *np;
	283	void __iomem *base;
	284	u32 val;
	285
	286	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
	287	if (!np) {
	288	pr_warn("failed to find ocotp node\n");
	289	return;
	290	}
	291
	292	base = of_iomap(np, 0);
	293	if (!base) {
	294	pr_warn("failed to map ocotp\n");
	295	goto put_node;
	296	}
	297
	298	val = readl_relaxed(base + OCOTP_CFG3);
	299	val >>= OCOTP_CFG3_SPEED_SHIFT;
	300	if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ)
	301	if (opp_disable(cpu_dev, 1200000000))
	302	pr_warn("failed to disable 1.2 GHz OPP\n");
	303
	304	put_node:
	305	of_node_put(np);
	306	}
	307
	308	static void __init imx6q_opp_init(struct device *cpu_dev)
	309	{
	310	struct device_node *np;
	311
	312	np = of_find_node_by_path("/cpus/cpu@0");
	313	if (!np) {
	314	pr_warn("failed to find cpu0 node\n");
	315	return;
	316	}
	317
	318	cpu_dev->of_node = np;
	319	if (of_init_opp_table(cpu_dev)) {
	320	pr_warn("failed to init OPP table\n");
	321	goto put_node;
	322	}
	323
	324	imx6q_opp_check_1p2ghz(cpu_dev);
	325
	326	put_node:
	327	of_node_put(np);
	328	}
	329
f8c11b2b	330	static struct platform_device imx6q_cpufreq_pdev = {
96574a6d SG	331	.name = "imx6q-cpufreq",
	332	};
	333
b9d18dc3 RL	334	static void __init imx6q_init_late(void)
b9d18dc3 RL	335	{
e5f9dec8 SG	336	/*
	337	* WAIT mode is broken on TO 1.0 and 1.1, so there is no point
	338	* to run cpuidle on them.
	339	*/
	340	if (imx6q_revision() > IMX_CHIP_REVISION_1_1)
	341	imx6q_cpuidle_init();
96574a6d SG	342
	343	if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
	344	imx6q_opp_init(&imx6q_cpufreq_pdev.dev);
	345	platform_device_register(&imx6q_cpufreq_pdev);
	346	}
b9d18dc3 RL	347	}
b9d18dc3 RL	348
13eed989 SG	349	static void __init imx6q_map_io(void)
13eed989 SG	350	{
3e549a69	351	debug_ll_io_init();
13eed989 SG	352	imx_scu_map_io();
	353	}
	354
b3a9c315 DB	355	#ifdef CONFIG_CACHE_L2X0
	356	static void __init imx6q_init_l2cache(void)
	357	{
	358	void __iomem *l2x0_base;
	359	struct device_node *np;
	360	unsigned int val;
	361
	362	np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
	363	if (!np)
	364	goto out;
	365
	366	l2x0_base = of_iomap(np, 0);
	367	if (!l2x0_base) {
	368	of_node_put(np);
	369	goto out;
	370	}
	371
	372	/* Configure the L2 PREFETCH and POWER registers */
	373	val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
	374	val \|= 0x70800000;
	375	writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL);
	376	val = L2X0_DYNAMIC_CLK_GATING_EN \| L2X0_STNDBY_MODE_EN;
	377	writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL);
	378
	379	iounmap(l2x0_base);
	380	of_node_put(np);
	381
	382	out:
	383	l2x0_of_init(0, ~0UL);
	384	}
	385	#else
	386	static inline void imx6q_init_l2cache(void) {}
	387	#endif
	388
13eed989 SG	389	static void __init imx6q_init_irq(void)
13eed989 SG	390	{
3c03a2fe	391	imx6q_init_revision();
b3a9c315	392	imx6q_init_l2cache();
13eed989 SG	393	imx_src_init();
13eed989 SG	394	imx_gpc_init();
0529e315	395	irqchip_init();
13eed989 SG	396	}
	397
	398	static void __init imx6q_timer_init(void)
	399	{
53bb71da	400	of_clk_init(NULL);
da4a686a	401	clocksource_of_init();
3c03a2fe SG	402	imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
3c03a2fe SG	403	imx6q_revision());
13eed989 SG	404	}
13eed989 SG	405
13eed989	406	static const char *imx6q_dt_compat[] __initdata = {
3c03a2fe	407	"fsl,imx6dl",
3f8976d9	408	"fsl,imx6q",
13eed989 SG	409	NULL,
	410	};
	411
3c03a2fe	412	DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
e4f2d979	413	.smp = smp_ops(imx_smp_ops),
13eed989 SG	414	.map_io = imx6q_map_io,
13eed989 SG	415	.init_irq = imx6q_init_irq,
6bb27d73	416	.init_time = imx6q_timer_init,
13eed989	417	.init_machine = imx6q_init_machine,
b9d18dc3	418	.init_late = imx6q_init_late,
13eed989	419	.dt_compat = imx6q_dt_compat,
0575fb75	420	.restart = imx6q_restart,
13eed989	421	MACHINE_END