[deliverable/linux.git] / arch / arm / mach-imx / mach-imx6q.c

/*
 * Copyright 2011-2013 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clocksource.h>
#include <linux/cpu.h>
#include <linux/delay.h>
#include <linux/export.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/opp.h>
#include <linux/phy.h>
#include <linux/regmap.h>
#include <linux/micrel_phy.h>
#include <linux/mfd/syscon.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h>

#include "common.h"
#include "cpuidle.h"
#include "hardware.h"

static u32 chip_revision;

int imx6q_revision(void)
{
	return chip_revision;
}

static void __init imx6q_init_revision(void)
{
	u32 rev = imx_anatop_get_digprog();

	switch (rev & 0xff) {
	case 0:
		chip_revision = IMX_CHIP_REVISION_1_0;
		break;
	case 1:
		chip_revision = IMX_CHIP_REVISION_1_1;
		break;
	case 2:
		chip_revision = IMX_CHIP_REVISION_1_2;
		break;
	default:
		chip_revision = IMX_CHIP_REVISION_UNKNOWN;
	}

	mxc_set_cpu_type(rev >> 16 & 0xff);
}

static void imx6q_restart(char mode, const char *cmd)
{
	struct device_node *np;
	void __iomem *wdog_base;

	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt");
	wdog_base = of_iomap(np, 0);
	if (!wdog_base)
		goto soft;

	imx_src_prepare_restart();

	/* enable wdog */
	writew_relaxed(1 << 2, wdog_base);
	/* write twice to ensure the request will not get ignored */
	writew_relaxed(1 << 2, wdog_base);

	/* wait for reset to assert ... */
	mdelay(500);

	pr_err("Watchdog reset failed to assert reset\n");

	/* delay to allow the serial port to show the message */
	mdelay(50);

soft:
	/* we'll take a jump through zero as a poor second */
	soft_restart(0);
}

/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
static int ksz9021rn_phy_fixup(struct phy_device *phydev)
{
	if (IS_BUILTIN(CONFIG_PHYLIB)) {
		/* min rx data delay */
		phy_write(phydev, 0x0b, 0x8105);
		phy_write(phydev, 0x0c, 0x0000);

		/* max rx/tx clock delay, min rx/tx control delay */
		phy_write(phydev, 0x0b, 0x8104);
		phy_write(phydev, 0x0c, 0xf0f0);
		phy_write(phydev, 0x0b, 0x104);
	}

	return 0;
}

static void __init imx6q_sabrelite_cko1_setup(void)
{
	struct clk *cko1_sel, *ahb, *cko1;
	unsigned long rate;

	cko1_sel = clk_get_sys(NULL, "cko1_sel");
	ahb = clk_get_sys(NULL, "ahb");
	cko1 = clk_get_sys(NULL, "cko1");
	if (IS_ERR(cko1_sel) || IS_ERR(ahb) || IS_ERR(cko1)) {
		pr_err("cko1 setup failed!\n");
		goto put_clk;
	}
	clk_set_parent(cko1_sel, ahb);
	rate = clk_round_rate(cko1, 16000000);
	clk_set_rate(cko1, rate);
put_clk:
	if (!IS_ERR(cko1_sel))
		clk_put(cko1_sel);
	if (!IS_ERR(ahb))
		clk_put(ahb);
	if (!IS_ERR(cko1))
		clk_put(cko1);
}

static void __init imx6q_sabrelite_init(void)
{
	if (IS_BUILTIN(CONFIG_PHYLIB))
		phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
				ksz9021rn_phy_fixup);
	imx6q_sabrelite_cko1_setup();
}

static void __init imx6q_1588_init(void)
{
	struct regmap *gpr;

	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	if (!IS_ERR(gpr))
		regmap_update_bits(gpr, 0x4, 1 << 21, 1 << 21);
	else
		pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");

}
static void __init imx6q_usb_init(void)
{
	imx_anatop_usb_chrg_detect_disable();
}

static void __init imx6q_init_machine(void)
{
	if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
		imx6q_sabrelite_init();

	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);

	imx_anatop_init();
	imx6q_pm_init();
	imx6q_usb_init();
	imx6q_1588_init();
}

#define OCOTP_CFG3			0x440
#define OCOTP_CFG3_SPEED_SHIFT		16
#define OCOTP_CFG3_SPEED_1P2GHZ		0x3

static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
{
	struct device_node *np;
	void __iomem *base;
	u32 val;

	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
	if (!np) {
		pr_warn("failed to find ocotp node\n");
		return;
	}

	base = of_iomap(np, 0);
	if (!base) {
		pr_warn("failed to map ocotp\n");
		goto put_node;
	}

	val = readl_relaxed(base + OCOTP_CFG3);
	val >>= OCOTP_CFG3_SPEED_SHIFT;
	if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ)
		if (opp_disable(cpu_dev, 1200000000))
			pr_warn("failed to disable 1.2 GHz OPP\n");

put_node:
	of_node_put(np);
}

static void __init imx6q_opp_init(struct device *cpu_dev)
{
	struct device_node *np;

	np = of_find_node_by_path("/cpus/cpu@0");
	if (!np) {
		pr_warn("failed to find cpu0 node\n");
		return;
	}

	cpu_dev->of_node = np;
	if (of_init_opp_table(cpu_dev)) {
		pr_warn("failed to init OPP table\n");
		goto put_node;
	}

	imx6q_opp_check_1p2ghz(cpu_dev);

put_node:
	of_node_put(np);
}

static struct platform_device imx6q_cpufreq_pdev = {
	.name = "imx6q-cpufreq",
};

static void __init imx6q_init_late(void)
{
	/*
	 * WAIT mode is broken on TO 1.0 and 1.1, so there is no point
	 * to run cpuidle on them.
	 */
	if (imx6q_revision() > IMX_CHIP_REVISION_1_1)
		imx6q_cpuidle_init();

	if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
		imx6q_opp_init(&imx6q_cpufreq_pdev.dev);
		platform_device_register(&imx6q_cpufreq_pdev);
	}
}

static void __init imx6q_map_io(void)
{
	debug_ll_io_init();
	imx_scu_map_io();
}

static void __init imx6q_init_irq(void)
{
	imx6q_init_revision();
	l2x0_of_init(0, ~0UL);
	imx_src_init();
	imx_gpc_init();
	irqchip_init();
}

static void __init imx6q_timer_init(void)
{
	mx6q_clocks_init();
	clocksource_of_init();
	imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
			      imx6q_revision());
}

static const char *imx6q_dt_compat[] __initdata = {
	"fsl,imx6dl",
	"fsl,imx6q",
	NULL,
};

DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
	.smp		= smp_ops(imx_smp_ops),
	.map_io		= imx6q_map_io,
	.init_irq	= imx6q_init_irq,
	.init_time	= imx6q_timer_init,
	.init_machine	= imx6q_init_machine,
	.init_late      = imx6q_init_late,
	.dt_compat	= imx6q_dt_compat,
	.restart	= imx6q_restart,
MACHINE_END
Commit	Line	Data
13eed989	1	/*
e95dddb3	2	* Copyright 2011-2013 Freescale Semiconductor, Inc.
13eed989 SG	3	* Copyright 2011 Linaro Ltd.
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
a258561d RZ	13	#include <linux/clk.h>
a258561d RZ	14	#include <linux/clkdev.h>
da4a686a	15	#include <linux/clocksource.h>
96574a6d	16	#include <linux/cpu.h>
0575fb75	17	#include <linux/delay.h>
b9d18dc3	18	#include <linux/export.h>
13eed989	19	#include <linux/init.h>
0575fb75	20	#include <linux/io.h>
13eed989	21	#include <linux/irq.h>
0529e315	22	#include <linux/irqchip.h>
13eed989	23	#include <linux/of.h>
0575fb75	24	#include <linux/of_address.h>
13eed989 SG	25	#include <linux/of_irq.h>
13eed989 SG	26	#include <linux/of_platform.h>
96574a6d	27	#include <linux/opp.h>
477fce49	28	#include <linux/phy.h>
baa64151	29	#include <linux/regmap.h>
477fce49	30	#include <linux/micrel_phy.h>
baa64151	31	#include <linux/mfd/syscon.h>
13eed989	32	#include <asm/hardware/cache-l2x0.h>
13eed989	33	#include <asm/mach/arch.h>
3e549a69	34	#include <asm/mach/map.h>
9f97da78	35	#include <asm/system_misc.h>
13eed989	36
e3372474	37	#include "common.h"
e29248c9	38	#include "cpuidle.h"
50f2de61	39	#include "hardware.h"
b9d18dc3	40
3c03a2fe	41	static u32 chip_revision;
b29b3e6f	42
b1a3582d	43	int imx6q_revision(void)
b29b3e6f	44	{
3c03a2fe SG	45	return chip_revision;
3c03a2fe SG	46	}
b29b3e6f	47
3c03a2fe SG	48	static void __init imx6q_init_revision(void)
	49	{
	50	u32 rev = imx_anatop_get_digprog();
b29b3e6f SG	51
	52	switch (rev & 0xff) {
	53	case 0:
3c03a2fe SG	54	chip_revision = IMX_CHIP_REVISION_1_0;
3c03a2fe SG	55	break;
b29b3e6f	56	case 1:
3c03a2fe SG	57	chip_revision = IMX_CHIP_REVISION_1_1;
3c03a2fe SG	58	break;
b29b3e6f	59	case 2:
3c03a2fe SG	60	chip_revision = IMX_CHIP_REVISION_1_2;
3c03a2fe SG	61	break;
b29b3e6f	62	default:
3c03a2fe	63	chip_revision = IMX_CHIP_REVISION_UNKNOWN;
b29b3e6f	64	}
3c03a2fe SG	65
3c03a2fe SG	66	mxc_set_cpu_type(rev >> 16 & 0xff);
b29b3e6f SG	67	}
b29b3e6f SG	68
f8c11b2b	69	static void imx6q_restart(char mode, const char *cmd)
0575fb75 SG	70	{
	71	struct device_node *np;
	72	void __iomem *wdog_base;
	73
	74	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt");
	75	wdog_base = of_iomap(np, 0);
	76	if (!wdog_base)
	77	goto soft;
	78
	79	imx_src_prepare_restart();
	80
	81	/* enable wdog */
	82	writew_relaxed(1 << 2, wdog_base);
	83	/* write twice to ensure the request will not get ignored */
	84	writew_relaxed(1 << 2, wdog_base);
	85
	86	/* wait for reset to assert ... */
	87	mdelay(500);
	88
	89	pr_err("Watchdog reset failed to assert reset\n");
	90
	91	/* delay to allow the serial port to show the message */
	92	mdelay(50);
	93
	94	soft:
	95	/* we'll take a jump through zero as a poor second */
	96	soft_restart(0);
	97	}
	98
477fce49 RZ	99	/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
	100	static int ksz9021rn_phy_fixup(struct phy_device *phydev)
	101	{
9f9ba0fd	102	if (IS_BUILTIN(CONFIG_PHYLIB)) {
ef441806 SG	103	/* min rx data delay */
	104	phy_write(phydev, 0x0b, 0x8105);
	105	phy_write(phydev, 0x0c, 0x0000);
477fce49	106
ef441806 SG	107	/* max rx/tx clock delay, min rx/tx control delay */
	108	phy_write(phydev, 0x0b, 0x8104);
	109	phy_write(phydev, 0x0c, 0xf0f0);
	110	phy_write(phydev, 0x0b, 0x104);
	111	}
477fce49 RZ	112
	113	return 0;
	114	}
	115
a258561d RZ	116	static void __init imx6q_sabrelite_cko1_setup(void)
	117	{
	118	struct clk cko1_sel, ahb, *cko1;
	119	unsigned long rate;
	120
	121	cko1_sel = clk_get_sys(NULL, "cko1_sel");
	122	ahb = clk_get_sys(NULL, "ahb");
	123	cko1 = clk_get_sys(NULL, "cko1");
	124	if (IS_ERR(cko1_sel) \|\| IS_ERR(ahb) \|\| IS_ERR(cko1)) {
	125	pr_err("cko1 setup failed!\n");
	126	goto put_clk;
	127	}
	128	clk_set_parent(cko1_sel, ahb);
	129	rate = clk_round_rate(cko1, 16000000);
	130	clk_set_rate(cko1, rate);
a258561d RZ	131	put_clk:
	132	if (!IS_ERR(cko1_sel))
	133	clk_put(cko1_sel);
	134	if (!IS_ERR(ahb))
	135	clk_put(ahb);
	136	if (!IS_ERR(cko1))
	137	clk_put(cko1);
	138	}
	139
071dea50 RZ	140	static void __init imx6q_sabrelite_init(void)
071dea50 RZ	141	{
9f9ba0fd	142	if (IS_BUILTIN(CONFIG_PHYLIB))
ef441806	143	phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
071dea50	144	ksz9021rn_phy_fixup);
a258561d	145	imx6q_sabrelite_cko1_setup();
071dea50 RZ	146	}
071dea50 RZ	147
d6e0d9fc FL	148	static void __init imx6q_1588_init(void)
	149	{
	150	struct regmap *gpr;
	151
	152	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	153	if (!IS_ERR(gpr))
	154	regmap_update_bits(gpr, 0x4, 1 << 21, 1 << 21);
	155	else
	156	pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
	157
	158	}
396bf1c2 RZ	159	static void __init imx6q_usb_init(void)
396bf1c2 RZ	160	{
e95dddb3	161	imx_anatop_usb_chrg_detect_disable();
396bf1c2 RZ	162	}
396bf1c2 RZ	163
13eed989 SG	164	static void __init imx6q_init_machine(void)
13eed989 SG	165	{
477fce49	166	if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
071dea50	167	imx6q_sabrelite_init();
477fce49	168
13eed989 SG	169	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
13eed989 SG	170
e95dddb3	171	imx_anatop_init();
13eed989	172	imx6q_pm_init();
396bf1c2	173	imx6q_usb_init();
d6e0d9fc	174	imx6q_1588_init();
13eed989 SG	175	}
13eed989 SG	176
96574a6d SG	177	#define OCOTP_CFG3 0x440
	178	#define OCOTP_CFG3_SPEED_SHIFT 16
	179	#define OCOTP_CFG3_SPEED_1P2GHZ 0x3
	180
	181	static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
	182	{
	183	struct device_node *np;
	184	void __iomem *base;
	185	u32 val;
	186
	187	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
	188	if (!np) {
	189	pr_warn("failed to find ocotp node\n");
	190	return;
	191	}
	192
	193	base = of_iomap(np, 0);
	194	if (!base) {
	195	pr_warn("failed to map ocotp\n");
	196	goto put_node;
	197	}
	198
	199	val = readl_relaxed(base + OCOTP_CFG3);
	200	val >>= OCOTP_CFG3_SPEED_SHIFT;
	201	if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ)
	202	if (opp_disable(cpu_dev, 1200000000))
	203	pr_warn("failed to disable 1.2 GHz OPP\n");
	204
	205	put_node:
	206	of_node_put(np);
	207	}
	208
	209	static void __init imx6q_opp_init(struct device *cpu_dev)
	210	{
	211	struct device_node *np;
	212
	213	np = of_find_node_by_path("/cpus/cpu@0");
	214	if (!np) {
	215	pr_warn("failed to find cpu0 node\n");
	216	return;
	217	}
	218
	219	cpu_dev->of_node = np;
	220	if (of_init_opp_table(cpu_dev)) {
	221	pr_warn("failed to init OPP table\n");
	222	goto put_node;
	223	}
	224
	225	imx6q_opp_check_1p2ghz(cpu_dev);
	226
	227	put_node:
	228	of_node_put(np);
	229	}
	230
f8c11b2b	231	static struct platform_device imx6q_cpufreq_pdev = {
96574a6d SG	232	.name = "imx6q-cpufreq",
	233	};
	234
b9d18dc3 RL	235	static void __init imx6q_init_late(void)
b9d18dc3 RL	236	{
e5f9dec8 SG	237	/*
	238	* WAIT mode is broken on TO 1.0 and 1.1, so there is no point
	239	* to run cpuidle on them.
	240	*/
	241	if (imx6q_revision() > IMX_CHIP_REVISION_1_1)
	242	imx6q_cpuidle_init();
96574a6d SG	243
	244	if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
	245	imx6q_opp_init(&imx6q_cpufreq_pdev.dev);
	246	platform_device_register(&imx6q_cpufreq_pdev);
	247	}
b9d18dc3 RL	248	}
b9d18dc3 RL	249
13eed989 SG	250	static void __init imx6q_map_io(void)
13eed989 SG	251	{
3e549a69	252	debug_ll_io_init();
13eed989 SG	253	imx_scu_map_io();
	254	}
	255
13eed989 SG	256	static void __init imx6q_init_irq(void)
13eed989 SG	257	{
3c03a2fe	258	imx6q_init_revision();
13eed989 SG	259	l2x0_of_init(0, ~0UL);
	260	imx_src_init();
	261	imx_gpc_init();
0529e315	262	irqchip_init();
13eed989 SG	263	}
	264
	265	static void __init imx6q_timer_init(void)
	266	{
	267	mx6q_clocks_init();
da4a686a	268	clocksource_of_init();
3c03a2fe SG	269	imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
3c03a2fe SG	270	imx6q_revision());
13eed989 SG	271	}
13eed989 SG	272
13eed989	273	static const char *imx6q_dt_compat[] __initdata = {
3c03a2fe	274	"fsl,imx6dl",
3f8976d9	275	"fsl,imx6q",
13eed989 SG	276	NULL,
	277	};
	278
3c03a2fe	279	DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
e4f2d979	280	.smp = smp_ops(imx_smp_ops),
13eed989 SG	281	.map_io = imx6q_map_io,
13eed989 SG	282	.init_irq = imx6q_init_irq,
6bb27d73	283	.init_time = imx6q_timer_init,
13eed989	284	.init_machine = imx6q_init_machine,
b9d18dc3	285	.init_late = imx6q_init_late,
13eed989	286	.dt_compat = imx6q_dt_compat,
0575fb75	287	.restart = imx6q_restart,
13eed989	288	MACHINE_END