[deliverable/linux.git] / arch / arm / mach-imx / mach-imx6q.c

/*
 * Copyright 2011-2013 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/clocksource.h>
#include <linux/cpu.h>
#include <linux/delay.h>
#include <linux/export.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/opp.h>
#include <linux/phy.h>
#include <linux/reboot.h>
#include <linux/regmap.h>
#include <linux/micrel_phy.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h>

#include "common.h"
#include "cpuidle.h"
#include "hardware.h"

static u32 chip_revision;

int imx6q_revision(void)
{
	return chip_revision;
}

static void __init imx6q_init_revision(void)
{
	u32 rev = imx_anatop_get_digprog();

	switch (rev & 0xff) {
	case 0:
		chip_revision = IMX_CHIP_REVISION_1_0;
		break;
	case 1:
		chip_revision = IMX_CHIP_REVISION_1_1;
		break;
	case 2:
		chip_revision = IMX_CHIP_REVISION_1_2;
		break;
	default:
		chip_revision = IMX_CHIP_REVISION_UNKNOWN;
	}

	mxc_set_cpu_type(rev >> 16 & 0xff);
}

static void imx6q_restart(enum reboot_mode mode, const char *cmd)
{
	struct device_node *np;
	void __iomem *wdog_base;

	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt");
	wdog_base = of_iomap(np, 0);
	if (!wdog_base)
		goto soft;

	imx_src_prepare_restart();

	/* enable wdog */
	writew_relaxed(1 << 2, wdog_base);
	/* write twice to ensure the request will not get ignored */
	writew_relaxed(1 << 2, wdog_base);

	/* wait for reset to assert ... */
	mdelay(500);

	pr_err("Watchdog reset failed to assert reset\n");

	/* delay to allow the serial port to show the message */
	mdelay(50);

soft:
	/* we'll take a jump through zero as a poor second */
	soft_restart(0);
}

/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
static int ksz9021rn_phy_fixup(struct phy_device *phydev)
{
	if (IS_BUILTIN(CONFIG_PHYLIB)) {
		/* min rx data delay */
		phy_write(phydev, 0x0b, 0x8105);
		phy_write(phydev, 0x0c, 0x0000);

		/* max rx/tx clock delay, min rx/tx control delay */
		phy_write(phydev, 0x0b, 0x8104);
		phy_write(phydev, 0x0c, 0xf0f0);
		phy_write(phydev, 0x0b, 0x104);
	}

	return 0;
}

static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
{
	phy_write(dev, 0x0d, device);
	phy_write(dev, 0x0e, reg);
	phy_write(dev, 0x0d, (1 << 14) | device);
	phy_write(dev, 0x0e, val);
}

static int ksz9031rn_phy_fixup(struct phy_device *dev)
{
	/*
	 * min rx data delay, max rx/tx clock delay,
	 * min rx/tx control delay
	 */
	mmd_write_reg(dev, 2, 4, 0);
	mmd_write_reg(dev, 2, 5, 0);
	mmd_write_reg(dev, 2, 8, 0x003ff);

	return 0;
}

static int ar8031_phy_fixup(struct phy_device *dev)
{
	u16 val;

	/* To enable AR8031 output a 125MHz clk from CLK_25M */
	phy_write(dev, 0xd, 0x7);
	phy_write(dev, 0xe, 0x8016);
	phy_write(dev, 0xd, 0x4007);

	val = phy_read(dev, 0xe);
	val &= 0xffe3;
	val |= 0x18;
	phy_write(dev, 0xe, val);

	/* introduce tx clock delay */
	phy_write(dev, 0x1d, 0x5);
	val = phy_read(dev, 0x1e);
	val |= 0x0100;
	phy_write(dev, 0x1e, val);

	return 0;
}

static void __init imx6q_sabrelite_cko1_setup(void)
{
	struct clk *cko1_sel, *ahb, *cko1;
	unsigned long rate;

	cko1_sel = clk_get_sys(NULL, "cko1_sel");
	ahb = clk_get_sys(NULL, "ahb");
	cko1 = clk_get_sys(NULL, "cko1");
	if (IS_ERR(cko1_sel) || IS_ERR(ahb) || IS_ERR(cko1)) {
		pr_err("cko1 setup failed!\n");
		goto put_clk;
	}
	clk_set_parent(cko1_sel, ahb);
	rate = clk_round_rate(cko1, 16000000);
	clk_set_rate(cko1, rate);
put_clk:
	if (!IS_ERR(cko1_sel))
		clk_put(cko1_sel);
	if (!IS_ERR(ahb))
		clk_put(ahb);
	if (!IS_ERR(cko1))
		clk_put(cko1);
}

#define PHY_ID_AR8031	0x004dd074

static void __init imx6q_enet_phy_init(void)
{
	if (IS_BUILTIN(CONFIG_PHYLIB)) {
		phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
				ksz9021rn_phy_fixup);
		phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
				ksz9031rn_phy_fixup);
		phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
				ar8031_phy_fixup);
	}
}

static void __init imx6q_sabresd_cko1_setup(void)
{
	struct clk *cko1_sel, *pll4, *pll4_post, *cko1;
	unsigned long rate;

	cko1_sel = clk_get_sys(NULL, "cko1_sel");
	pll4 = clk_get_sys(NULL, "pll4_audio");
	pll4_post = clk_get_sys(NULL, "pll4_post_div");
	cko1 = clk_get_sys(NULL, "cko1");
	if (IS_ERR(cko1_sel) || IS_ERR(pll4)
			|| IS_ERR(pll4_post) || IS_ERR(cko1)) {
		pr_err("cko1 setup failed!\n");
		goto put_clk;
	}
	/*
	 * Setting pll4 at 768MHz (24MHz * 32)
	 * So its child clock can get 24MHz easily
	 */
	clk_set_rate(pll4, 768000000);

	clk_set_parent(cko1_sel, pll4_post);
	rate = clk_round_rate(cko1, 24000000);
	clk_set_rate(cko1, rate);
put_clk:
	if (!IS_ERR(cko1_sel))
		clk_put(cko1_sel);
	if (!IS_ERR(pll4_post))
		clk_put(pll4_post);
	if (!IS_ERR(pll4))
		clk_put(pll4);
	if (!IS_ERR(cko1))
		clk_put(cko1);
}

static void __init imx6q_sabresd_init(void)
{
	imx6q_sabresd_cko1_setup();
}

static void __init imx6q_1588_init(void)
{
	struct regmap *gpr;

	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	if (!IS_ERR(gpr))
		regmap_update_bits(gpr, IOMUXC_GPR1,
				IMX6Q_GPR1_ENET_CLK_SEL_MASK,
				IMX6Q_GPR1_ENET_CLK_SEL_ANATOP);
	else
		pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");

}

static void __init imx6q_init_machine(void)
{
	if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
		imx6q_sabrelite_cko1_setup();
	else if (of_machine_is_compatible("fsl,imx6q-sabresd") ||
			of_machine_is_compatible("fsl,imx6dl-sabresd"))
		imx6q_sabresd_init();

	imx6q_enet_phy_init();

	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);

	imx_anatop_init();
	imx6q_pm_init();
	imx6q_1588_init();
}

#define OCOTP_CFG3			0x440
#define OCOTP_CFG3_SPEED_SHIFT		16
#define OCOTP_CFG3_SPEED_1P2GHZ		0x3

static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
{
	struct device_node *np;
	void __iomem *base;
	u32 val;

	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
	if (!np) {
		pr_warn("failed to find ocotp node\n");
		return;
	}

	base = of_iomap(np, 0);
	if (!base) {
		pr_warn("failed to map ocotp\n");
		goto put_node;
	}

	val = readl_relaxed(base + OCOTP_CFG3);
	val >>= OCOTP_CFG3_SPEED_SHIFT;
	if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ)
		if (opp_disable(cpu_dev, 1200000000))
			pr_warn("failed to disable 1.2 GHz OPP\n");

put_node:
	of_node_put(np);
}

static void __init imx6q_opp_init(struct device *cpu_dev)
{
	struct device_node *np;

	np = of_find_node_by_path("/cpus/cpu@0");
	if (!np) {
		pr_warn("failed to find cpu0 node\n");
		return;
	}

	cpu_dev->of_node = np;
	if (of_init_opp_table(cpu_dev)) {
		pr_warn("failed to init OPP table\n");
		goto put_node;
	}

	imx6q_opp_check_1p2ghz(cpu_dev);

put_node:
	of_node_put(np);
}

static struct platform_device imx6q_cpufreq_pdev = {
	.name = "imx6q-cpufreq",
};

static void __init imx6q_init_late(void)
{
	/*
	 * WAIT mode is broken on TO 1.0 and 1.1, so there is no point
	 * to run cpuidle on them.
	 */
	if (imx6q_revision() > IMX_CHIP_REVISION_1_1)
		imx6q_cpuidle_init();

	if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
		imx6q_opp_init(&imx6q_cpufreq_pdev.dev);
		platform_device_register(&imx6q_cpufreq_pdev);
	}
}

static void __init imx6q_map_io(void)
{
	debug_ll_io_init();
	imx_scu_map_io();
}

static void __init imx6q_init_irq(void)
{
	imx6q_init_revision();
	imx_init_l2cache();
	imx_src_init();
	imx_gpc_init();
	irqchip_init();
}

static void __init imx6q_timer_init(void)
{
	of_clk_init(NULL);
	clocksource_of_init();
	imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
			      imx6q_revision());
}

static const char *imx6q_dt_compat[] __initdata = {
	"fsl,imx6dl",
	"fsl,imx6q",
	NULL,
};

DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
	.smp		= smp_ops(imx_smp_ops),
	.map_io		= imx6q_map_io,
	.init_irq	= imx6q_init_irq,
	.init_time	= imx6q_timer_init,
	.init_machine	= imx6q_init_machine,
	.init_late      = imx6q_init_late,
	.dt_compat	= imx6q_dt_compat,
	.restart	= imx6q_restart,
MACHINE_END
Commit	Line	Data
13eed989	1	/*
e95dddb3	2	* Copyright 2011-2013 Freescale Semiconductor, Inc.
13eed989 SG	3	* Copyright 2011 Linaro Ltd.
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
a258561d	13	#include <linux/clk.h>
53bb71da	14	#include <linux/clk-provider.h>
a258561d	15	#include <linux/clkdev.h>
da4a686a	16	#include <linux/clocksource.h>
96574a6d	17	#include <linux/cpu.h>
0575fb75	18	#include <linux/delay.h>
b9d18dc3	19	#include <linux/export.h>
13eed989	20	#include <linux/init.h>
0575fb75	21	#include <linux/io.h>
13eed989	22	#include <linux/irq.h>
0529e315	23	#include <linux/irqchip.h>
13eed989	24	#include <linux/of.h>
0575fb75	25	#include <linux/of_address.h>
13eed989 SG	26	#include <linux/of_irq.h>
13eed989 SG	27	#include <linux/of_platform.h>
96574a6d	28	#include <linux/opp.h>
477fce49	29	#include <linux/phy.h>
7b6d864b	30	#include <linux/reboot.h>
baa64151	31	#include <linux/regmap.h>
477fce49	32	#include <linux/micrel_phy.h>
baa64151	33	#include <linux/mfd/syscon.h>
6d6fc501	34	#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
13eed989	35	#include <asm/mach/arch.h>
3e549a69	36	#include <asm/mach/map.h>
9f97da78	37	#include <asm/system_misc.h>
13eed989	38
e3372474	39	#include "common.h"
e29248c9	40	#include "cpuidle.h"
50f2de61	41	#include "hardware.h"
b9d18dc3	42
3c03a2fe	43	static u32 chip_revision;
b29b3e6f	44
b1a3582d	45	int imx6q_revision(void)
b29b3e6f	46	{
3c03a2fe SG	47	return chip_revision;
3c03a2fe SG	48	}
b29b3e6f	49
3c03a2fe SG	50	static void __init imx6q_init_revision(void)
	51	{
	52	u32 rev = imx_anatop_get_digprog();
b29b3e6f SG	53
	54	switch (rev & 0xff) {
	55	case 0:
3c03a2fe SG	56	chip_revision = IMX_CHIP_REVISION_1_0;
3c03a2fe SG	57	break;
b29b3e6f	58	case 1:
3c03a2fe SG	59	chip_revision = IMX_CHIP_REVISION_1_1;
3c03a2fe SG	60	break;
b29b3e6f	61	case 2:
3c03a2fe SG	62	chip_revision = IMX_CHIP_REVISION_1_2;
3c03a2fe SG	63	break;
b29b3e6f	64	default:
3c03a2fe	65	chip_revision = IMX_CHIP_REVISION_UNKNOWN;
b29b3e6f	66	}
3c03a2fe SG	67
3c03a2fe SG	68	mxc_set_cpu_type(rev >> 16 & 0xff);
b29b3e6f SG	69	}
b29b3e6f SG	70
7b6d864b	71	static void imx6q_restart(enum reboot_mode mode, const char *cmd)
0575fb75 SG	72	{
	73	struct device_node *np;
	74	void __iomem *wdog_base;
	75
	76	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt");
	77	wdog_base = of_iomap(np, 0);
	78	if (!wdog_base)
	79	goto soft;
	80
	81	imx_src_prepare_restart();
	82
	83	/* enable wdog */
	84	writew_relaxed(1 << 2, wdog_base);
	85	/* write twice to ensure the request will not get ignored */
	86	writew_relaxed(1 << 2, wdog_base);
	87
	88	/* wait for reset to assert ... */
	89	mdelay(500);
	90
	91	pr_err("Watchdog reset failed to assert reset\n");
	92
	93	/* delay to allow the serial port to show the message */
	94	mdelay(50);
	95
	96	soft:
	97	/* we'll take a jump through zero as a poor second */
	98	soft_restart(0);
	99	}
	100
477fce49 RZ	101	/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
	102	static int ksz9021rn_phy_fixup(struct phy_device *phydev)
	103	{
9f9ba0fd	104	if (IS_BUILTIN(CONFIG_PHYLIB)) {
ef441806 SG	105	/* min rx data delay */
	106	phy_write(phydev, 0x0b, 0x8105);
	107	phy_write(phydev, 0x0c, 0x0000);
477fce49	108
ef441806 SG	109	/* max rx/tx clock delay, min rx/tx control delay */
	110	phy_write(phydev, 0x0b, 0x8104);
	111	phy_write(phydev, 0x0c, 0xf0f0);
	112	phy_write(phydev, 0x0b, 0x104);
	113	}
477fce49 RZ	114
	115	return 0;
	116	}
	117
dbf6719a SH	118	static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
	119	{
	120	phy_write(dev, 0x0d, device);
	121	phy_write(dev, 0x0e, reg);
	122	phy_write(dev, 0x0d, (1 << 14) \| device);
	123	phy_write(dev, 0x0e, val);
	124	}
	125
	126	static int ksz9031rn_phy_fixup(struct phy_device *dev)
	127	{
	128	/*
	129	* min rx data delay, max rx/tx clock delay,
	130	* min rx/tx control delay
	131	*/
	132	mmd_write_reg(dev, 2, 4, 0);
	133	mmd_write_reg(dev, 2, 5, 0);
	134	mmd_write_reg(dev, 2, 8, 0x003ff);
	135
	136	return 0;
	137	}
	138
12da4844 SH	139	static int ar8031_phy_fixup(struct phy_device *dev)
	140	{
	141	u16 val;
	142
	143	/* To enable AR8031 output a 125MHz clk from CLK_25M */
	144	phy_write(dev, 0xd, 0x7);
	145	phy_write(dev, 0xe, 0x8016);
	146	phy_write(dev, 0xd, 0x4007);
	147
	148	val = phy_read(dev, 0xe);
	149	val &= 0xffe3;
	150	val \|= 0x18;
	151	phy_write(dev, 0xe, val);
	152
	153	/* introduce tx clock delay */
	154	phy_write(dev, 0x1d, 0x5);
	155	val = phy_read(dev, 0x1e);
	156	val \|= 0x0100;
	157	phy_write(dev, 0x1e, val);
	158
	159	return 0;
	160	}
	161
a258561d RZ	162	static void __init imx6q_sabrelite_cko1_setup(void)
	163	{
	164	struct clk cko1_sel, ahb, *cko1;
	165	unsigned long rate;
	166
	167	cko1_sel = clk_get_sys(NULL, "cko1_sel");
	168	ahb = clk_get_sys(NULL, "ahb");
	169	cko1 = clk_get_sys(NULL, "cko1");
	170	if (IS_ERR(cko1_sel) \|\| IS_ERR(ahb) \|\| IS_ERR(cko1)) {
	171	pr_err("cko1 setup failed!\n");
	172	goto put_clk;
	173	}
	174	clk_set_parent(cko1_sel, ahb);
	175	rate = clk_round_rate(cko1, 16000000);
	176	clk_set_rate(cko1, rate);
a258561d RZ	177	put_clk:
	178	if (!IS_ERR(cko1_sel))
	179	clk_put(cko1_sel);
	180	if (!IS_ERR(ahb))
	181	clk_put(ahb);
	182	if (!IS_ERR(cko1))
	183	clk_put(cko1);
	184	}
	185
12da4844 SH	186	#define PHY_ID_AR8031 0x004dd074
12da4844 SH	187
14078291	188	static void __init imx6q_enet_phy_init(void)
071dea50	189	{
14078291	190	if (IS_BUILTIN(CONFIG_PHYLIB)) {
ef441806	191	phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
071dea50	192	ksz9021rn_phy_fixup);
dbf6719a SH	193	phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
dbf6719a SH	194	ksz9031rn_phy_fixup);
12da4844 SH	195	phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
12da4844 SH	196	ar8031_phy_fixup);
14078291	197	}
071dea50 RZ	198	}
071dea50 RZ	199
e7eccc7e NC	200	static void __init imx6q_sabresd_cko1_setup(void)
	201	{
	202	struct clk cko1_sel, pll4, pll4_post, cko1;
	203	unsigned long rate;
	204
	205	cko1_sel = clk_get_sys(NULL, "cko1_sel");
	206	pll4 = clk_get_sys(NULL, "pll4_audio");
	207	pll4_post = clk_get_sys(NULL, "pll4_post_div");
	208	cko1 = clk_get_sys(NULL, "cko1");
	209	if (IS_ERR(cko1_sel) \|\| IS_ERR(pll4)
	210	\|\| IS_ERR(pll4_post) \|\| IS_ERR(cko1)) {
	211	pr_err("cko1 setup failed!\n");
	212	goto put_clk;
	213	}
	214	/*
	215	* Setting pll4 at 768MHz (24MHz * 32)
	216	* So its child clock can get 24MHz easily
	217	*/
	218	clk_set_rate(pll4, 768000000);
	219
	220	clk_set_parent(cko1_sel, pll4_post);
	221	rate = clk_round_rate(cko1, 24000000);
	222	clk_set_rate(cko1, rate);
	223	put_clk:
	224	if (!IS_ERR(cko1_sel))
	225	clk_put(cko1_sel);
	226	if (!IS_ERR(pll4_post))
	227	clk_put(pll4_post);
	228	if (!IS_ERR(pll4))
	229	clk_put(pll4);
	230	if (!IS_ERR(cko1))
	231	clk_put(cko1);
	232	}
	233
	234	static void __init imx6q_sabresd_init(void)
	235	{
	236	imx6q_sabresd_cko1_setup();
	237	}
	238
d6e0d9fc FL	239	static void __init imx6q_1588_init(void)
	240	{
	241	struct regmap *gpr;
	242
	243	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	244	if (!IS_ERR(gpr))
6d6fc501 PZ	245	regmap_update_bits(gpr, IOMUXC_GPR1,
	246	IMX6Q_GPR1_ENET_CLK_SEL_MASK,
	247	IMX6Q_GPR1_ENET_CLK_SEL_ANATOP);
d6e0d9fc FL	248	else
	249	pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
	250
	251	}
396bf1c2	252
13eed989 SG	253	static void __init imx6q_init_machine(void)
13eed989 SG	254	{
477fce49	255	if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
14078291	256	imx6q_sabrelite_cko1_setup();
e7eccc7e NC	257	else if (of_machine_is_compatible("fsl,imx6q-sabresd") \|\|
	258	of_machine_is_compatible("fsl,imx6dl-sabresd"))
	259	imx6q_sabresd_init();
477fce49	260
14078291 SH	261	imx6q_enet_phy_init();
14078291 SH	262
13eed989 SG	263	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
13eed989 SG	264
e95dddb3	265	imx_anatop_init();
13eed989	266	imx6q_pm_init();
d6e0d9fc	267	imx6q_1588_init();
13eed989 SG	268	}
13eed989 SG	269
96574a6d SG	270	#define OCOTP_CFG3 0x440
	271	#define OCOTP_CFG3_SPEED_SHIFT 16
	272	#define OCOTP_CFG3_SPEED_1P2GHZ 0x3
	273
	274	static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
	275	{
	276	struct device_node *np;
	277	void __iomem *base;
	278	u32 val;
	279
	280	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
	281	if (!np) {
	282	pr_warn("failed to find ocotp node\n");
	283	return;
	284	}
	285
	286	base = of_iomap(np, 0);
	287	if (!base) {
	288	pr_warn("failed to map ocotp\n");
	289	goto put_node;
	290	}
	291
	292	val = readl_relaxed(base + OCOTP_CFG3);
	293	val >>= OCOTP_CFG3_SPEED_SHIFT;
	294	if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ)
	295	if (opp_disable(cpu_dev, 1200000000))
	296	pr_warn("failed to disable 1.2 GHz OPP\n");
	297
	298	put_node:
	299	of_node_put(np);
	300	}
	301
	302	static void __init imx6q_opp_init(struct device *cpu_dev)
	303	{
	304	struct device_node *np;
	305
	306	np = of_find_node_by_path("/cpus/cpu@0");
	307	if (!np) {
	308	pr_warn("failed to find cpu0 node\n");
	309	return;
	310	}
	311
	312	cpu_dev->of_node = np;
	313	if (of_init_opp_table(cpu_dev)) {
	314	pr_warn("failed to init OPP table\n");
	315	goto put_node;
	316	}
	317
	318	imx6q_opp_check_1p2ghz(cpu_dev);
	319
	320	put_node:
	321	of_node_put(np);
	322	}
	323
f8c11b2b	324	static struct platform_device imx6q_cpufreq_pdev = {
96574a6d SG	325	.name = "imx6q-cpufreq",
	326	};
	327
b9d18dc3 RL	328	static void __init imx6q_init_late(void)
b9d18dc3 RL	329	{
e5f9dec8 SG	330	/*
	331	* WAIT mode is broken on TO 1.0 and 1.1, so there is no point
	332	* to run cpuidle on them.
	333	*/
	334	if (imx6q_revision() > IMX_CHIP_REVISION_1_1)
	335	imx6q_cpuidle_init();
96574a6d SG	336
	337	if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
	338	imx6q_opp_init(&imx6q_cpufreq_pdev.dev);
	339	platform_device_register(&imx6q_cpufreq_pdev);
	340	}
b9d18dc3 RL	341	}
b9d18dc3 RL	342
13eed989 SG	343	static void __init imx6q_map_io(void)
13eed989 SG	344	{
3e549a69	345	debug_ll_io_init();
13eed989 SG	346	imx_scu_map_io();
	347	}
	348
13eed989 SG	349	static void __init imx6q_init_irq(void)
13eed989 SG	350	{
3c03a2fe	351	imx6q_init_revision();
e6a07569	352	imx_init_l2cache();
13eed989 SG	353	imx_src_init();
13eed989 SG	354	imx_gpc_init();
0529e315	355	irqchip_init();
13eed989 SG	356	}
	357
	358	static void __init imx6q_timer_init(void)
	359	{
53bb71da	360	of_clk_init(NULL);
da4a686a	361	clocksource_of_init();
3c03a2fe SG	362	imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
3c03a2fe SG	363	imx6q_revision());
13eed989 SG	364	}
13eed989 SG	365
13eed989	366	static const char *imx6q_dt_compat[] __initdata = {
3c03a2fe	367	"fsl,imx6dl",
3f8976d9	368	"fsl,imx6q",
13eed989 SG	369	NULL,
	370	};
	371
3c03a2fe	372	DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
e4f2d979	373	.smp = smp_ops(imx_smp_ops),
13eed989 SG	374	.map_io = imx6q_map_io,
13eed989 SG	375	.init_irq = imx6q_init_irq,
6bb27d73	376	.init_time = imx6q_timer_init,
13eed989	377	.init_machine = imx6q_init_machine,
b9d18dc3	378	.init_late = imx6q_init_late,
13eed989	379	.dt_compat = imx6q_dt_compat,
0575fb75	380	.restart = imx6q_restart,
13eed989	381	MACHINE_END