Commit | Line | Data |
---|---|---|
13eed989 | 1 | /* |
e95dddb3 | 2 | * Copyright 2011-2013 Freescale Semiconductor, Inc. |
13eed989 SG |
3 | * Copyright 2011 Linaro Ltd. |
4 | * | |
5 | * The code contained herein is licensed under the GNU General Public | |
6 | * License. You may obtain a copy of the GNU General Public License | |
7 | * Version 2 or later at the following locations: | |
8 | * | |
9 | * http://www.opensource.org/licenses/gpl-license.html | |
10 | * http://www.gnu.org/copyleft/gpl.html | |
11 | */ | |
12 | ||
a258561d RZ |
13 | #include <linux/clk.h> |
14 | #include <linux/clkdev.h> | |
96574a6d | 15 | #include <linux/cpu.h> |
4bb1d09f | 16 | #include <linux/delay.h> |
b9d18dc3 | 17 | #include <linux/export.h> |
13eed989 | 18 | #include <linux/init.h> |
0575fb75 | 19 | #include <linux/io.h> |
13eed989 | 20 | #include <linux/irq.h> |
0529e315 | 21 | #include <linux/irqchip.h> |
13eed989 | 22 | #include <linux/of.h> |
0575fb75 | 23 | #include <linux/of_address.h> |
13eed989 SG |
24 | #include <linux/of_irq.h> |
25 | #include <linux/of_platform.h> | |
e4db1c74 | 26 | #include <linux/pm_opp.h> |
4bb1d09f | 27 | #include <linux/pci.h> |
477fce49 | 28 | #include <linux/phy.h> |
7b6d864b | 29 | #include <linux/reboot.h> |
baa64151 | 30 | #include <linux/regmap.h> |
477fce49 | 31 | #include <linux/micrel_phy.h> |
baa64151 | 32 | #include <linux/mfd/syscon.h> |
6d6fc501 | 33 | #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> |
13eed989 | 34 | #include <asm/mach/arch.h> |
3e549a69 | 35 | #include <asm/mach/map.h> |
9f97da78 | 36 | #include <asm/system_misc.h> |
13eed989 | 37 | |
e3372474 | 38 | #include "common.h" |
e29248c9 | 39 | #include "cpuidle.h" |
50f2de61 | 40 | #include "hardware.h" |
b9d18dc3 | 41 | |
477fce49 RZ |
42 | /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */ |
43 | static int ksz9021rn_phy_fixup(struct phy_device *phydev) | |
44 | { | |
9f9ba0fd | 45 | if (IS_BUILTIN(CONFIG_PHYLIB)) { |
ef441806 | 46 | /* min rx data delay */ |
dc76a1ad DN |
47 | phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, |
48 | 0x8000 | MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW); | |
49 | phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000); | |
477fce49 | 50 | |
ef441806 | 51 | /* max rx/tx clock delay, min rx/tx control delay */ |
dc76a1ad DN |
52 | phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, |
53 | 0x8000 | MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW); | |
54 | phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0); | |
55 | phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, | |
56 | MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW); | |
ef441806 | 57 | } |
477fce49 RZ |
58 | |
59 | return 0; | |
60 | } | |
61 | ||
dbf6719a | 62 | static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val) |
a258561d | 63 | { |
dbf6719a SH |
64 | phy_write(dev, 0x0d, device); |
65 | phy_write(dev, 0x0e, reg); | |
66 | phy_write(dev, 0x0d, (1 << 14) | device); | |
67 | phy_write(dev, 0x0e, val); | |
a258561d RZ |
68 | } |
69 | ||
dbf6719a | 70 | static int ksz9031rn_phy_fixup(struct phy_device *dev) |
071dea50 | 71 | { |
dbf6719a SH |
72 | /* |
73 | * min rx data delay, max rx/tx clock delay, | |
74 | * min rx/tx control delay | |
75 | */ | |
76 | mmd_write_reg(dev, 2, 4, 0); | |
77 | mmd_write_reg(dev, 2, 5, 0); | |
78 | mmd_write_reg(dev, 2, 8, 0x003ff); | |
79 | ||
80 | return 0; | |
071dea50 RZ |
81 | } |
82 | ||
4bb1d09f TH |
83 | /* |
84 | * fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High | |
85 | * as they are used for slots1-7 PERST# | |
86 | */ | |
87 | static void ventana_pciesw_early_fixup(struct pci_dev *dev) | |
88 | { | |
89 | u32 dw; | |
90 | ||
91 | if (!of_machine_is_compatible("gw,ventana")) | |
92 | return; | |
93 | ||
94 | if (dev->devfn != 0) | |
95 | return; | |
96 | ||
97 | pci_read_config_dword(dev, 0x62c, &dw); | |
98 | dw |= 0xaaa8; // GPIO1-7 outputs | |
99 | pci_write_config_dword(dev, 0x62c, dw); | |
100 | ||
101 | pci_read_config_dword(dev, 0x644, &dw); | |
102 | dw |= 0xfe; // GPIO1-7 output high | |
103 | pci_write_config_dword(dev, 0x644, dw); | |
104 | ||
105 | msleep(100); | |
106 | } | |
107 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609, ventana_pciesw_early_fixup); | |
108 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, ventana_pciesw_early_fixup); | |
109 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, ventana_pciesw_early_fixup); | |
110 | ||
12da4844 | 111 | static int ar8031_phy_fixup(struct phy_device *dev) |
e7eccc7e | 112 | { |
12da4844 SH |
113 | u16 val; |
114 | ||
115 | /* To enable AR8031 output a 125MHz clk from CLK_25M */ | |
116 | phy_write(dev, 0xd, 0x7); | |
117 | phy_write(dev, 0xe, 0x8016); | |
118 | phy_write(dev, 0xd, 0x4007); | |
119 | ||
120 | val = phy_read(dev, 0xe); | |
121 | val &= 0xffe3; | |
122 | val |= 0x18; | |
123 | phy_write(dev, 0xe, val); | |
124 | ||
125 | /* introduce tx clock delay */ | |
126 | phy_write(dev, 0x1d, 0x5); | |
127 | val = phy_read(dev, 0x1e); | |
128 | val |= 0x0100; | |
129 | phy_write(dev, 0x1e, val); | |
130 | ||
131 | return 0; | |
e7eccc7e NC |
132 | } |
133 | ||
12da4844 SH |
134 | #define PHY_ID_AR8031 0x004dd074 |
135 | ||
208d7baf RK |
136 | static int ar8035_phy_fixup(struct phy_device *dev) |
137 | { | |
138 | u16 val; | |
139 | ||
140 | /* Ar803x phy SmartEEE feature cause link status generates glitch, | |
141 | * which cause ethernet link down/up issue, so disable SmartEEE | |
142 | */ | |
143 | phy_write(dev, 0xd, 0x3); | |
144 | phy_write(dev, 0xe, 0x805d); | |
145 | phy_write(dev, 0xd, 0x4003); | |
146 | ||
147 | val = phy_read(dev, 0xe); | |
148 | phy_write(dev, 0xe, val & ~(1 << 8)); | |
149 | ||
150 | /* | |
151 | * Enable 125MHz clock from CLK_25M on the AR8031. This | |
152 | * is fed in to the IMX6 on the ENET_REF_CLK (V22) pad. | |
153 | * Also, introduce a tx clock delay. | |
154 | * | |
155 | * This is the same as is the AR8031 fixup. | |
156 | */ | |
157 | ar8031_phy_fixup(dev); | |
158 | ||
159 | /*check phy power*/ | |
160 | val = phy_read(dev, 0x0); | |
161 | if (val & BMCR_PDOWN) | |
162 | phy_write(dev, 0x0, val & ~BMCR_PDOWN); | |
163 | ||
164 | return 0; | |
165 | } | |
166 | ||
167 | #define PHY_ID_AR8035 0x004dd072 | |
168 | ||
14078291 | 169 | static void __init imx6q_enet_phy_init(void) |
e7eccc7e | 170 | { |
14078291 | 171 | if (IS_BUILTIN(CONFIG_PHYLIB)) { |
ef441806 | 172 | phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, |
071dea50 | 173 | ksz9021rn_phy_fixup); |
dbf6719a SH |
174 | phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK, |
175 | ksz9031rn_phy_fixup); | |
12da4844 SH |
176 | phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff, |
177 | ar8031_phy_fixup); | |
208d7baf RK |
178 | phy_register_fixup_for_uid(PHY_ID_AR8035, 0xffffffef, |
179 | ar8035_phy_fixup); | |
14078291 | 180 | } |
e7eccc7e NC |
181 | } |
182 | ||
d6e0d9fc FL |
183 | static void __init imx6q_1588_init(void) |
184 | { | |
810c0ca8 SG |
185 | struct device_node *np; |
186 | struct clk *ptp_clk; | |
187 | struct clk *enet_ref; | |
d6e0d9fc | 188 | struct regmap *gpr; |
810c0ca8 | 189 | u32 clksel; |
d6e0d9fc | 190 | |
810c0ca8 SG |
191 | np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-fec"); |
192 | if (!np) { | |
193 | pr_warn("%s: failed to find fec node\n", __func__); | |
194 | return; | |
195 | } | |
196 | ||
197 | ptp_clk = of_clk_get(np, 2); | |
198 | if (IS_ERR(ptp_clk)) { | |
199 | pr_warn("%s: failed to get ptp clock\n", __func__); | |
200 | goto put_node; | |
201 | } | |
202 | ||
203 | enet_ref = clk_get_sys(NULL, "enet_ref"); | |
204 | if (IS_ERR(enet_ref)) { | |
205 | pr_warn("%s: failed to get enet clock\n", __func__); | |
206 | goto put_ptp_clk; | |
207 | } | |
208 | ||
209 | /* | |
210 | * If enet_ref from ANATOP/CCM is the PTP clock source, we need to | |
211 | * set bit IOMUXC_GPR1[21]. Or the PTP clock must be from pad | |
212 | * (external OSC), and we need to clear the bit. | |
213 | */ | |
214 | clksel = ptp_clk == enet_ref ? IMX6Q_GPR1_ENET_CLK_SEL_ANATOP : | |
215 | IMX6Q_GPR1_ENET_CLK_SEL_PAD; | |
d6e0d9fc FL |
216 | gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); |
217 | if (!IS_ERR(gpr)) | |
6d6fc501 PZ |
218 | regmap_update_bits(gpr, IOMUXC_GPR1, |
219 | IMX6Q_GPR1_ENET_CLK_SEL_MASK, | |
810c0ca8 | 220 | clksel); |
d6e0d9fc FL |
221 | else |
222 | pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n"); | |
223 | ||
810c0ca8 SG |
224 | clk_put(enet_ref); |
225 | put_ptp_clk: | |
226 | clk_put(ptp_clk); | |
227 | put_node: | |
228 | of_node_put(np); | |
d6e0d9fc | 229 | } |
396bf1c2 | 230 | |
7ea653ef PZ |
231 | static void __init imx6q_axi_init(void) |
232 | { | |
233 | struct regmap *gpr; | |
234 | unsigned int mask; | |
235 | ||
236 | gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); | |
237 | if (!IS_ERR(gpr)) { | |
238 | /* | |
239 | * Enable the cacheable attribute of VPU and IPU | |
240 | * AXI transactions. | |
241 | */ | |
242 | mask = IMX6Q_GPR4_VPU_WR_CACHE_SEL | | |
243 | IMX6Q_GPR4_VPU_RD_CACHE_SEL | | |
244 | IMX6Q_GPR4_VPU_P_WR_CACHE_VAL | | |
245 | IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK | | |
246 | IMX6Q_GPR4_IPU_WR_CACHE_CTL | | |
247 | IMX6Q_GPR4_IPU_RD_CACHE_CTL; | |
248 | regmap_update_bits(gpr, IOMUXC_GPR4, mask, mask); | |
249 | ||
250 | /* Increase IPU read QoS priority */ | |
251 | regmap_update_bits(gpr, IOMUXC_GPR6, | |
252 | IMX6Q_GPR6_IPU1_ID00_RD_QOS_MASK | | |
253 | IMX6Q_GPR6_IPU1_ID01_RD_QOS_MASK, | |
254 | (0xf << 16) | (0x7 << 20)); | |
255 | regmap_update_bits(gpr, IOMUXC_GPR7, | |
256 | IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK | | |
257 | IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK, | |
258 | (0xf << 16) | (0x7 << 20)); | |
259 | } else { | |
260 | pr_warn("failed to find fsl,imx6q-iomuxc-gpr regmap\n"); | |
261 | } | |
262 | } | |
263 | ||
13eed989 SG |
264 | static void __init imx6q_init_machine(void) |
265 | { | |
a2887546 SG |
266 | struct device *parent; |
267 | ||
4d9d18a5 | 268 | imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", |
3f75978b | 269 | imx_get_soc_revision()); |
4d9d18a5 | 270 | |
87a84b69 SG |
271 | mxc_arch_reset_init_dt(); |
272 | ||
a2887546 SG |
273 | parent = imx_soc_device_init(); |
274 | if (parent == NULL) | |
275 | pr_warn("failed to initialize soc device\n"); | |
276 | ||
14078291 | 277 | imx6q_enet_phy_init(); |
477fce49 | 278 | |
a2887546 | 279 | of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); |
13eed989 | 280 | |
e95dddb3 | 281 | imx_anatop_init(); |
df595746 | 282 | cpu_is_imx6q() ? imx6q_pm_init() : imx6dl_pm_init(); |
d6e0d9fc | 283 | imx6q_1588_init(); |
7ea653ef | 284 | imx6q_axi_init(); |
13eed989 SG |
285 | } |
286 | ||
96574a6d SG |
287 | #define OCOTP_CFG3 0x440 |
288 | #define OCOTP_CFG3_SPEED_SHIFT 16 | |
289 | #define OCOTP_CFG3_SPEED_1P2GHZ 0x3 | |
c962a099 AH |
290 | #define OCOTP_CFG3_SPEED_996MHZ 0x2 |
291 | #define OCOTP_CFG3_SPEED_852MHZ 0x1 | |
96574a6d | 292 | |
c962a099 | 293 | static void __init imx6q_opp_check_speed_grading(struct device *cpu_dev) |
96574a6d SG |
294 | { |
295 | struct device_node *np; | |
296 | void __iomem *base; | |
297 | u32 val; | |
298 | ||
299 | np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp"); | |
300 | if (!np) { | |
301 | pr_warn("failed to find ocotp node\n"); | |
302 | return; | |
303 | } | |
304 | ||
305 | base = of_iomap(np, 0); | |
306 | if (!base) { | |
307 | pr_warn("failed to map ocotp\n"); | |
308 | goto put_node; | |
309 | } | |
310 | ||
c962a099 AH |
311 | /* |
312 | * SPEED_GRADING[1:0] defines the max speed of ARM: | |
313 | * 2b'11: 1200000000Hz; | |
314 | * 2b'10: 996000000Hz; | |
315 | * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz. | |
316 | * 2b'00: 792000000Hz; | |
317 | * We need to set the max speed of ARM according to fuse map. | |
318 | */ | |
96574a6d SG |
319 | val = readl_relaxed(base + OCOTP_CFG3); |
320 | val >>= OCOTP_CFG3_SPEED_SHIFT; | |
c962a099 AH |
321 | val &= 0x3; |
322 | ||
a49fb63c | 323 | if ((val != OCOTP_CFG3_SPEED_1P2GHZ) && cpu_is_imx6q()) |
5d4879cd | 324 | if (dev_pm_opp_disable(cpu_dev, 1200000000)) |
96574a6d | 325 | pr_warn("failed to disable 1.2 GHz OPP\n"); |
c962a099 AH |
326 | if (val < OCOTP_CFG3_SPEED_996MHZ) |
327 | if (dev_pm_opp_disable(cpu_dev, 996000000)) | |
328 | pr_warn("failed to disable 996 MHz OPP\n"); | |
329 | if (cpu_is_imx6q()) { | |
330 | if (val != OCOTP_CFG3_SPEED_852MHZ) | |
331 | if (dev_pm_opp_disable(cpu_dev, 852000000)) | |
332 | pr_warn("failed to disable 852 MHz OPP\n"); | |
333 | } | |
96574a6d SG |
334 | |
335 | put_node: | |
336 | of_node_put(np); | |
337 | } | |
338 | ||
b494b48d | 339 | static void __init imx6q_opp_init(void) |
96574a6d SG |
340 | { |
341 | struct device_node *np; | |
b494b48d | 342 | struct device *cpu_dev = get_cpu_device(0); |
96574a6d | 343 | |
b494b48d SK |
344 | if (!cpu_dev) { |
345 | pr_warn("failed to get cpu0 device\n"); | |
346 | return; | |
347 | } | |
cdc58d60 | 348 | np = of_node_get(cpu_dev->of_node); |
96574a6d SG |
349 | if (!np) { |
350 | pr_warn("failed to find cpu0 node\n"); | |
351 | return; | |
352 | } | |
353 | ||
96574a6d SG |
354 | if (of_init_opp_table(cpu_dev)) { |
355 | pr_warn("failed to init OPP table\n"); | |
356 | goto put_node; | |
357 | } | |
358 | ||
c962a099 | 359 | imx6q_opp_check_speed_grading(cpu_dev); |
96574a6d SG |
360 | |
361 | put_node: | |
362 | of_node_put(np); | |
363 | } | |
364 | ||
f8c11b2b | 365 | static struct platform_device imx6q_cpufreq_pdev = { |
96574a6d SG |
366 | .name = "imx6q-cpufreq", |
367 | }; | |
368 | ||
b9d18dc3 RL |
369 | static void __init imx6q_init_late(void) |
370 | { | |
e5f9dec8 SG |
371 | /* |
372 | * WAIT mode is broken on TO 1.0 and 1.1, so there is no point | |
373 | * to run cpuidle on them. | |
374 | */ | |
3f75978b | 375 | if (imx_get_soc_revision() > IMX_CHIP_REVISION_1_1) |
e5f9dec8 | 376 | imx6q_cpuidle_init(); |
96574a6d SG |
377 | |
378 | if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) { | |
b494b48d | 379 | imx6q_opp_init(); |
96574a6d SG |
380 | platform_device_register(&imx6q_cpufreq_pdev); |
381 | } | |
b9d18dc3 RL |
382 | } |
383 | ||
13eed989 SG |
384 | static void __init imx6q_map_io(void) |
385 | { | |
3e549a69 | 386 | debug_ll_io_init(); |
13eed989 SG |
387 | imx_scu_map_io(); |
388 | } | |
389 | ||
13eed989 SG |
390 | static void __init imx6q_init_irq(void) |
391 | { | |
f1c6f314 | 392 | imx_init_revision_from_anatop(); |
e6a07569 | 393 | imx_init_l2cache(); |
13eed989 SG |
394 | imx_src_init(); |
395 | imx_gpc_init(); | |
0529e315 | 396 | irqchip_init(); |
13eed989 SG |
397 | } |
398 | ||
8756dd92 | 399 | static const char * const imx6q_dt_compat[] __initconst = { |
3c03a2fe | 400 | "fsl,imx6dl", |
3f8976d9 | 401 | "fsl,imx6q", |
13eed989 SG |
402 | NULL, |
403 | }; | |
404 | ||
3c03a2fe | 405 | DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)") |
e4f2d979 | 406 | .smp = smp_ops(imx_smp_ops), |
13eed989 SG |
407 | .map_io = imx6q_map_io, |
408 | .init_irq = imx6q_init_irq, | |
13eed989 | 409 | .init_machine = imx6q_init_machine, |
b9d18dc3 | 410 | .init_late = imx6q_init_late, |
13eed989 | 411 | .dt_compat = imx6q_dt_compat, |
87a84b69 | 412 | .restart = mxc_restart, |
13eed989 | 413 | MACHINE_END |