Commit | Line | Data |
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13eed989 | 1 | /* |
e95dddb3 | 2 | * Copyright 2011-2013 Freescale Semiconductor, Inc. |
13eed989 SG |
3 | * Copyright 2011 Linaro Ltd. |
4 | * | |
5 | * The code contained herein is licensed under the GNU General Public | |
6 | * License. You may obtain a copy of the GNU General Public License | |
7 | * Version 2 or later at the following locations: | |
8 | * | |
9 | * http://www.opensource.org/licenses/gpl-license.html | |
10 | * http://www.gnu.org/copyleft/gpl.html | |
11 | */ | |
12 | ||
a258561d RZ |
13 | #include <linux/clk.h> |
14 | #include <linux/clkdev.h> | |
96574a6d | 15 | #include <linux/cpu.h> |
0575fb75 | 16 | #include <linux/delay.h> |
b9d18dc3 | 17 | #include <linux/export.h> |
13eed989 | 18 | #include <linux/init.h> |
0575fb75 | 19 | #include <linux/io.h> |
13eed989 | 20 | #include <linux/irq.h> |
0529e315 | 21 | #include <linux/irqchip.h> |
13eed989 | 22 | #include <linux/of.h> |
0575fb75 | 23 | #include <linux/of_address.h> |
13eed989 SG |
24 | #include <linux/of_irq.h> |
25 | #include <linux/of_platform.h> | |
96574a6d | 26 | #include <linux/opp.h> |
477fce49 | 27 | #include <linux/phy.h> |
baa64151 | 28 | #include <linux/regmap.h> |
477fce49 | 29 | #include <linux/micrel_phy.h> |
baa64151 | 30 | #include <linux/mfd/syscon.h> |
58458e03 | 31 | #include <asm/smp_twd.h> |
13eed989 | 32 | #include <asm/hardware/cache-l2x0.h> |
13eed989 | 33 | #include <asm/mach/arch.h> |
3e549a69 | 34 | #include <asm/mach/map.h> |
13eed989 | 35 | #include <asm/mach/time.h> |
9f97da78 | 36 | #include <asm/system_misc.h> |
13eed989 | 37 | |
e3372474 | 38 | #include "common.h" |
e29248c9 | 39 | #include "cpuidle.h" |
50f2de61 | 40 | #include "hardware.h" |
b9d18dc3 | 41 | |
b1a3582d | 42 | int imx6q_revision(void) |
b29b3e6f | 43 | { |
b29b3e6f SG |
44 | static u32 rev; |
45 | ||
e95dddb3 AH |
46 | if (!rev) |
47 | rev = imx_anatop_get_digprog(); | |
b29b3e6f SG |
48 | |
49 | switch (rev & 0xff) { | |
50 | case 0: | |
51 | return IMX_CHIP_REVISION_1_0; | |
52 | case 1: | |
53 | return IMX_CHIP_REVISION_1_1; | |
54 | case 2: | |
55 | return IMX_CHIP_REVISION_1_2; | |
56 | default: | |
57 | return IMX_CHIP_REVISION_UNKNOWN; | |
58 | } | |
59 | } | |
60 | ||
0575fb75 SG |
61 | void imx6q_restart(char mode, const char *cmd) |
62 | { | |
63 | struct device_node *np; | |
64 | void __iomem *wdog_base; | |
65 | ||
66 | np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt"); | |
67 | wdog_base = of_iomap(np, 0); | |
68 | if (!wdog_base) | |
69 | goto soft; | |
70 | ||
71 | imx_src_prepare_restart(); | |
72 | ||
73 | /* enable wdog */ | |
74 | writew_relaxed(1 << 2, wdog_base); | |
75 | /* write twice to ensure the request will not get ignored */ | |
76 | writew_relaxed(1 << 2, wdog_base); | |
77 | ||
78 | /* wait for reset to assert ... */ | |
79 | mdelay(500); | |
80 | ||
81 | pr_err("Watchdog reset failed to assert reset\n"); | |
82 | ||
83 | /* delay to allow the serial port to show the message */ | |
84 | mdelay(50); | |
85 | ||
86 | soft: | |
87 | /* we'll take a jump through zero as a poor second */ | |
88 | soft_restart(0); | |
89 | } | |
90 | ||
477fce49 RZ |
91 | /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */ |
92 | static int ksz9021rn_phy_fixup(struct phy_device *phydev) | |
93 | { | |
9f9ba0fd | 94 | if (IS_BUILTIN(CONFIG_PHYLIB)) { |
ef441806 SG |
95 | /* min rx data delay */ |
96 | phy_write(phydev, 0x0b, 0x8105); | |
97 | phy_write(phydev, 0x0c, 0x0000); | |
477fce49 | 98 | |
ef441806 SG |
99 | /* max rx/tx clock delay, min rx/tx control delay */ |
100 | phy_write(phydev, 0x0b, 0x8104); | |
101 | phy_write(phydev, 0x0c, 0xf0f0); | |
102 | phy_write(phydev, 0x0b, 0x104); | |
103 | } | |
477fce49 RZ |
104 | |
105 | return 0; | |
106 | } | |
107 | ||
a258561d RZ |
108 | static void __init imx6q_sabrelite_cko1_setup(void) |
109 | { | |
110 | struct clk *cko1_sel, *ahb, *cko1; | |
111 | unsigned long rate; | |
112 | ||
113 | cko1_sel = clk_get_sys(NULL, "cko1_sel"); | |
114 | ahb = clk_get_sys(NULL, "ahb"); | |
115 | cko1 = clk_get_sys(NULL, "cko1"); | |
116 | if (IS_ERR(cko1_sel) || IS_ERR(ahb) || IS_ERR(cko1)) { | |
117 | pr_err("cko1 setup failed!\n"); | |
118 | goto put_clk; | |
119 | } | |
120 | clk_set_parent(cko1_sel, ahb); | |
121 | rate = clk_round_rate(cko1, 16000000); | |
122 | clk_set_rate(cko1, rate); | |
a258561d RZ |
123 | put_clk: |
124 | if (!IS_ERR(cko1_sel)) | |
125 | clk_put(cko1_sel); | |
126 | if (!IS_ERR(ahb)) | |
127 | clk_put(ahb); | |
128 | if (!IS_ERR(cko1)) | |
129 | clk_put(cko1); | |
130 | } | |
131 | ||
071dea50 RZ |
132 | static void __init imx6q_sabrelite_init(void) |
133 | { | |
9f9ba0fd | 134 | if (IS_BUILTIN(CONFIG_PHYLIB)) |
ef441806 | 135 | phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, |
071dea50 | 136 | ksz9021rn_phy_fixup); |
a258561d | 137 | imx6q_sabrelite_cko1_setup(); |
071dea50 RZ |
138 | } |
139 | ||
d6e0d9fc FL |
140 | static void __init imx6q_1588_init(void) |
141 | { | |
142 | struct regmap *gpr; | |
143 | ||
144 | gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); | |
145 | if (!IS_ERR(gpr)) | |
146 | regmap_update_bits(gpr, 0x4, 1 << 21, 1 << 21); | |
147 | else | |
148 | pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n"); | |
149 | ||
150 | } | |
396bf1c2 RZ |
151 | static void __init imx6q_usb_init(void) |
152 | { | |
e95dddb3 | 153 | imx_anatop_usb_chrg_detect_disable(); |
396bf1c2 RZ |
154 | } |
155 | ||
13eed989 SG |
156 | static void __init imx6q_init_machine(void) |
157 | { | |
477fce49 | 158 | if (of_machine_is_compatible("fsl,imx6q-sabrelite")) |
071dea50 | 159 | imx6q_sabrelite_init(); |
477fce49 | 160 | |
13eed989 SG |
161 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); |
162 | ||
e95dddb3 | 163 | imx_anatop_init(); |
13eed989 | 164 | imx6q_pm_init(); |
396bf1c2 | 165 | imx6q_usb_init(); |
d6e0d9fc | 166 | imx6q_1588_init(); |
13eed989 SG |
167 | } |
168 | ||
96574a6d SG |
169 | #define OCOTP_CFG3 0x440 |
170 | #define OCOTP_CFG3_SPEED_SHIFT 16 | |
171 | #define OCOTP_CFG3_SPEED_1P2GHZ 0x3 | |
172 | ||
173 | static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev) | |
174 | { | |
175 | struct device_node *np; | |
176 | void __iomem *base; | |
177 | u32 val; | |
178 | ||
179 | np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp"); | |
180 | if (!np) { | |
181 | pr_warn("failed to find ocotp node\n"); | |
182 | return; | |
183 | } | |
184 | ||
185 | base = of_iomap(np, 0); | |
186 | if (!base) { | |
187 | pr_warn("failed to map ocotp\n"); | |
188 | goto put_node; | |
189 | } | |
190 | ||
191 | val = readl_relaxed(base + OCOTP_CFG3); | |
192 | val >>= OCOTP_CFG3_SPEED_SHIFT; | |
193 | if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ) | |
194 | if (opp_disable(cpu_dev, 1200000000)) | |
195 | pr_warn("failed to disable 1.2 GHz OPP\n"); | |
196 | ||
197 | put_node: | |
198 | of_node_put(np); | |
199 | } | |
200 | ||
201 | static void __init imx6q_opp_init(struct device *cpu_dev) | |
202 | { | |
203 | struct device_node *np; | |
204 | ||
205 | np = of_find_node_by_path("/cpus/cpu@0"); | |
206 | if (!np) { | |
207 | pr_warn("failed to find cpu0 node\n"); | |
208 | return; | |
209 | } | |
210 | ||
211 | cpu_dev->of_node = np; | |
212 | if (of_init_opp_table(cpu_dev)) { | |
213 | pr_warn("failed to init OPP table\n"); | |
214 | goto put_node; | |
215 | } | |
216 | ||
217 | imx6q_opp_check_1p2ghz(cpu_dev); | |
218 | ||
219 | put_node: | |
220 | of_node_put(np); | |
221 | } | |
222 | ||
223 | struct platform_device imx6q_cpufreq_pdev = { | |
224 | .name = "imx6q-cpufreq", | |
225 | }; | |
226 | ||
b9d18dc3 RL |
227 | static void __init imx6q_init_late(void) |
228 | { | |
e5f9dec8 SG |
229 | /* |
230 | * WAIT mode is broken on TO 1.0 and 1.1, so there is no point | |
231 | * to run cpuidle on them. | |
232 | */ | |
233 | if (imx6q_revision() > IMX_CHIP_REVISION_1_1) | |
234 | imx6q_cpuidle_init(); | |
96574a6d SG |
235 | |
236 | if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) { | |
237 | imx6q_opp_init(&imx6q_cpufreq_pdev.dev); | |
238 | platform_device_register(&imx6q_cpufreq_pdev); | |
239 | } | |
b9d18dc3 RL |
240 | } |
241 | ||
13eed989 SG |
242 | static void __init imx6q_map_io(void) |
243 | { | |
3e549a69 | 244 | debug_ll_io_init(); |
13eed989 SG |
245 | imx_scu_map_io(); |
246 | } | |
247 | ||
13eed989 SG |
248 | static void __init imx6q_init_irq(void) |
249 | { | |
250 | l2x0_of_init(0, ~0UL); | |
251 | imx_src_init(); | |
252 | imx_gpc_init(); | |
0529e315 | 253 | irqchip_init(); |
13eed989 SG |
254 | } |
255 | ||
256 | static void __init imx6q_timer_init(void) | |
257 | { | |
258 | mx6q_clocks_init(); | |
58458e03 | 259 | twd_local_timer_of_register(); |
7006ba24 | 260 | imx_print_silicon_rev("i.MX6Q", imx6q_revision()); |
13eed989 SG |
261 | } |
262 | ||
13eed989 | 263 | static const char *imx6q_dt_compat[] __initdata = { |
3f8976d9 | 264 | "fsl,imx6q", |
13eed989 SG |
265 | NULL, |
266 | }; | |
267 | ||
268 | DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad (Device Tree)") | |
e4f2d979 | 269 | .smp = smp_ops(imx_smp_ops), |
13eed989 SG |
270 | .map_io = imx6q_map_io, |
271 | .init_irq = imx6q_init_irq, | |
6bb27d73 | 272 | .init_time = imx6q_timer_init, |
13eed989 | 273 | .init_machine = imx6q_init_machine, |
b9d18dc3 | 274 | .init_late = imx6q_init_late, |
13eed989 | 275 | .dt_compat = imx6q_dt_compat, |
0575fb75 | 276 | .restart = imx6q_restart, |
13eed989 | 277 | MACHINE_END |