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31a2fbf7 SG |
1 | /* |
2 | * Copyright 2013 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | */ | |
9 | ||
10 | #include <linux/irqchip.h> | |
11 | #include <linux/of.h> | |
12 | #include <linux/of_platform.h> | |
a9aec30d FD |
13 | #include <linux/mfd/syscon.h> |
14 | #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> | |
15 | #include <linux/regmap.h> | |
31a2fbf7 SG |
16 | #include <asm/mach/arch.h> |
17 | #include <asm/mach/map.h> | |
18 | ||
19 | #include "common.h" | |
751f7e99 | 20 | #include "cpuidle.h" |
31a2fbf7 | 21 | |
a9aec30d FD |
22 | static void __init imx6sl_fec_init(void) |
23 | { | |
24 | struct regmap *gpr; | |
25 | ||
26 | /* set FEC clock from internal PLL clock source */ | |
27 | gpr = syscon_regmap_lookup_by_compatible("fsl,imx6sl-iomuxc-gpr"); | |
28 | if (!IS_ERR(gpr)) { | |
29 | regmap_update_bits(gpr, IOMUXC_GPR1, | |
30 | IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK, 0); | |
31 | regmap_update_bits(gpr, IOMUXC_GPR1, | |
32 | IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK, 0); | |
33 | } else { | |
34 | pr_err("failed to find fsl,imx6sl-iomux-gpr regmap\n"); | |
35 | } | |
36 | } | |
37 | ||
1ed4aaeb JT |
38 | static void __init imx6sl_init_late(void) |
39 | { | |
40 | /* imx6sl reuses imx6q cpufreq driver */ | |
41 | if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) | |
42 | platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0); | |
751f7e99 AH |
43 | |
44 | imx6sl_cpuidle_init(); | |
1ed4aaeb JT |
45 | } |
46 | ||
31a2fbf7 SG |
47 | static void __init imx6sl_init_machine(void) |
48 | { | |
a2887546 SG |
49 | struct device *parent; |
50 | ||
a2887546 SG |
51 | parent = imx_soc_device_init(); |
52 | if (parent == NULL) | |
53 | pr_warn("failed to initialize soc device\n"); | |
54 | ||
55 | of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); | |
a9aec30d FD |
56 | |
57 | imx6sl_fec_init(); | |
9ba64fe3 | 58 | imx_anatop_init(); |
df595746 | 59 | imx6sl_pm_init(); |
31a2fbf7 SG |
60 | } |
61 | ||
62 | static void __init imx6sl_init_irq(void) | |
63 | { | |
14517564 | 64 | imx_gpc_check_dt(); |
d8ce823f | 65 | imx_init_revision_from_anatop(); |
73dada7f | 66 | imx_init_l2cache(); |
31a2fbf7 | 67 | imx_src_init(); |
31a2fbf7 SG |
68 | irqchip_init(); |
69 | } | |
70 | ||
8756dd92 | 71 | static const char * const imx6sl_dt_compat[] __initconst = { |
31a2fbf7 SG |
72 | "fsl,imx6sl", |
73 | NULL, | |
74 | }; | |
75 | ||
76 | DT_MACHINE_START(IMX6SL, "Freescale i.MX6 SoloLite (Device Tree)") | |
31a2fbf7 | 77 | .init_irq = imx6sl_init_irq, |
31a2fbf7 | 78 | .init_machine = imx6sl_init_machine, |
1ed4aaeb | 79 | .init_late = imx6sl_init_late, |
31a2fbf7 | 80 | .dt_compat = imx6sl_dt_compat, |
31a2fbf7 | 81 | MACHINE_END |