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5739b919 AH |
1 | /* |
2 | * Copyright (C) 2015 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | #include <linux/irqchip.h> | |
69f9c504 FD |
9 | #include <linux/mfd/syscon.h> |
10 | #include <linux/mfd/syscon/imx7-iomuxc-gpr.h> | |
5739b919 | 11 | #include <linux/of_platform.h> |
69f9c504 FD |
12 | #include <linux/phy.h> |
13 | #include <linux/regmap.h> | |
14 | ||
5739b919 AH |
15 | #include <asm/mach/arch.h> |
16 | #include <asm/mach/map.h> | |
17 | ||
18 | #include "common.h" | |
19 | ||
69f9c504 FD |
20 | static int ar8031_phy_fixup(struct phy_device *dev) |
21 | { | |
22 | u16 val; | |
23 | ||
24 | /* Set RGMII IO voltage to 1.8V */ | |
25 | phy_write(dev, 0x1d, 0x1f); | |
26 | phy_write(dev, 0x1e, 0x8); | |
27 | ||
28 | /* disable phy AR8031 SmartEEE function. */ | |
29 | phy_write(dev, 0xd, 0x3); | |
30 | phy_write(dev, 0xe, 0x805d); | |
31 | phy_write(dev, 0xd, 0x4003); | |
32 | val = phy_read(dev, 0xe); | |
33 | val &= ~(0x1 << 8); | |
34 | phy_write(dev, 0xe, val); | |
35 | ||
36 | /* introduce tx clock delay */ | |
37 | phy_write(dev, 0x1d, 0x5); | |
38 | val = phy_read(dev, 0x1e); | |
39 | val |= 0x0100; | |
40 | phy_write(dev, 0x1e, val); | |
41 | ||
42 | return 0; | |
43 | } | |
44 | ||
45 | static int bcm54220_phy_fixup(struct phy_device *dev) | |
46 | { | |
47 | /* enable RXC skew select RGMII copper mode */ | |
48 | phy_write(dev, 0x1e, 0x21); | |
49 | phy_write(dev, 0x1f, 0x7ea8); | |
50 | phy_write(dev, 0x1e, 0x2f); | |
51 | phy_write(dev, 0x1f, 0x71b7); | |
52 | ||
53 | return 0; | |
54 | } | |
55 | ||
56 | #define PHY_ID_AR8031 0x004dd074 | |
57 | #define PHY_ID_BCM54220 0x600d8589 | |
58 | ||
59 | static void __init imx7d_enet_phy_init(void) | |
60 | { | |
61 | if (IS_BUILTIN(CONFIG_PHYLIB)) { | |
62 | phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff, | |
63 | ar8031_phy_fixup); | |
64 | phy_register_fixup_for_uid(PHY_ID_BCM54220, 0xffffffff, | |
65 | bcm54220_phy_fixup); | |
66 | } | |
67 | } | |
68 | ||
69 | static void __init imx7d_enet_clk_sel(void) | |
70 | { | |
71 | struct regmap *gpr; | |
72 | ||
73 | gpr = syscon_regmap_lookup_by_compatible("fsl,imx7d-iomuxc-gpr"); | |
74 | if (!IS_ERR(gpr)) { | |
75 | regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK, 0); | |
76 | regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_CLK_DIR_MASK, 0); | |
77 | } else { | |
78 | pr_err("failed to find fsl,imx7d-iomux-gpr regmap\n"); | |
79 | } | |
80 | } | |
81 | ||
82 | static inline void imx7d_enet_init(void) | |
83 | { | |
84 | imx7d_enet_phy_init(); | |
85 | imx7d_enet_clk_sel(); | |
86 | } | |
87 | ||
5739b919 AH |
88 | static void __init imx7d_init_machine(void) |
89 | { | |
90 | struct device *parent; | |
91 | ||
92 | parent = imx_soc_device_init(); | |
93 | if (parent == NULL) | |
94 | pr_warn("failed to initialize soc device\n"); | |
95 | ||
96 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | |
97 | imx_anatop_init(); | |
69f9c504 | 98 | imx7d_enet_init(); |
5739b919 AH |
99 | } |
100 | ||
101 | static void __init imx7d_init_irq(void) | |
102 | { | |
103 | imx_init_revision_from_anatop(); | |
104 | imx_src_init(); | |
105 | irqchip_init(); | |
106 | } | |
107 | ||
19c233b7 | 108 | static const char *const imx7d_dt_compat[] __initconst = { |
5739b919 AH |
109 | "fsl,imx7d", |
110 | NULL, | |
111 | }; | |
112 | ||
113 | DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual (Device Tree)") | |
114 | .init_irq = imx7d_init_irq, | |
115 | .init_machine = imx7d_init_machine, | |
116 | .dt_compat = imx7d_dt_compat, | |
117 | MACHINE_END |