[deliverable/linux.git] / arch / arm / mach-imx / mach-kzm_arm11_01.c

/*
 * KZM-ARM11-01 support
 *  Copyright (C) 2009  Yoichi Yuasa <yuasa@linux-mips.org>
 *
 * based on code for MX31ADS,
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
 *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/smsc911x.h>
#include <linux/types.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>

#include <asm/irq.h>
#include <asm/mach-types.h>
#include <asm/memory.h>
#include <asm/setup.h>
#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>

#include <mach/clock.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx3.h>

#include "devices-imx31.h"

#define KZM_ARM11_IO_ADDRESS(x) (IOMEM(					\
	IMX_IO_P2V_MODULE(x, MX31_CS4) ?:				\
	IMX_IO_P2V_MODULE(x, MX31_CS5)) ?:				\
	MX31_IO_ADDRESS(x))

/*
 *  KZM-ARM11-01 Board Control Registers on FPGA
 */
#define KZM_ARM11_CTL1		(MX31_CS4_BASE_ADDR + 0x1000)
#define KZM_ARM11_CTL2		(MX31_CS4_BASE_ADDR + 0x1001)
#define KZM_ARM11_RSW1		(MX31_CS4_BASE_ADDR + 0x1002)
#define KZM_ARM11_BACK_LIGHT	(MX31_CS4_BASE_ADDR + 0x1004)
#define KZM_ARM11_FPGA_REV	(MX31_CS4_BASE_ADDR + 0x1008)
#define KZM_ARM11_7SEG_LED	(MX31_CS4_BASE_ADDR + 0x1010)
#define KZM_ARM11_LEDS		(MX31_CS4_BASE_ADDR + 0x1020)
#define KZM_ARM11_DIPSW2	(MX31_CS4_BASE_ADDR + 0x1003)

/*
 * External UART for touch panel on FPGA
 */
#define KZM_ARM11_16550		(MX31_CS4_BASE_ADDR + 0x1050)

#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
/*
 * KZM-ARM11-01 has an external UART on FPGA
 */
static struct plat_serial8250_port serial_platform_data[] = {
	{
		.membase	= KZM_ARM11_IO_ADDRESS(KZM_ARM11_16550),
		.mapbase	= KZM_ARM11_16550,
		/* irq number is run-time assigned */
		.irqflags	= IRQ_TYPE_EDGE_RISING,
		.uartclk	= 14745600,
		.regshift	= 0,
		.iotype		= UPIO_MEM,
		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
				  UPF_BUGGY_UART,
	},
	{},
};

static struct resource serial8250_resources[] = {
	{
		.start	= KZM_ARM11_16550,
		.end	= KZM_ARM11_16550 + 0x10,
		.flags	= IORESOURCE_MEM,
	},
	{
		/* irq number is run-time assigned */
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device serial_device = {
	.name		= "serial8250",
	.id		= PLAT8250_DEV_PLATFORM,
	.dev		= {
				.platform_data = serial_platform_data,
			  },
	.num_resources	= ARRAY_SIZE(serial8250_resources),
	.resource	= serial8250_resources,
};

static int __init kzm_init_ext_uart(void)
{
	u8 tmp;

	/*
	 * GPIO 1-1: external UART interrupt line
	 */
	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO));
	gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "ext-uart-int");
	gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));

	/*
	 * Unmask UART interrupt
	 */
	tmp = __raw_readb(KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1));
	tmp |= 0x2;
	__raw_writeb(tmp, KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1));

	serial_platform_data[0].irq =
			gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
	serial8250_resources[1].start =
			gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
	serial8250_resources[1].end =
			gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));

	return platform_device_register(&serial_device);
}
#else
static inline int kzm_init_ext_uart(void)
{
	return 0;
}
#endif

/*
 * SMSC LAN9118
 */
#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
static struct smsc911x_platform_config kzm_smsc9118_config = {
	.phy_interface	= PHY_INTERFACE_MODE_MII,
	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
	.irq_type	= SMSC911X_IRQ_TYPE_PUSH_PULL,
	.flags		= SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
};

static struct resource kzm_smsc9118_resources[] = {
	{
		.start	= MX31_CS5_BASE_ADDR,
		.end	= MX31_CS5_BASE_ADDR + SZ_128K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		/* irq number is run-time assigned */
		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
	},
};

static struct platform_device kzm_smsc9118_device = {
	.name		= "smsc911x",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(kzm_smsc9118_resources),
	.resource	= kzm_smsc9118_resources,
	.dev		= {
				.platform_data = &kzm_smsc9118_config,
			  },
};

static struct regulator_consumer_supply dummy_supplies[] = {
	REGULATOR_SUPPLY("vdd33a", "smsc911x"),
	REGULATOR_SUPPLY("vddvario", "smsc911x"),
};

static int __init kzm_init_smsc9118(void)
{
	/*
	 * GPIO 1-2: SMSC9118 interrupt line
	 */
	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_2, IOMUX_CONFIG_GPIO));
	gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2), "smsc9118-int");
	gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2));

	regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));

	kzm_smsc9118_resources[1].start =
			gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2));
	kzm_smsc9118_resources[1].end =
			gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2));

	return platform_device_register(&kzm_smsc9118_device);
}
#else
static inline int kzm_init_smsc9118(void)
{
	return 0;
}
#endif

#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
static const struct imxuart_platform_data uart_pdata __initconst = {
	.flags = IMXUART_HAVE_RTSCTS,
};

static void __init kzm_init_imx_uart(void)
{
	imx31_add_imx_uart0(&uart_pdata);
	imx31_add_imx_uart1(&uart_pdata);
}
#else
static inline void kzm_init_imx_uart(void)
{
}
#endif

static int kzm_pins[] __initdata = {
	MX31_PIN_CTS1__CTS1,
	MX31_PIN_RTS1__RTS1,
	MX31_PIN_TXD1__TXD1,
	MX31_PIN_RXD1__RXD1,
	MX31_PIN_DCD_DCE1__DCD_DCE1,
	MX31_PIN_RI_DCE1__RI_DCE1,
	MX31_PIN_DSR_DCE1__DSR_DCE1,
	MX31_PIN_DTR_DCE1__DTR_DCE1,
	MX31_PIN_CTS2__CTS2,
	MX31_PIN_RTS2__RTS2,
	MX31_PIN_TXD2__TXD2,
	MX31_PIN_RXD2__RXD2,
	MX31_PIN_DCD_DTE1__DCD_DTE2,
	MX31_PIN_RI_DTE1__RI_DTE2,
	MX31_PIN_DSR_DTE1__DSR_DTE2,
	MX31_PIN_DTR_DTE1__DTR_DTE2,
};

/*
 * Board specific initialization.
 */
static void __init kzm_board_init(void)
{
	imx31_soc_init();

	mxc_iomux_setup_multiple_pins(kzm_pins,
				      ARRAY_SIZE(kzm_pins), "kzm");
	kzm_init_ext_uart();
	kzm_init_smsc9118();
	kzm_init_imx_uart();

	pr_info("Clock input source is 26MHz\n");
}

/*
 * This structure defines static mappings for the kzm-arm11-01 board.
 */
static struct map_desc kzm_io_desc[] __initdata = {
	{
		.virtual	= MX31_CS4_BASE_ADDR_VIRT,
		.pfn		= __phys_to_pfn(MX31_CS4_BASE_ADDR),
		.length		= MX31_CS4_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= MX31_CS5_BASE_ADDR_VIRT,
		.pfn		= __phys_to_pfn(MX31_CS5_BASE_ADDR),
		.length		= MX31_CS5_SIZE,
		.type		= MT_DEVICE
	},
};

/*
 * Set up static virtual mappings.
 */
static void __init kzm_map_io(void)
{
	mx31_map_io();
	iotable_init(kzm_io_desc, ARRAY_SIZE(kzm_io_desc));
}

static void __init kzm_timer_init(void)
{
	mx31_clocks_init(26000000);
}

static struct sys_timer kzm_timer = {
	.init = kzm_timer_init,
};

MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01")
	.atag_offset = 0x100,
	.map_io = kzm_map_io,
	.init_early = imx31_init_early,
	.init_irq = mx31_init_irq,
	.handle_irq = imx31_handle_irq,
	.timer = &kzm_timer,
	.init_machine = kzm_board_init,
	.restart	= mxc_restart,
MACHINE_END
Commit	Line	Data
415c7d26 YY	1	/*
	2	* KZM-ARM11-01 support
	3	* Copyright (C) 2009 Yoichi Yuasa <yuasa@linux-mips.org>
	4	*
	5	* based on code for MX31ADS,
	6	* Copyright (C) 2000 Deep Blue Solutions Ltd
	7	* Copyright (C) 2002 Shane Nay (shane@minirl.com)
	8	* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; either version 2 of the License, or
	13	* (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
415c7d26 YY	19	*/
	20
	21	#include <linux/gpio.h>
	22	#include <linux/init.h>
	23	#include <linux/platform_device.h>
	24	#include <linux/serial_8250.h>
	25	#include <linux/smsc911x.h>
	26	#include <linux/types.h>
ccdf3278 FE	27	#include <linux/regulator/machine.h>
ccdf3278 FE	28	#include <linux/regulator/fixed.h>
415c7d26 YY	29
	30	#include <asm/irq.h>
	31	#include <asm/mach-types.h>
f4117ac9	32	#include <asm/memory.h>
415c7d26 YY	33	#include <asm/setup.h>
	34	#include <asm/mach/arch.h>
	35	#include <asm/mach/irq.h>
	36	#include <asm/mach/map.h>
	37	#include <asm/mach/time.h>
	38
415c7d26 YY	39	#include <mach/clock.h>
415c7d26 YY	40	#include <mach/common.h>
f2d9661b	41	#include <mach/hardware.h>
415c7d26	42	#include <mach/iomux-mx3.h>
415c7d26	43
16cf5c41	44	#include "devices-imx31.h"
415c7d26	45
f5d7a13b UKK	46	#define KZM_ARM11_IO_ADDRESS(x) (IOMEM( \
	47	IMX_IO_P2V_MODULE(x, MX31_CS4) ?: \
	48	IMX_IO_P2V_MODULE(x, MX31_CS5)) ?: \
59e26081 UKK	49	MX31_IO_ADDRESS(x))
59e26081 UKK	50
7b562d0f UKK	51	/*
	52	* KZM-ARM11-01 Board Control Registers on FPGA
	53	*/
	54	#define KZM_ARM11_CTL1 (MX31_CS4_BASE_ADDR + 0x1000)
	55	#define KZM_ARM11_CTL2 (MX31_CS4_BASE_ADDR + 0x1001)
	56	#define KZM_ARM11_RSW1 (MX31_CS4_BASE_ADDR + 0x1002)
	57	#define KZM_ARM11_BACK_LIGHT (MX31_CS4_BASE_ADDR + 0x1004)
	58	#define KZM_ARM11_FPGA_REV (MX31_CS4_BASE_ADDR + 0x1008)
	59	#define KZM_ARM11_7SEG_LED (MX31_CS4_BASE_ADDR + 0x1010)
	60	#define KZM_ARM11_LEDS (MX31_CS4_BASE_ADDR + 0x1020)
	61	#define KZM_ARM11_DIPSW2 (MX31_CS4_BASE_ADDR + 0x1003)
	62
	63	/*
	64	* External UART for touch panel on FPGA
	65	*/
	66	#define KZM_ARM11_16550 (MX31_CS4_BASE_ADDR + 0x1050)
	67
415c7d26 YY	68	#if defined(CONFIG_SERIAL_8250) \|\| defined(CONFIG_SERIAL_8250_MODULE)
	69	/*
	70	* KZM-ARM11-01 has an external UART on FPGA
	71	*/
	72	static struct plat_serial8250_port serial_platform_data[] = {
	73	{
59e26081	74	.membase = KZM_ARM11_IO_ADDRESS(KZM_ARM11_16550),
415c7d26	75	.mapbase = KZM_ARM11_16550,
ed175343	76	/* irq number is run-time assigned */
415c7d26 YY	77	.irqflags = IRQ_TYPE_EDGE_RISING,
	78	.uartclk = 14745600,
	79	.regshift = 0,
	80	.iotype = UPIO_MEM,
	81	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST \|
	82	UPF_BUGGY_UART,
	83	},
	84	{},
	85	};
	86
	87	static struct resource serial8250_resources[] = {
	88	{
	89	.start = KZM_ARM11_16550,
	90	.end = KZM_ARM11_16550 + 0x10,
	91	.flags = IORESOURCE_MEM,
	92	},
	93	{
ed175343	94	/* irq number is run-time assigned */
415c7d26 YY	95	.flags = IORESOURCE_IRQ,
	96	},
	97	};
	98
	99	static struct platform_device serial_device = {
	100	.name = "serial8250",
	101	.id = PLAT8250_DEV_PLATFORM,
	102	.dev = {
	103	.platform_data = serial_platform_data,
	104	},
	105	.num_resources = ARRAY_SIZE(serial8250_resources),
	106	.resource = serial8250_resources,
	107	};
	108
	109	static int __init kzm_init_ext_uart(void)
	110	{
	111	u8 tmp;
	112
	113	/*
	114	* GPIO 1-1: external UART interrupt line
	115	*/
	116	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO));
	117	gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "ext-uart-int");
	118	gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
	119
	120	/*
	121	* Unmask UART interrupt
	122	*/
59e26081	123	tmp = __raw_readb(KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1));
415c7d26	124	tmp \|= 0x2;
59e26081	125	__raw_writeb(tmp, KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1));
415c7d26	126
ed175343 SG	127	serial_platform_data[0].irq =
	128	gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
	129	serial8250_resources[1].start =
	130	gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
	131	serial8250_resources[1].end =
	132	gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
	133
415c7d26 YY	134	return platform_device_register(&serial_device);
	135	}
	136	#else
	137	static inline int kzm_init_ext_uart(void)
	138	{
	139	return 0;
	140	}
	141	#endif
	142
	143	/*
	144	* SMSC LAN9118
	145	*/
	146	#if defined(CONFIG_SMSC911X) \|\| defined(CONFIG_SMSC911X_MODULE)
	147	static struct smsc911x_platform_config kzm_smsc9118_config = {
	148	.phy_interface = PHY_INTERFACE_MODE_MII,
	149	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
	150	.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
	151	.flags = SMSC911X_USE_32BIT \| SMSC911X_SAVE_MAC_ADDRESS,
	152	};
	153
	154	static struct resource kzm_smsc9118_resources[] = {
	155	{
f568dd7f UKK	156	.start = MX31_CS5_BASE_ADDR,
f568dd7f UKK	157	.end = MX31_CS5_BASE_ADDR + SZ_128K - 1,
415c7d26 YY	158	.flags = IORESOURCE_MEM,
	159	},
	160	{
ed175343	161	/* irq number is run-time assigned */
415c7d26 YY	162	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_HIGHEDGE,
	163	},
	164	};
	165
	166	static struct platform_device kzm_smsc9118_device = {
	167	.name = "smsc911x",
	168	.id = -1,
	169	.num_resources = ARRAY_SIZE(kzm_smsc9118_resources),
	170	.resource = kzm_smsc9118_resources,
	171	.dev = {
	172	.platform_data = &kzm_smsc9118_config,
	173	},
	174	};
	175
ccdf3278 FE	176	static struct regulator_consumer_supply dummy_supplies[] = {
	177	REGULATOR_SUPPLY("vdd33a", "smsc911x"),
	178	REGULATOR_SUPPLY("vddvario", "smsc911x"),
	179	};
	180
415c7d26 YY	181	static int __init kzm_init_smsc9118(void)
	182	{
	183	/*
	184	* GPIO 1-2: SMSC9118 interrupt line
	185	*/
	186	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_2, IOMUX_CONFIG_GPIO));
	187	gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2), "smsc9118-int");
	188	gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2));
	189
ccdf3278 FE	190	regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
ccdf3278 FE	191
ed175343 SG	192	kzm_smsc9118_resources[1].start =
	193	gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2));
	194	kzm_smsc9118_resources[1].end =
	195	gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2));
	196
415c7d26 YY	197	return platform_device_register(&kzm_smsc9118_device);
	198	}
	199	#else
	200	static inline int kzm_init_smsc9118(void)
	201	{
	202	return 0;
	203	}
	204	#endif
	205
	206	#if defined(CONFIG_SERIAL_IMX) \|\| defined(CONFIG_SERIAL_IMX_MODULE)
16cf5c41	207	static const struct imxuart_platform_data uart_pdata __initconst = {
415c7d26 YY	208	.flags = IMXUART_HAVE_RTSCTS,
	209	};
	210
	211	static void __init kzm_init_imx_uart(void)
	212	{
16cf5c41 UKK	213	imx31_add_imx_uart0(&uart_pdata);
16cf5c41 UKK	214	imx31_add_imx_uart1(&uart_pdata);
415c7d26 YY	215	}
	216	#else
	217	static inline void kzm_init_imx_uart(void)
	218	{
	219	}
	220	#endif
	221
	222	static int kzm_pins[] __initdata = {
	223	MX31_PIN_CTS1__CTS1,
	224	MX31_PIN_RTS1__RTS1,
	225	MX31_PIN_TXD1__TXD1,
	226	MX31_PIN_RXD1__RXD1,
	227	MX31_PIN_DCD_DCE1__DCD_DCE1,
	228	MX31_PIN_RI_DCE1__RI_DCE1,
	229	MX31_PIN_DSR_DCE1__DSR_DCE1,
	230	MX31_PIN_DTR_DCE1__DTR_DCE1,
	231	MX31_PIN_CTS2__CTS2,
	232	MX31_PIN_RTS2__RTS2,
	233	MX31_PIN_TXD2__TXD2,
	234	MX31_PIN_RXD2__RXD2,
	235	MX31_PIN_DCD_DTE1__DCD_DTE2,
	236	MX31_PIN_RI_DTE1__RI_DTE2,
	237	MX31_PIN_DSR_DTE1__DSR_DTE2,
	238	MX31_PIN_DTR_DTE1__DTR_DTE2,
	239	};
	240
	241	/*
	242	* Board specific initialization.
	243	*/
	244	static void __init kzm_board_init(void)
	245	{
b78d8e59 SG	246	imx31_soc_init();
b78d8e59 SG	247
415c7d26 YY	248	mxc_iomux_setup_multiple_pins(kzm_pins,
	249	ARRAY_SIZE(kzm_pins), "kzm");
	250	kzm_init_ext_uart();
	251	kzm_init_smsc9118();
	252	kzm_init_imx_uart();
	253
	254	pr_info("Clock input source is 26MHz\n");
	255	}
	256
	257	/*
	258	* This structure defines static mappings for the kzm-arm11-01 board.
	259	*/
	260	static struct map_desc kzm_io_desc[] __initdata = {
	261	{
f568dd7f UKK	262	.virtual = MX31_CS4_BASE_ADDR_VIRT,
	263	.pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
	264	.length = MX31_CS4_SIZE,
415c7d26 YY	265	.type = MT_DEVICE
	266	},
	267	{
f568dd7f UKK	268	.virtual = MX31_CS5_BASE_ADDR_VIRT,
	269	.pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
	270	.length = MX31_CS5_SIZE,
415c7d26 YY	271	.type = MT_DEVICE
	272	},
	273	};
	274
	275	/*
	276	* Set up static virtual mappings.
	277	*/
	278	static void __init kzm_map_io(void)
	279	{
	280	mx31_map_io();
	281	iotable_init(kzm_io_desc, ARRAY_SIZE(kzm_io_desc));
	282	}
	283
	284	static void __init kzm_timer_init(void)
	285	{
	286	mx31_clocks_init(26000000);
	287	}
	288
	289	static struct sys_timer kzm_timer = {
e134fb2b	290	.init = kzm_timer_init,
415c7d26 YY	291	};
415c7d26 YY	292
415c7d26	293	MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01")
dc8f1907	294	.atag_offset = 0x100,
97976e22 UKK	295	.map_io = kzm_map_io,
	296	.init_early = imx31_init_early,
	297	.init_irq = mx31_init_irq,
ffa2ea3f	298	.handle_irq = imx31_handle_irq,
97976e22 UKK	299	.timer = &kzm_timer,
97976e22 UKK	300	.init_machine = kzm_board_init,
65ea7884	301	.restart = mxc_restart,
415c7d26	302	MACHINE_END