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6b91edde IC |
1 | /* |
2 | * Copyright (C) 2000 Deep Blue Solutions Ltd | |
3 | * Copyright (C) 2002 Shane Nay (shane@minirl.com) | |
4 | * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
6b91edde IC |
15 | */ |
16 | ||
17 | #include <linux/platform_device.h> | |
18 | #include <linux/mtd/mtd.h> | |
19 | #include <linux/mtd/physmap.h> | |
20 | #include <linux/gpio.h> | |
21 | #include <mach/common.h> | |
22 | #include <mach/hardware.h> | |
23 | #include <asm/mach-types.h> | |
24 | #include <asm/mach/arch.h> | |
25 | #include <asm/mach/time.h> | |
26 | #include <asm/mach/map.h> | |
e835d88e | 27 | #include <mach/iomux-mx21.h> |
6b91edde | 28 | |
1f8d721c | 29 | #include "devices-imx21.h" |
6b91edde | 30 | |
d393d43f UKK |
31 | /* |
32 | * Memory-mapped I/O on MX21ADS base board | |
33 | */ | |
34 | #define MX21ADS_MMIO_BASE_ADDR 0xf5000000 | |
350ab15b | 35 | #define MX21ADS_MMIO_SIZE 0xc00000 |
d393d43f UKK |
36 | |
37 | #define MX21ADS_REG_ADDR(offset) (void __force __iomem *) \ | |
38 | (MX21ADS_MMIO_BASE_ADDR + (offset)) | |
39 | ||
c8c9e837 | 40 | #define MX21ADS_CS8900A_MMIO_SIZE 0x200000 |
d393d43f | 41 | #define MX21ADS_CS8900A_IRQ IRQ_GPIOE(11) |
d393d43f UKK |
42 | #define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000) |
43 | #define MX21ADS_VERSION_REG MX21ADS_REG_ADDR(0x400000) | |
44 | #define MX21ADS_IO_REG MX21ADS_REG_ADDR(0x800000) | |
45 | ||
46 | /* MX21ADS_IO_REG bit definitions */ | |
47 | #define MX21ADS_IO_SD_WP 0x0001 /* read */ | |
48 | #define MX21ADS_IO_TP6 0x0001 /* write */ | |
49 | #define MX21ADS_IO_SW_SEL 0x0002 /* read */ | |
50 | #define MX21ADS_IO_TP7 0x0002 /* write */ | |
51 | #define MX21ADS_IO_RESET_E_UART 0x0004 | |
52 | #define MX21ADS_IO_RESET_BASE 0x0008 | |
53 | #define MX21ADS_IO_CSI_CTL2 0x0010 | |
54 | #define MX21ADS_IO_CSI_CTL1 0x0020 | |
55 | #define MX21ADS_IO_CSI_CTL0 0x0040 | |
56 | #define MX21ADS_IO_UART1_EN 0x0080 | |
57 | #define MX21ADS_IO_UART4_EN 0x0100 | |
58 | #define MX21ADS_IO_LCDON 0x0200 | |
59 | #define MX21ADS_IO_IRDA_EN 0x0400 | |
60 | #define MX21ADS_IO_IRDA_FIR_SEL 0x0800 | |
61 | #define MX21ADS_IO_IRDA_MD0_B 0x1000 | |
62 | #define MX21ADS_IO_IRDA_MD1 0x2000 | |
63 | #define MX21ADS_IO_LED4_ON 0x4000 | |
64 | #define MX21ADS_IO_LED3_ON 0x8000 | |
65 | ||
6c80ee51 | 66 | static const int mx21ads_pins[] __initconst = { |
6b91edde IC |
67 | |
68 | /* CS8900A */ | |
69 | (GPIO_PORTE | GPIO_GPIO | GPIO_IN | 11), | |
70 | ||
71 | /* UART1 */ | |
72 | PE12_PF_UART1_TXD, | |
73 | PE13_PF_UART1_RXD, | |
74 | PE14_PF_UART1_CTS, | |
75 | PE15_PF_UART1_RTS, | |
76 | ||
77 | /* UART3 (IrDA) - only TXD and RXD */ | |
78 | PE8_PF_UART3_TXD, | |
79 | PE9_PF_UART3_RXD, | |
80 | ||
81 | /* UART4 */ | |
82 | PB26_AF_UART4_RTS, | |
83 | PB28_AF_UART4_TXD, | |
84 | PB29_AF_UART4_CTS, | |
85 | PB31_AF_UART4_RXD, | |
86 | ||
87 | /* LCDC */ | |
88 | PA5_PF_LSCLK, | |
89 | PA6_PF_LD0, | |
90 | PA7_PF_LD1, | |
91 | PA8_PF_LD2, | |
92 | PA9_PF_LD3, | |
93 | PA10_PF_LD4, | |
94 | PA11_PF_LD5, | |
95 | PA12_PF_LD6, | |
96 | PA13_PF_LD7, | |
97 | PA14_PF_LD8, | |
98 | PA15_PF_LD9, | |
99 | PA16_PF_LD10, | |
100 | PA17_PF_LD11, | |
101 | PA18_PF_LD12, | |
102 | PA19_PF_LD13, | |
103 | PA20_PF_LD14, | |
104 | PA21_PF_LD15, | |
105 | PA22_PF_LD16, | |
106 | PA24_PF_REV, /* Sharp panel dedicated signal */ | |
107 | PA25_PF_CLS, /* Sharp panel dedicated signal */ | |
108 | PA26_PF_PS, /* Sharp panel dedicated signal */ | |
109 | PA27_PF_SPL_SPR, /* Sharp panel dedicated signal */ | |
110 | PA28_PF_HSYNC, | |
111 | PA29_PF_VSYNC, | |
112 | PA30_PF_CONTRAST, | |
113 | PA31_PF_OE_ACD, | |
114 | ||
115 | /* MMC/SDHC */ | |
116 | PE18_PF_SD1_D0, | |
117 | PE19_PF_SD1_D1, | |
118 | PE20_PF_SD1_D2, | |
119 | PE21_PF_SD1_D3, | |
120 | PE22_PF_SD1_CMD, | |
121 | PE23_PF_SD1_CLK, | |
122 | ||
123 | /* NFC */ | |
124 | PF0_PF_NRFB, | |
125 | PF1_PF_NFCE, | |
126 | PF2_PF_NFWP, | |
127 | PF3_PF_NFCLE, | |
128 | PF4_PF_NFALE, | |
129 | PF5_PF_NFRE, | |
130 | PF6_PF_NFWE, | |
131 | PF7_PF_NFIO0, | |
132 | PF8_PF_NFIO1, | |
133 | PF9_PF_NFIO2, | |
134 | PF10_PF_NFIO3, | |
135 | PF11_PF_NFIO4, | |
136 | PF12_PF_NFIO5, | |
137 | PF13_PF_NFIO6, | |
138 | PF14_PF_NFIO7, | |
139 | }; | |
140 | ||
141 | /* ADS's NOR flash: 2x AM29BDS128HE9VKI on 32-bit bus */ | |
142 | static struct physmap_flash_data mx21ads_flash_data = { | |
143 | .width = 4, | |
144 | }; | |
145 | ||
146 | static struct resource mx21ads_flash_resource = { | |
3f35d1f5 UKK |
147 | .start = MX21_CS0_BASE_ADDR, |
148 | .end = MX21_CS0_BASE_ADDR + 0x02000000 - 1, | |
6b91edde IC |
149 | .flags = IORESOURCE_MEM, |
150 | }; | |
151 | ||
152 | static struct platform_device mx21ads_nor_mtd_device = { | |
153 | .name = "physmap-flash", | |
154 | .id = 0, | |
155 | .dev = { | |
156 | .platform_data = &mx21ads_flash_data, | |
157 | }, | |
158 | .num_resources = 1, | |
159 | .resource = &mx21ads_flash_resource, | |
160 | }; | |
161 | ||
c8c9e837 JB |
162 | static const struct resource mx21ads_cs8900_resources[] __initconst = { |
163 | DEFINE_RES_MEM(MX21_CS1_BASE_ADDR, MX21ADS_CS8900A_MMIO_SIZE), | |
164 | DEFINE_RES_IRQ(MX21ADS_CS8900A_IRQ), | |
165 | }; | |
166 | ||
167 | static const struct platform_device_info mx21ads_cs8900_devinfo __initconst = { | |
168 | .name = "cs89x0", | |
169 | .id = 0, | |
170 | .res = mx21ads_cs8900_resources, | |
171 | .num_res = ARRAY_SIZE(mx21ads_cs8900_resources), | |
172 | }; | |
173 | ||
3c5227fd | 174 | static const struct imxuart_platform_data uart_pdata_rts __initconst = { |
6b91edde IC |
175 | .flags = IMXUART_HAVE_RTSCTS, |
176 | }; | |
177 | ||
3c5227fd | 178 | static const struct imxuart_platform_data uart_pdata_norts __initconst = { |
6b91edde IC |
179 | }; |
180 | ||
6b91edde IC |
181 | static int mx21ads_fb_init(struct platform_device *pdev) |
182 | { | |
183 | u16 tmp; | |
184 | ||
185 | tmp = __raw_readw(MX21ADS_IO_REG); | |
186 | tmp |= MX21ADS_IO_LCDON; | |
187 | __raw_writew(tmp, MX21ADS_IO_REG); | |
188 | return 0; | |
189 | } | |
190 | ||
191 | static void mx21ads_fb_exit(struct platform_device *pdev) | |
192 | { | |
193 | u16 tmp; | |
194 | ||
195 | tmp = __raw_readw(MX21ADS_IO_REG); | |
196 | tmp &= ~MX21ADS_IO_LCDON; | |
197 | __raw_writew(tmp, MX21ADS_IO_REG); | |
198 | } | |
199 | ||
200 | /* | |
201 | * Connected is a portrait Sharp-QVGA display | |
202 | * of type: LQ035Q7DB02 | |
203 | */ | |
c35d3a41 SH |
204 | static struct imx_fb_videomode mx21ads_modes[] = { |
205 | { | |
206 | .mode = { | |
207 | .name = "Sharp-LQ035Q7", | |
208 | .refresh = 60, | |
209 | .xres = 240, | |
210 | .yres = 320, | |
211 | .pixclock = 188679, /* in ps (5.3MHz) */ | |
212 | .hsync_len = 2, | |
213 | .left_margin = 6, | |
214 | .right_margin = 16, | |
215 | .vsync_len = 1, | |
216 | .upper_margin = 8, | |
217 | .lower_margin = 10, | |
218 | }, | |
219 | .pcr = 0xfb108bc7, | |
220 | .bpp = 16, | |
221 | }, | |
222 | }; | |
223 | ||
ad851bff | 224 | static const struct imx_fb_platform_data mx21ads_fb_data __initconst = { |
c35d3a41 SH |
225 | .mode = mx21ads_modes, |
226 | .num_modes = ARRAY_SIZE(mx21ads_modes), | |
227 | ||
228 | .pwmr = 0x00a903ff, | |
229 | .lscr1 = 0x00120300, | |
230 | .dmacr = 0x00020008, | |
6b91edde IC |
231 | |
232 | .init = mx21ads_fb_init, | |
233 | .exit = mx21ads_fb_exit, | |
234 | }; | |
235 | ||
236 | static int mx21ads_sdhc_get_ro(struct device *dev) | |
237 | { | |
238 | return (__raw_readw(MX21ADS_IO_REG) & MX21ADS_IO_SD_WP) ? 1 : 0; | |
239 | } | |
240 | ||
241 | static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq, | |
242 | void *data) | |
243 | { | |
9d3d945a | 244 | return request_irq(IRQ_GPIOD(25), detect_irq, |
6b91edde | 245 | IRQF_TRIGGER_FALLING, "mmc-detect", data); |
6b91edde IC |
246 | } |
247 | ||
248 | static void mx21ads_sdhc_exit(struct device *dev, void *data) | |
249 | { | |
250 | free_irq(IRQ_GPIOD(25), data); | |
251 | } | |
252 | ||
9d3d945a | 253 | static const struct imxmmc_platform_data mx21ads_sdhc_pdata __initconst = { |
6b91edde IC |
254 | .ocr_avail = MMC_VDD_29_30 | MMC_VDD_30_31, /* 3.0V */ |
255 | .get_ro = mx21ads_sdhc_get_ro, | |
256 | .init = mx21ads_sdhc_init, | |
257 | .exit = mx21ads_sdhc_exit, | |
258 | }; | |
259 | ||
1f8d721c UKK |
260 | static const struct mxc_nand_platform_data |
261 | mx21ads_nand_board_info __initconst = { | |
6b91edde IC |
262 | .width = 1, |
263 | .hw_ecc = 1, | |
264 | }; | |
265 | ||
266 | static struct map_desc mx21ads_io_desc[] __initdata = { | |
267 | /* | |
268 | * Memory-mapped I/O on MX21ADS Base board: | |
269 | * - CS8900A Ethernet controller | |
270 | * - ST16C2552CJ UART | |
271 | * - CPU and Base board version | |
272 | * - Base board I/O register | |
273 | */ | |
274 | { | |
275 | .virtual = MX21ADS_MMIO_BASE_ADDR, | |
3f35d1f5 | 276 | .pfn = __phys_to_pfn(MX21_CS1_BASE_ADDR), |
6b91edde IC |
277 | .length = MX21ADS_MMIO_SIZE, |
278 | .type = MT_DEVICE, | |
279 | }, | |
280 | }; | |
281 | ||
282 | static void __init mx21ads_map_io(void) | |
283 | { | |
284 | mx21_map_io(); | |
285 | iotable_init(mx21ads_io_desc, ARRAY_SIZE(mx21ads_io_desc)); | |
286 | } | |
287 | ||
288 | static struct platform_device *platform_devices[] __initdata = { | |
289 | &mx21ads_nor_mtd_device, | |
290 | }; | |
291 | ||
292 | static void __init mx21ads_board_init(void) | |
293 | { | |
b78d8e59 SG |
294 | imx21_soc_init(); |
295 | ||
6b91edde IC |
296 | mxc_gpio_setup_multiple_pins(mx21ads_pins, ARRAY_SIZE(mx21ads_pins), |
297 | "mx21ads"); | |
298 | ||
3c5227fd UKK |
299 | imx21_add_imx_uart0(&uart_pdata_rts); |
300 | imx21_add_imx_uart2(&uart_pdata_norts); | |
301 | imx21_add_imx_uart3(&uart_pdata_rts); | |
ad851bff | 302 | imx21_add_imx_fb(&mx21ads_fb_data); |
9d3d945a | 303 | imx21_add_mxc_mmc(0, &mx21ads_sdhc_pdata); |
1f8d721c | 304 | imx21_add_mxc_nand(&mx21ads_nand_board_info); |
6b91edde IC |
305 | |
306 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); | |
d5be0d73 | 307 | platform_device_register_full(&mx21ads_cs8900_devinfo); |
6b91edde IC |
308 | } |
309 | ||
310 | static void __init mx21ads_timer_init(void) | |
311 | { | |
312 | mx21_clocks_init(32768, 26000000); | |
313 | } | |
314 | ||
315 | static struct sys_timer mx21ads_timer = { | |
316 | .init = mx21ads_timer_init, | |
317 | }; | |
318 | ||
319 | MACHINE_START(MX21ADS, "Freescale i.MX21ADS") | |
320 | /* maintainer: Freescale Semiconductor, Inc. */ | |
dc8f1907 | 321 | .atag_offset = 0x100, |
3dac2196 UKK |
322 | .map_io = mx21ads_map_io, |
323 | .init_early = imx21_init_early, | |
324 | .init_irq = mx21_init_irq, | |
ffa2ea3f | 325 | .handle_irq = imx21_handle_irq, |
3dac2196 UKK |
326 | .timer = &mx21ads_timer, |
327 | .init_machine = mx21ads_board_init, | |
65ea7884 | 328 | .restart = mxc_restart, |
6b91edde | 329 | MACHINE_END |